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    • 35. 发明授权
    • METHOD OF MANUFACTURING AN ELECTRONIC POWER DEVICE MONOLITHICALLY INTEGRATED ON A SEMICONDUCTOR AND COMPRISING A FIRST POWER REGION, A SECOND REGION, AND AN ISOLATION STRUCTURE OF LIMITED PLANAR DIMENSION
    • 制造一体化集成在半导体上并包含第一电源区域,第二区域以及有限平面尺寸的隔离结构的电子设备的方法
    • US06693019B2
    • 2004-02-17
    • US10213016
    • 2002-08-05
    • Salvatore Leonardi
    • Salvatore Leonardi
    • H01L2176
    • H01L21/76208H01L21/761H01L27/088
    • An electronic power device is integrated monolithically in a semiconductor substrate. The device has a first power region and a second region, each region including P/N junction formed of a first semiconductor region with a first type of conductivity, which first semiconductor region extends through the substrate from the top surface of the device and is diffused into a second semiconductor region with the opposite conductivity from the first. The device also includes an interface structure between the two regions, of substantial thickness and limited planar size, that includes a trench filled with dielectric material. A method of manufacturing the electronic power device includes forming a silicon oxide-filled trench. The method includes forming, in the substrate, a plurality of small trenches having predetermined widths and -being delimited by a corresponding plurality of semiconductor material walls having second predetermined widths. Next, the semiconductor is oxidized by a thermal process directed to oxidize the walls which produces a single trench.
    • 电子功率器件整体地集成在半导体衬底中。 该器件具有第一功率区和第二区,每个区域包括由具有第一导电类型的第一半导体区域形成的P / N结,该第一半导体区域从器件的顶表面延伸穿过衬底并被扩散 进入具有与第一半导体相反的导电性的第二半导体区域。 该装置还包括两个区域之间的界面结构,其具有相当大的厚度和有限的平面尺寸,其包括填充有电介质材料的沟槽。 一种制造电子功率器件的方法包括形成填充氧化硅的沟槽。 该方法包括在衬底中形成具有预定宽度的多个小沟槽,并且由相应的具有第二预定宽度的多个半导体材料壁界定。 接下来,半导体被热处理氧化,以产生单个沟槽的氧化壁。
    • 37. 发明授权
    • Semiconductor power device with insulated circuit
    • 具有绝缘电路的半导体功率器件
    • US06525392B1
    • 2003-02-25
    • US09352477
    • 1999-07-13
    • Salvatore Leonardi
    • Salvatore Leonardi
    • H01L2707
    • H01L21/7624H01L21/762
    • A semiconductor power device with an insulated control circuit is formed in a chip of semiconductor material having predominantly a first type of conductivity. The device includes a region having a second type of conductivity, buried in the semiconductor material, and at least one insulated region of semiconductor material, containing at least part of the control circuit, disposed between the front surface of the chip and the buried region. The device also includes electrical contacts for the buried region and the semiconductor material. To eliminate the effects of parasitic components, the insulated region is delimited, at least partially, by an insulating dielectric material.
    • 具有绝缘控制电路的半导体功率器件形成在主要具有第一类导电性的半导体材料的芯片中。 该器件包括埋置在半导体材料中的第二导电类型的区域和至少一个半导体材料的绝缘区域,该半导体材料的绝缘区域包含设置在芯片的前表面和掩埋区域之间的控制电路的至少一部分。 该器件还包括用于掩埋区域和半导体材料的电触点。 为了消除寄生成分的影响,绝缘区域至少部分由绝缘电介质材料界定。
    • 38. 发明授权
    • Monolithically integrated device with protective structure
    • 具有保护结构的单片集成器件
    • US6121640A
    • 2000-09-19
    • US336639
    • 1999-06-18
    • Salvatore Leonardi
    • Salvatore Leonardi
    • H01L27/06H01L27/07H01L29/74H01L31/111
    • H01L27/0716H01L27/0635H01L29/7302H01L29/739H01L29/7803H01L29/7808
    • A monolithic integrated device includes a protection structure and is formed in a semiconductor material substrate having a first conductivity type, which device includes at least a first epitaxial layer formed on the substrate. The integrated device further includes a bipolar first transistor formed of a base region having a second conductivity type and including a first buried region formed in the first epitaxial layer, and having a first diffused region which extends from the first buried region to contact a top surface of the integrated device through a surface contact region with a high concentration of dopant material. The first transistor also has an emitter region with the first conductivity type, embedded in the base region, and including a second buried region formed on the first buried region and a second diffused region, with a high concentration of dopant material, which extends from the second buried region to contact the top surface of the integrated device. The integrated device additionally comprises a second transistor of the MOS type having a drain region formed in the emitter region of the first transistor, said drain region incorporating a third diffused region with a high concentration of dopant material and the first conductivity type which includes a source region of the second transistor. The protection structure is formed of the overlap of the surface contact region and at least one of the diffused regions with a high concentration of dopant material to provide a low breakdown voltage junction of the Zener type.
    • 单片集成器件包括保护结构,并形成在具有第一导电类型的半导体材料衬底中,该器件至少包括形成在衬底上的第一外延层。 集成器件还包括由具有第二导电类型的基极区形成的双极性第一晶体管,并且包括形成在第一外延层中的第一掩埋区,并且具有从第一掩埋区延伸以接触顶表面的第一扩散区 的集成器件通过具有高浓度掺杂剂材料的表面接触区域。 第一晶体管还具有第一导电类型的发射极区域,嵌入在基极区域中,并且包括形成在第一掩埋区域上的第二掩埋区域和具有高浓度掺杂剂材料的第二扩散区域,其从 第二掩埋区域以与集成器件的顶面接触。 集成器件还包括MOS型的第二晶体管,其具有形成在第一晶体管的发射极区域中的漏极区域,所述漏极区域包含具有高浓度掺杂剂材料的第三扩散区域,并且第一导电类型包括源极 第二晶体管的区域。 保护结构由表面接触区域和至少一个扩散区域与高浓度掺杂剂材料的重叠形成,以提供齐纳二极型的低击穿电压结。