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31. 发明申请

US20090049341A1 Method for Performing Memory Diagnostics Using a Programmable Diagnostic Memory Module 失效
标题翻译：使用可编程诊断内存模块执行内存诊断的方法
公开(公告)号：US20090049341A1
公开(公告)日：2009-02-19
申请号：US11840498
申请日：2007-08-17
申请人： Moises Cases , Daniel Mark Dreps , Bhyrav M. Mutnury , Nam H. Pham , Daniel N. De Araujo
发明人： Moises Cases , Daniel Mark Dreps , Bhyrav M. Mutnury , Nam H. Pham , Daniel N. De Araujo
IPC分类号： G06F11/26 , G06F9/455
CPC分类号： G06F11/24
摘要： A method for performing memory diagnostics using a programmable diagnostic memory module provides enhanced testability of memory controller and memory subsystem design. The programmable diagnostic memory module includes an interface for communicating with an external diagnostic system, and the interface is used to transfer commands to the memory module to alter various behaviors of the memory module. The altered behaviors may be changing data streams that are written to the memory module to simulate errors, altering the timing and/or loading of the memory module signals, downloading programs for execution by a processor core within the memory module, changing driver strengths of output signals of the memory module, and manipulating in an analog domain, signals at terminals of the memory module such as injecting noise on power supply connections to the memory module. The memory module may emulate multiple selectable memory module types, and may include a complete storage array to provide standard memory module operation.
摘要翻译：使用可编程诊断存储器模块执行存储器诊断的方法提供了存储器控制器和存储器子系统设计的增强的可测试性。可编程诊断存储器模块包括用于与外部诊断系统通信的接口，并且该接口用于将命令传送到存储器模块以改变存储器模块的各种行为。改变的行为可能是改变被写入存储器模块的数据流，以模拟错误，改变存储器模块信号的定时和/或加载，下载由存储器模块内的处理器核心执行的程序，改变驱动器的输出强度存储器模块的信号和在模拟域中的操作，在存储器模块的端子处发出信号，例如在与存储器模块的电源连接上注入噪声。存储器模块可以模拟多个可选择的存储器模块类型，并且可以包括完整的存储阵列以提供标准存储器模块操作。

32. 发明申请

US20090021264A1 METHOD AND APPARATUS FOR REPEATABLE DRIVE STRENGTH ASSESSMENTS OF HIGH SPEED MEMORY DIMMS 有权
标题翻译：用于高速记忆体可重复驱动强度评估的方法和装置
公开(公告)号：US20090021264A1
公开(公告)日：2009-01-22
申请号：US11780505
申请日：2007-07-20
申请人： Moises Cases , Daniel N. de Araujo , Bradley D. Herrman , Erdem Matoglu , Bhyrav M. Mutnury , Pravin Patel , Nam H. Pham
发明人： Moises Cases , Daniel N. de Araujo , Bradley D. Herrman , Erdem Matoglu , Bhyrav M. Mutnury , Pravin Patel , Nam H. Pham
IPC分类号： G01R31/02 , G06F11/00
CPC分类号： G01R31/2815 , G01R31/304 , G11C29/02 , G11C29/022 , G11C29/56 , G11C2029/5602
摘要： The present invention assesses memory (DIMM) strength by calculating frequency content of a radiated field which is collected by an apparatus, such as a dipole antenna. Radiated field is created by accelerated charge, which is a function of the slew rate or DIMM strength. Radiated power is directly proportional to the frequency at which bits are driven. By separating the radiated field from the near field or stored field, the DIMM strength content is isolated from other functional DIMM issues, such as tRCD latency, refresh cycles, addressing mode, etc. By examining the radiated power, the disadvantages of the prior art, such as by probing the DIMM's contacts, are avoided.
摘要翻译：本发明通过计算由诸如偶极天线的装置收集的辐射场的频率内容来评估存储器（DIMM）强度。辐射场由加速电荷产生，这是压摆率或DIMM强度的函数。辐射功率与驱动位的频率成正比。通过将辐射场与近场或存储场分离，DIMM强度内容与其他功能性DIMM问题（例如tRCD延迟，刷新周期，寻址模式等）隔离。通过检查辐射功率，现有技术的缺点，例如通过探测DIMM的触点。

33. 发明授权

US07443180B2 On-chip probing apparatus 失效
标题翻译：片上探测装置
公开(公告)号：US07443180B2
公开(公告)日：2008-10-28
申请号：US11567449
申请日：2006-12-06
申请人： Moises Cases , Daniel N. de Araujo , Bradley D. Herrman , Erdem Matoglu , Bhyrav M. Mutnury , Pravin S. Patel , Nam H. Pham
发明人： Moises Cases , Daniel N. de Araujo , Bradley D. Herrman , Erdem Matoglu , Bhyrav M. Mutnury , Pravin S. Patel , Nam H. Pham
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： G01R31/31723 , G01R31/2884 , G01R31/31926
摘要： The invention is directed to an on-chip probing apparatus. In accordance with an embodiment of the present invention, the on-chip probing apparatus includes: a plurality of switches on a chip; a plurality of externally accessible probe points on the chip; and a multiplexer for controlling the plurality of switches to selectively couple an output signal of the chip to one of the plurality of probe points.
摘要翻译：本发明涉及片上探测装置。根据本发明的实施例，片上探测装置包括：芯片上的多个开关; 芯片上的多个外部可访问的探针点; 以及多路复用器，用于控制所述多个开关以选择性地将所述芯片的输出信号耦合到所述多个探针点中的一个。

34. 发明申请

US20080258755A1 Noise Reduction Among Conductors 审中-公开
标题翻译：导体之间的降噪
公开(公告)号：US20080258755A1
公开(公告)日：2008-10-23
申请号：US11737355
申请日：2007-04-19
申请人： Moises Cases , Daniel N. de Araujo , Bhyrav M. Mutnury , Nam H. Pham
发明人： Moises Cases , Daniel N. de Araujo , Bhyrav M. Mutnury , Nam H. Pham
IPC分类号： H03K17/16
CPC分类号： H04B3/32 , H03K2005/00019 , H03K2005/00156
摘要： Noise reduction among conductors, the conductors disposed adjacent to one another, the conductors characterized as two or more aggressor conductors and one or more victim conductors, a least two of the aggressor conductors driven with at least two signals that induce unwanted crosstalk upon at least one of the victim conductors, a programmable delay device disposed in a signal path of each of the at least two signals that induce unwanted crosstalk, including programming a delay period into each programmable delay device; receiving, simultaneously at the programmable delay devices, the at least two signals that induce unwanted crosstalk; and transmitting, on two aggressor conductors, the at least two signals that induce unwanted crosstalk, with the at least two signals separated in time by the delay period.
摘要翻译：导体之间的噪声降低，导体彼此相邻布置，导体表征为两个或多个侵略导体和一个或多个受害导体，至少两个侵略体导体用至少两个信号驱动，这些信号在至少一个所述可编程延迟装置设置在所述至少两个信号中的每一个的信号路径中，所述至少两个信号引起不需要的串扰，包括将延迟周期编程到每个可编程延迟装置中; 同时在可编程延迟装置处接收至少两个引起不想要的串扰的信号; 以及在两个侵略者导体上传输引起不想要的串扰的至少两个信号，其中至少两个信号在时间上与延迟周期分开。

35. 发明申请

US20080155149A1 MULTI-PATH REDUNDANT ARCHITECTURE FOR FAULT TOLERANT FULLY BUFFERED DIMMS 审中-公开
标题翻译：多路径冗余架构，用于故障的全面缓冲区
公开(公告)号：US20080155149A1
公开(公告)日：2008-06-26
申请号：US11613363
申请日：2006-12-20
申请人： Daniel N. de Araujo , Moises Cases , Erdem Matoglu , Nam H. Pham
发明人： Daniel N. de Araujo , Moises Cases , Erdem Matoglu , Nam H. Pham
IPC分类号： G06F13/16
CPC分类号： G06F11/2007
摘要： The present invention is directed to a multi-path redundant architecture for fault tolerant fully buffered dual inline memory modules (FB-DIMMs). The architecture includes: a FB-DIMM channel including a plurality of DIMM modules and a memory controller; a bidirectional serial memory bus for coupling the memory controller and the plurality of DIMM modules of the FB-DIMM channel in a first connection order; and a redundant bidirectional serial memory bus for coupling the memory controller and the plurality of DIMM modules of the FB-DIMM channel in a second connection order
摘要翻译：本发明涉及用于容错全缓冲双列直插式存储器模块（FB-DIMM）的多路径冗余架构。该架构包括：包括多个DIMM模块的FB-DIMM通道和存储器控制器; 用于以第一连接顺序耦合存储器控制器和FB-DIMM通道的多个DIMM模块的双向串行存储器总线; 以及用于以第二连接顺序耦合存储器控制器和FB-DIMM通道的多个DIMM模块的冗余双向串行存储器总线

36. 发明授权

US10141086B2 Cable for high speed data communications 有权
公开(公告)号：US10141086B2
公开(公告)日：2018-11-27
申请号：US12628245
申请日：2009-12-01
申请人： Moises Cases , Vinh B. Lu , Bhyrav M. Mutnury
发明人： Moises Cases , Vinh B. Lu , Bhyrav M. Mutnury
IPC分类号： H01B7/00 , H01B11/20 , H01B11/10 , H01P3/06
摘要： A cable for high speed data communications is provided. The cable includes a first inner conductor enclosed by a first dielectric layer and a second inner conductor enclosed by a second dielectric layer. The first inner conductor is substantially parallel to the second inner conductor and to a longitudinal axis. The cable includes a conductive shield wrapped around the first and second inner conductors, with an overlap of the conductive shield along and about the longitudinal axis. The overlap is aligned with a low current plane. The low current plane is substantially parallel to the first and second inner conductors, substantially equidistant from the first and second inner conductors, and substantially orthogonal to a plane including the first and second inner conductors.

37. 发明授权

US08830690B2 Minimizing plating stub reflections in a chip package using capacitance 有权
标题翻译：使用电容最小化芯片封装中的电镀短截线反射
公开(公告)号：US08830690B2
公开(公告)日：2014-09-09
申请号：US12237444
申请日：2008-09-25
申请人： Bhyrav M Mutnury , Moises Cases , Nanju Na , Tae Hong Kim
发明人： Bhyrav M Mutnury , Moises Cases , Nanju Na , Tae Hong Kim
IPC分类号： H05K1/18 , H05K1/02 , H05K1/16 , H05K3/24
CPC分类号： H01L21/4853 , C25D5/02 , H01L24/73 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/14 , H01L2924/15311 , H05K1/0231 , H05K1/162 , H05K3/242 , H05K2203/049 , H01L2924/00012 , H01L2924/00
摘要： Embodiments of the present invention are directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A first outer layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A capacitor is used to capacitively couple the plating stub to a ground layer.
摘要翻译：本发明的实施例涉及通过连接开放式电镀短截线和接地之间的电容来将高频芯片封装中的谐振频率从工作频率移开。一个实施例提供了用于将芯片与印刷电路板接口的多层基板。第一外层提供了芯片安装位置。信号互连与芯片安装位置间隔开，并且信号迹线从芯片安装位置附近延伸到信号互连。安装在芯片安装位置的芯片可以通过引线键合连接到信号迹线。电镀短截线从信号互连延伸到衬底的周围。电容器用于将电镀端子电容耦合到接地层。

38. 发明授权

US08453081B2 Electrical design space exploration 失效
标题翻译：电气设计空间探索
公开(公告)号：US08453081B2
公开(公告)日：2013-05-28
申请号：US12784150
申请日：2010-05-20
申请人： Moises Cases , Jinwoo Choi , Bhyrav M. Mutnury , Caleb J. Wesley
发明人： Moises Cases , Jinwoo Choi , Bhyrav M. Mutnury , Caleb J. Wesley
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F2217/08
摘要： A method for electrical design space exploration includes receiving a template for an electrical design. Design component parameters associated with at least one component in the electrical design are also received. Weighted factors are assigned to design complexity parameters of the electrical design. The parameters of the complexity can include at least one of following: whether the electrical design is known, a number of the design component parameters, a level of interaction among the design component parameters, a time constraint and a memory restriction of a simulation, and whether a statistical analysis or a worst case approach is used to analyze an output of the simulation. A simulation approach for design space exploration of the electrical design is selected based on the weighted factors for the parameters of the complexity of the electrical design. The simulation is performed based on the selected simulation approach.
摘要翻译：电气设计空间探索的方法包括接收电气设计的模板。还接收与电气设计中的至少一个组件相关联的设计组件参数。加权因子分配给电气设计的设计复杂性参数。复杂性的参数可以包括以下至少一个：电气设计是否已知，多个设计组件参数，设计组件参数之间的交互级别，时间约束和模拟的存储器限制，以及是否使用统计分析或最坏情况的方法来分析模拟的输出。基于电气设计复杂度参数的加权因子，选择电气设计空间探索的仿真方法。基于选择的模拟方法进行模拟。

39. 发明授权

US08402406B2 Controlling plating stub reflections in a chip package 失效
标题翻译：控制芯片封装中的电镀短截线反射
公开(公告)号：US08402406B2
公开(公告)日：2013-03-19
申请号：US12979745
申请日：2010-12-28
申请人： Moises Cases , Bhyrav M. Mutnury , Nanju Na , Terence Rodrigues
发明人： Moises Cases , Bhyrav M. Mutnury , Nanju Na , Terence Rodrigues
IPC分类号： G06F17/50 , G06F9/455 , H01L23/02 , H01L21/00 , H01R9/00
CPC分类号： G06F17/5068 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： Methods, apparatuses, and computer program products are disclosed for controlling plating stub reflections in a chip package. In one embodiment, a resonance optimizer determines performance characteristics of a bond wire that connects a chip to a substrate of a semiconductor chip mount. In this embodiment, the resonance optimizer selects, based on the performance characteristics of the bond wire, a line width for an open-ended plating stub that extends from a signal interconnect of the substrate to a periphery of the substrate, The resonance optimizer also generates a design of signal traces for the substrate, where the signal traces include the open-ended plating stub with the selected line width.
摘要翻译：公开了用于控制芯片封装中的电镀短截线反射的方法，装置和计算机程序产品。在一个实施例中，谐振优化器确定将芯片连接到半导体芯片基座的衬底的接合线的性能特性。在该实施例中，谐振优化器基于接合线的性能特性，选择从衬底的信号互连延伸到衬底的周边的开放式电镀短截线的线宽度。谐振优化器还产生用于衬底的信号迹线的设计，其中信号迹线包括具有所选线宽的开口电镀短截线。

40. 发明授权

US08319113B2 Printed circuit board with reduced dielectric loss 有权
标题翻译：具有降低介电损耗的印刷电路板
公开(公告)号：US08319113B2
公开(公告)日：2012-11-27
申请号：US12797244
申请日：2010-06-09
申请人： Moises Cases , Bradley D. Herrman , Bhyrav M. Mutnury , Nam H. Pham , Terence Rodrigues
发明人： Moises Cases , Bradley D. Herrman , Bhyrav M. Mutnury , Nam H. Pham , Terence Rodrigues
IPC分类号： H05K1/00 , H05K3/00
CPC分类号： H05K1/024 , H05K3/4602 , H05K3/4697 , Y10T29/49124 , Y10T29/49155
摘要： A printed circuit board (‘PCB’) with reduced dielectric loss, including conductive traces disposed upon layers of dielectric material, the layers of dielectric material including core layers and prepreg layers, one or more of the layers of dielectric material including pockets of air that reduce an overall relative dielectric constant of the PCB.
摘要翻译：一种具有降低的介质损耗的印刷电路板（PCB），包括设置在介电材料层上的导电迹线，所述介电材料层包括芯层和预浸料层，介电材料层中的一个或多个包括空气袋， PCB的总相对介电常数。

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