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31. 发明授权

US07402207B1 Method and apparatus for controlling the thickness of a selective epitaxial growth layer 有权
标题翻译：用于控制选择性外延生长层厚度的方法和装置
公开(公告)号：US07402207B1
公开(公告)日：2008-07-22
申请号：US10839378
申请日：2004-05-05
申请人： Paul R. Besser , Eric N. Paton , William G. En
发明人： Paul R. Besser , Eric N. Paton , William G. En
IPC分类号： C30B21/04
CPC分类号： C30B25/16 , G01B11/0616 , H01L21/67167 , H01L21/67207 , H01L21/67745 , Y10T117/1004 , Y10T117/1008
摘要： Methods and systems for permitting thickness control of the selective epitaxial growth (SEG) layer in a semiconductor manufacturing process, for example raised source/drain applications in CMOS technologies, are presented. These methods and systems provide the capability to measure the thickness of an SEG film in-situ utilizing optical ellipsometry equipment during or after SEG layer growth, prior to removing the wafer from the SEG growth tool. Optical ellipsometry equipment can be integrated into the SEG platform and control software, thus providing automated process control (APC) capability for SEG thickness. The integration of the ellipsometry equipment may be varied, dependent upon the needs of the fabrication facility, e.g., integration to provide ellipsometer monitoring of a single process tool, or multiple tool monitoring, among other configurations.
摘要翻译：提出了在半导体制造工艺中允许厚度控制选择性外延生长（SEG）层的方法和系统，例如CMOS技术中的升高的源/漏应用。这些方法和系统提供了在从SEG生长工具移除晶片之前在SEG层生长期间或之后使用光学椭偏仪设备原位测量SEG膜的厚度的能力。光学椭圆测量设备可以集成到SEG平台和控制软件中，从而为SEG厚度提供自动化过程控制（APC）能力。椭圆测量设备的集成可以根据制造设施的需要而变化，例如集成以提供单个处理工具的椭偏仪监控，或者多个工具监视以及其他配置。

32. 发明授权

US07211489B1 Localized halo implant region formed using tilt pre-amorphization implant and laser thermal anneal 有权
标题翻译：使用倾斜预非晶化植入和激光热退火形成的局部化的晕圈植入区
公开(公告)号：US07211489B1
公开(公告)日：2007-05-01
申请号：US10934378
申请日：2004-09-07
申请人： Qi Xiang , Robert B. Ogle , Eric N. Paton , Cyrus E. Tabery , Bin Yu
发明人： Qi Xiang , Robert B. Ogle , Eric N. Paton , Cyrus E. Tabery , Bin Yu
IPC分类号： H01L21/336
CPC分类号： H01L21/268 , H01L21/26506 , H01L21/26586 , H01L29/1083 , H01L29/665 , H01L29/6653 , H01L29/6659
摘要： The present invention enables the production of improved high-reliability, high-density semiconductor devices. The present invention provides the high-density semiconductor devices by decreasing the size of semiconductor device structures, such as gate channel lengths. Short-channel effects are prevented by the use of highly localized halo implant regions formed in the device channel. Highly localized halo implant regions are formed by a tilt pre-amorphization implant and a laser thermal anneal of the halo implant region.
摘要翻译：本发明能够制造改进的高可靠性，高密度的半导体器件。本发明通过减小诸如栅极沟道长度的半导体器件结构的尺寸来提供高密度半导体器件。通过使用在器件通道中形成的高度局部化的注入区来防止短沟道效应。通过倾斜预非晶化植入和晕圈植入区域的激光热退火形成高度局部化的注入区域。

33. 发明授权

US06812106B1 Reduced dopant deactivation of source/drain extensions using laser thermal annealing 有权
标题翻译：使用激光热退火减少源/漏扩展的掺杂剂失活
公开(公告)号：US06812106B1
公开(公告)日：2004-11-02
申请号：US10341366
申请日：2003-01-14
申请人： Qi Xiang , Robert B. Ogle , Eric N. Paton , Cyrus E. Tabery , Bin Yu
发明人： Qi Xiang , Robert B. Ogle , Eric N. Paton , Cyrus E. Tabery , Bin Yu
IPC分类号： H01L21336
CPC分类号： H01L21/28194 , H01L21/26506 , H01L21/26586 , H01L21/268 , H01L29/517 , H01L29/66492 , H01L29/66545 , H01L29/66553 , H01L29/66606
摘要： Dopant deactivation of source/drain extensions during silicidation is reduced by forming deep source/drain regions using a disposable dummy gate as a mask, forming metal silicide layers on the deep source/drain regions, removing the dummy gate and then forming the source/drain extensions using laser thermal annealing. Embodiments include angular ion implantation, after removing the dummy gate, to form spaced apart pre-amorphized regions, ion implanting to form source/drain extension implants extending deeper into the substrate than the pre-amorphized regions, and then laser thermal annealing to activate the source/drain extensions having a higher impurity concentration at the main surface of the substrate than deeper into the substrate. Subsequent processing includes forming sidewall spacers, a gate dielectric layer and then the gate electrode.
摘要翻译：通过使用一次性虚拟栅极作为掩模形成深源极/漏极区域，在深度源极/漏极区域形成金属硅化物层，去除虚拟栅极，然后形成源极/漏极扩展使用激光热退火。实施例包括角度离子注入，在去除虚拟栅极之后，形成间隔开的非晶化区域，离子注入以形成比预非晶化区域更深地延伸到衬底中的源极/漏极延伸植入物，然后激光热退火以激活源/漏扩展在衬底的主表面具有较高的杂质浓度，而不是深入衬底。随后的处理包括形成侧壁间隔物，栅介质层，然后形成栅电极。

34. 发明授权

US06680250B1 Formation of deep amorphous region to separate junction from end-of-range defects 有权
标题翻译：形成深非晶区域以将结点与端范围缺陷分离
公开(公告)号：US06680250B1
公开(公告)日：2004-01-20
申请号：US10145740
申请日：2002-05-16
申请人： Eric N. Paton , Robert B. Ogle , Cyrus E. Tabery , Qi Xiang , Bin Yu
发明人： Eric N. Paton , Robert B. Ogle , Cyrus E. Tabery , Qi Xiang , Bin Yu
IPC分类号： H01L2144
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/268
摘要： A method of manufacturing a MOSFET semiconductor device includes forming a gate electrode over a substrate and a gate oxide between the gate electrode and the substrate. Inert dopants are then implanted within the substrate to form amorphized source/drain regions in the substrate extending to a first depth significantly greater than the intended junction depth. The amorphized source/drain regions are implanted with source/drain dopants such that the dopants extend into the substrate to a second depth less than the first depth, above and spaced apart from the end-of-range defect region created at the first depth by the amorphization process. Laser thermal annealing recrystallizes the amorphous regions, activates the source/drain regions and forms source/drain junctions. Because the recrystallization front velocity towards the substrate main surface is greater than the dopant atom velocity in the liquid substrate during laser thermal annealing, the junctions are not pushed down to the amorphous/crystalline silicon interface. Thus, end-of-range defects are located in a region below and spaced apart from the junctions, and the defects are not located in the activated source/drain regions. Junction leakage as a result of the end-of-range defects is thereby reduced.
摘要翻译：一种制造MOSFET半导体器件的方法包括：在栅极电极和衬底之间在衬底上形成栅极电极和栅极氧化物。然后将惰性掺杂剂注入衬底内以在衬底中形成非晶化的源极/漏极区域，延伸到明显大于预期结点深度的第一深度。非晶化源极/漏极区域注入源极/漏极掺杂剂，使得掺杂剂延伸到衬底中的第二深度小于第一深度的第二深度，在第一深度之上，并且与在第一深度处产生的端部范围缺陷区域间隔开非晶化过程。激光热退火使非晶区再结晶，激活源极/漏极区并形成源极/漏极结。因为朝向衬底主表面的再结晶前向速度大于激光热退火期间液体衬底中的掺杂剂原子速度，所以接合点不被推到非晶/硅晶界面。因此，距离范围缺陷位于与接合点下方和间隔开的区域中，并且缺陷不位于活化的源极/漏极区域中。因此，由于距离范围缺陷导致的结漏电减少。

35. 发明授权

US07091097B1 End-of-range defect minimization in semiconductor device 有权
标题翻译：半导体器件的范围内缺陷最小化
公开(公告)号：US07091097B1
公开(公告)日：2006-08-15
申请号：US10933424
申请日：2004-09-03
申请人： Eric N. Paton , Qi Xiang , Cyrus E. Tabery , Bin Yu , Robert B. Ogle
发明人： Eric N. Paton , Qi Xiang , Cyrus E. Tabery , Bin Yu , Robert B. Ogle
IPC分类号： H01L21/336
CPC分类号： H01L21/268 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L29/6659 , H01L29/7833
摘要： A method of fabricating a semiconductor device comprises forming a gate electrode over a substrate and forming deep amorphous regions within the substrate. And implanting dopants to form deep source/drain regions at a depth less than that of the deep amorphous regions, partially re-crystallizing portions of the deep amorphous regions to reduce their depth, and re-crystallizing the reduced amorphous regions to form activated final source/drain regions.
摘要翻译：制造半导体器件的方法包括在衬底上形成栅电极并在衬底内形成深非晶区域。并且注入掺杂剂以在深非晶区域的深度处形成深的源极/漏极区域，部分地重新结晶深非晶区域的部分以减小它们的深度，并且将还原的非晶区域再结晶以形成激活的最终光源 /漏区。

36. 发明授权

US06743689B1 Method of fabrication SOI devices with accurately defined monocrystalline source/drain extensions 失效
标题翻译：制造具有精确定义的单晶源极/漏极延伸的SOI器件的方法
公开(公告)号：US06743689B1
公开(公告)日：2004-06-01
申请号：US10341427
申请日：2003-01-14
申请人： Eric N. Paton , Robert B. Ogle , Cyrus E. Tabery , Qi Xiang , Bin Yu
发明人： Eric N. Paton , Robert B. Ogle , Cyrus E. Tabery , Qi Xiang , Bin Yu
IPC分类号： H01L21336
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/2658 , H01L21/268 , H01L29/458 , H01L29/66492 , H01L29/665 , H01L29/6653 , H01L29/66553 , H01L29/66772 , H01L29/78612 , H01L29/78621
摘要： Semiconductor devices comprising fully and partially depleted SOI transistors with accurately defined monocrystalline or substantially completely monocrystalline silicon source/drain extensions are fabricated by selectively pre-amorphizing intended source/drain extensions, ion implanting dopants into the pre-amorphized regions and laser thermal annealing to effect crystallization and activation of the source/drain extensions. Embodiments include forming a gate electrode over an SOI substrate with a gate dielectric layer therebetween, forming silicon nitride sidewall spacers on the side surfaces of the gate electrode, forming source/drain regions, forming a thermal oxide layer on the gate electrode and on the source/drain regions, removing the silicon nitride sidewall spacers, pre-amorphizing the intended source/drain extension regions, ion implanting impurities into the pre-amorphized regions and laser thermal annealing to crystallize the pre-amorphized regions and to activate the source/drain extensions.
摘要翻译：包括具有精确定义的单晶或基本上完全单晶硅源极/漏极延伸的完全和部分耗尽的SOI晶体管的半导体器件通过将预期的源/漏延伸，离子注入掺杂剂预先非晶化以进行预非晶化区域和激光热退火来制造源/漏扩展的结晶和激活。实施例包括在SOI衬底之上形成栅极电介质层，在栅电极之间形成氮化硅侧壁间隔物，形成源/漏区，在栅电极和源极上形成热氧化层漏极区域，去除氮化硅侧壁间隔物，使预期的源极/漏极延伸区域预非晶化，离子注入杂质到预非晶化区域和激光热退火以使预非晶化区域结晶并激活源极/漏极延伸部分。

37. 发明授权

US07071065B1 Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication 有权
标题翻译：具有硅锗源/漏扩展的应变硅PMOS及其制造方法
公开(公告)号：US07071065B1
公开(公告)日：2006-07-04
申请号：US10738716
申请日：2003-12-17
申请人： Qi Xiang , Eric N. Paton , Haihong Wang
发明人： Qi Xiang , Eric N. Paton , Haihong Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L29/1054 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/66916 , H01L29/7842 , H01L29/7848 , H01L29/802 , Y10S438/933
摘要： A strained silicon p-type MOSFET utilizes a strained silicon channel region formed on a silicon germanium substrate. Silicon germanium regions are formed on the silicon germanium layer adjacent to ends of the strained silicon channel region, and shallow source and drain extensions are implanted in the silicon germanium material. The shallow source and drain extensions do not extend into the strained silicon channel region. By forming the source and drain extensions in silicon germanium material rather than in silicon, source and drain extension distortions caused by the enhanced diffusion rate of boron in silicon are avoided.
摘要翻译：应变硅p型MOSFET利用形成在硅锗衬底上的应变硅沟道区。在邻近于应变硅沟道区的端部的硅锗层上形成硅锗区，并且在硅锗材料中注入浅的源极和漏极延伸。浅源极和漏极延伸部分不延伸到应变硅沟道区域。通过在硅锗材料而不是在硅中形成源极和漏极延伸，避免了由硅中的增强的扩散速率引起的源极和漏极扩展失真。

38. 发明授权

US06905923B1 Offset spacer process for forming N-type transistors 有权
标题翻译：用于形成N型晶体管的偏置间隔工艺
公开(公告)号：US06905923B1
公开(公告)日：2005-06-14
申请号：US10619877
申请日：2003-07-15
申请人： Eric N. Paton , Haihong Wang , Qi Xiang
发明人： Eric N. Paton , Haihong Wang , Qi Xiang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823864
摘要： A method of fabricating an SMOS integrated circuit with source and drain junctions utilizes an offset gate spacer for N-type transistors. Ions are implanted to form the source and drain regions in a strained layer. The offset spacer reduces problems associated with Arsenic (As) diffusion on strained semiconductor layers. The process can be utilized for SMOS metal oxide semiconductor field effect transistors (MOSFETs). The strained layer can be a strained silicon layer formed above a germanium layer.
摘要翻译：制造具有源极和漏极结的SMOS集成电路的方法利用用于N型晶体管的偏移栅极间隔物。植入离子以形成应变层中的源区和漏区。偏移间隔物减少了在应变半导体层上与砷（As）扩散相关的问题。该工艺可用于SMOS金属氧化物半导体场效应晶体管（MOSFET）。应变层可以是形成在锗层之上的应变硅层。

39. 发明授权

US07351638B1 Scanning laser thermal annealing 有权
标题翻译：扫描激光热退火
公开(公告)号：US07351638B1
公开(公告)日：2008-04-01
申请号：US10021782
申请日：2001-12-18
申请人： Cyrus E. Tabery , Eric N. Paton , Bin Yu , Qi Xiang , Robert B. Ogle
发明人： Cyrus E. Tabery , Eric N. Paton , Bin Yu , Qi Xiang , Robert B. Ogle
IPC分类号： H01L21/336
CPC分类号： H01L21/268 , H01L21/26513 , H01L29/6659
摘要： A method of manufacturing a semiconductor device includes forming a gate electrode over a substrate, implanting dopants into the substrate and activating the dopants using laser thermal annealing. During annealing, the laser and substrate are moved relative to one another, and the movement of the laser and the substrate relative to one another does not pause between and during activating one portion of the source/drain regions and activating another portion of the source/drain regions. Each pulse from the laser can respectively irradiate different portions of the source/drain regions, and a spot area of the laser is less than 50 millimeter2.
摘要翻译：一种制造半导体器件的方法包括在衬底上形成栅电极，将掺杂剂注入到衬底中并使用激光热退火激活掺杂剂。在退火期间，激光器和衬底相对于彼此移动，并且激光器和衬底相对于彼此的运动在激活源极/漏极区域的一部分之间和在激活源极/漏极区域的另一部分之间不间断，漏区。来自激光器的每个脉冲可以分别照射源极/漏极区域的不同部分，并且激光器的斑点面积小于50毫米2。

40. 发明授权

US06921709B1 Front side seal to prevent germanium outgassing 失效
标题翻译：前侧密封防止锗脱气
公开(公告)号：US06921709B1
公开(公告)日：2005-07-26
申请号：US10620194
申请日：2003-07-15
申请人： Eric N. Paton , Haihong Wang , Qi Xiang
发明人： Eric N. Paton , Haihong Wang , Qi Xiang
IPC分类号： H01L21/265 , H01L21/336 , H01L21/84 , H01L29/10
CPC分类号： H01L21/84 , H01L21/2652 , H01L29/1054 , H01L29/665 , H01L29/6659 , H01L29/7842 , Y10S438/923 , Y10S438/933
摘要： A method of manufacturing an integrated circuit having a gate structure above a substrate that includes germanium utilizes at least one layer as a seal. The layer advantageously can prevent back sputtering and outdiffusion. A transistor can be formed in the substrate by doping through the layer. Another layer can be provided below the first layer. Layers of silicon dioxide, silicon carbide, silicon nitride, titanium, titanium nitride, titanium/titanium nitride, tantalum nitride, and silicon carbide can be used.
摘要翻译：制造具有在包括锗的衬底之上的栅极结构的集成电路的方法利用至少一层作为密封。该层有利地可以防止反溅射和扩散。可以通过掺杂通过层在衬底中形成晶体管。可以在第一层下面提供另一层。可以使用二氧化硅，碳化硅，氮化硅，钛，氮化钛，钛/氮化钛，氮化钽和碳化硅的层。

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