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31. 发明申请

US20070099341A1 Method of making stacked die package 有权
标题翻译：制造堆叠模具包装的方法
公开(公告)号：US20070099341A1
公开(公告)日：2007-05-03
申请号：US11524457
申请日：2006-09-20
申请人： Wai Lo
发明人： Wai Lo
IPC分类号： H01L21/00
CPC分类号： H01L23/49575 , H01L21/568 , H01L23/3107 , H01L23/3128 , H01L23/4951 , H01L23/4952 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L2224/16225 , H01L2224/16245 , H01L2224/32145 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48599 , H01L2224/4917 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2224/85 , H01L2224/81 , H01L2224/83 , H01L2924/01004 , H01L2924/00011 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599
摘要： A method of making a stacked die package (39) includes placing a first flip chip die (16) on a base carrier (12) and electrically connecting the first flip chip die (16) to the base carrier (12). A second flip chip die (18) is attached back-to-back to the first flip chip die (16) and electrically connected to the base carrier (12) with a plurality of insulated wires (20). A mold compound (36) is formed over the first and second dice and one surface of the base carrier.
摘要翻译：制造堆叠管芯封装（39）的方法包括将第一倒装芯片裸片（16）放置在基座载体（12）上并将第一倒装芯片裸片（16）电连接到基座载体（12）。第二倒装芯片（18）背对背地安装到第一倒装芯片裸片（16），并用多个绝缘线（20）电连接到基座（12）。模制化合物（36）形成在第一和第二骰子和基底载体的一个表面上。

32. 发明授权

US07081406B2 Interconnect dielectric tuning 失效
标题翻译：互连电介质调谐
公开(公告)号：US07081406B2
公开(公告)日：2006-07-25
申请号：US10915719
申请日：2004-08-10
申请人： Wai Lo , Hong Lin , Shiqun Gu , Wilbur G. Catabay , Zhihai Wang , Wei-Jen Hsia
发明人： Wai Lo , Hong Lin , Shiqun Gu , Wilbur G. Catabay , Zhihai Wang , Wei-Jen Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76838 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.
摘要翻译：对形成集成电路的方法的改进。形成蚀刻停止层以覆盖集成电路的前端处理层。形成支撑结构，其被布置为支撑集成电路的各个级别上的导电互连。基本上去除了在制造互连期间形成的蚀刻停止层上方的所有非导电层。

33. 发明申请

US20050127458A1 Incorporating dopants to enhance the dielectric properties of metal silicates 失效
标题翻译：掺入掺杂剂以增强金属硅酸盐的介电性能
公开(公告)号：US20050127458A1
公开(公告)日：2005-06-16
申请号：US10738761
申请日：2003-12-16
申请人： Wai Lo , Verne Hornback , Wilbur Catabay , Wei-Jen Hsia , Sey-Shing Sun
发明人： Wai Lo , Verne Hornback , Wilbur Catabay , Wei-Jen Hsia , Sey-Shing Sun
IPC分类号： H01L21/3115 , H01L21/316 , H01L29/76
CPC分类号： H01L21/02142 , H01L21/02323 , H01L21/3115 , H01L21/31604 , H01L21/31612 , H01L21/31637 , H01L21/31645
摘要： The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group IV metal.
摘要翻译：本发明提供了在半导体晶片上形成高k电介质层的方法。金属硅酸盐介电层最初沉积在晶片上。将具有可离解氧的掺杂剂引入到晶片上的金属硅酸盐中。根据一个实施方案，金属硅酸盐包含IV族金属，掺杂剂是碱金属和碱土金属之一的氧化物。根据另一个实施方案，金属硅酸盐包含IV族金属。

34. 发明申请

US20110195348A1 METHOD AND SYSTEM FOR AUTOMATED GENERATION OF MASKS FOR SPACER FORMATION FROM A DESIRED FINAL WAFER PATTERN 有权
标题翻译：用于自动生成用于从预期的最终波形图形形成的掩模的方法和系统
公开(公告)号：US20110195348A1
公开(公告)日：2011-08-11
申请号：US12701391
申请日：2010-02-05
申请人： Wai Lo , Todd Lukanc , Christie Marrian
发明人： Wai Lo , Todd Lukanc , Christie Marrian
IPC分类号： G03F1/00 , B05C11/00
CPC分类号： G03F1/14 , G03F1/70
摘要： Methods and systems for generating masks for spacer formation are disclosed. As a part of a disclosed method, a predefined final wafer pattern is accessed, areas related to features in the predefined final wafer pattern are identified and a template mask is formed based on the identified areas for forming spacers on a wafer. Subsequently, a mask is formed for use in the removal of portions of the spacers to form an on wafer pattern that corresponds to the predefined final wafer pattern.
摘要翻译：公开了用于产生用于间隔物形成的掩模的方法和系统。作为所公开的方法的一部分，访问预定义的最终晶片图案，识别与预定的最终晶片图案中的特征相关的区域，并且基于用于在晶片上形成间隔物的所识别的区域形成模板掩模。随后，形成用于去除间隔物的部分以形成对应于预定的最终晶片图案的晶片图案的掩模。

35. 发明授权

US07553772B1 Process and apparatus for simultaneous light and radical surface treatment of integrated circuit structure 失效
标题翻译：集成电路结构的同时光和自由基表面处理的工艺和装置
公开(公告)号：US07553772B1
公开(公告)日：2009-06-30
申请号：US11046949
申请日：2005-01-31
申请人： Shiqun Gu , Wai Lo , Hong Lin
发明人： Shiqun Gu , Wai Lo , Hong Lin
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/76814 , H01L21/02238 , H01L21/02247 , H01L21/02249 , H01L21/3105 , H01L21/31662 , H01L21/3185
摘要： Process and apparatus provide reactive radicals generated from a remote plasma source which contact a portion of a substrate surface simultaneous with a contact of the same substrate surface with a light source which locally activates the portion of the substrate surface in contact with said radicals.
摘要翻译：工艺和设备提供从远程等离子体源产生的反应性基团，其接触衬底表面的一部分，同时与同一衬底表面的接触与局部激活与所述自由基接触的衬底表面的部分的光源。

36. 发明授权

US07405116B2 Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow 有权
标题翻译：门边缘衬垫的应用以保持栅极长度CD在替代栅极晶体管流中
公开(公告)号：US07405116B2
公开(公告)日：2008-07-29
申请号：US10916322
申请日：2004-08-11
申请人： Richard J. Carter , Wai Lo , Sey-Shing Sun , Hong Lin , Verne Hornback
发明人： Richard J. Carter , Wai Lo , Sey-Shing Sun , Hong Lin , Verne Hornback
IPC分类号： H01L21/338
CPC分类号： H01L29/6656 , H01L21/823828 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.
摘要翻译：保持良好限定的栅极堆叠轮廓的方法，沉积或生长均匀的栅极电介质，并且通过在虚拟栅极蚀刻之后和间隔物工艺之前沉积的惰性绝缘衬垫来维持栅极长度CD控制。衬垫材料对用于去除伪栅极氧化物的湿化学品是选择性的，从而防止间隔区域中的底切。该方法旨在使金属栅极电极技术成为与现有制造环境兼容的可行技术，用于多代CMOS晶体管，包括属于65nm，45nm和25nm技术节点的CMOS晶体管，这些晶体管正在用于模拟，数字或混合信号集成电路，用于通信，娱乐，教育和安全产品等各种应用。

37. 发明申请

US20070209196A1 Slider row bar de-bond fixture 审中-公开
标题翻译：滑块排条脱扣夹具
公开(公告)号：US20070209196A1
公开(公告)日：2007-09-13
申请号：US11708673
申请日：2007-02-21
申请人： Shing Lau , Wai Lo
发明人： Shing Lau , Wai Lo
IPC分类号： G11C5/12 , G11B5/127
CPC分类号： G11B5/102 , G11B5/3173 , Y10T29/49032 , Y10T29/5313 , Y10T29/53165
摘要： A slider row bar de-bond fixture has a base plate; a row of separator walls formed on a top surface of the base plate and spaced one another for separating a plurality of slider row bars; and a plurality of grooves defined between the adjacent separator walls for receiving the slider row bars respectively. Each of the separator walls has a free top end with a smaller depth than its bottom end. Preferably, each of the separator walls has a structure of trapezoid or triangular form in cross section. The slider row bar de-bond fixture occupy a little room and more importantly, receive the debonded slider row bars more safely and without overlapping.
摘要翻译：滑块排条脱扣夹具具有基板; 一排分隔壁，形成在基板的顶表面上并彼此间隔开以分离多个滑块排条; 以及限定在相邻分离器壁之间的多个凹槽，用于分别接收滑块排条。每个分隔壁具有比其底端更小的深度的自由顶端。优选地，每个隔板的横截面具有梯形或三角形的结构。滑块排条脱扣夹具占据一点空间，更重要的是，更安全地接收脱粘的滑块排条，而不重叠。

38. 发明申请

US20070184763A1 SAND PAD LOCK FOR SANDER 失效
标题翻译： SANDER的SAND PAD LOCK
公开(公告)号：US20070184763A1
公开(公告)日：2007-08-09
申请号：US11695977
申请日：2007-04-03
申请人： Koon Chung , Hoi Wang , Wai Lo
发明人： Koon Chung , Hoi Wang , Wai Lo
IPC分类号： B24B27/08
CPC分类号： B24B45/006 , B24B23/022
摘要： A lock formed from a body and a projection that is inserted into the aperture in the spindle to rotatably connect a sanding pad to the housing. The lock may include an arm rotatably mounted to the body that is movable between a first position wherein the arm can be manipulated to rotate the body with respect to the spindle and a second position where the arm is contained within the body.
摘要翻译：由主体形成的锁和插入主轴中的孔中的突起，以将磨垫可旋转地连接到壳体。锁可以包括可旋转地安装到主体的臂，其可以在第一位置和第二位置之间移动，第一位置可以操纵臂以使主体相对于主轴旋转，并且第二位置将臂固定在主体内。

39. 发明授权

US07064062B2 Incorporating dopants to enhance the dielectric properties of metal silicates 失效
标题翻译：掺入掺杂剂以增强金属硅酸盐的介电性能
公开(公告)号：US07064062B2
公开(公告)日：2006-06-20
申请号：US10738761
申请日：2003-12-16
申请人： Wai Lo , Verne Hornback , Wilbur G. Catabay , Wei-Jen Hsia , Sey-Shing Sun
发明人： Wai Lo , Verne Hornback , Wilbur G. Catabay , Wei-Jen Hsia , Sey-Shing Sun
IPC分类号： H01L21/4763 , B05D3/02
CPC分类号： H01L21/02142 , H01L21/02323 , H01L21/3115 , H01L21/31604 , H01L21/31612 , H01L21/31637 , H01L21/31645
摘要： The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group III metal.
摘要翻译：本发明提供了在半导体晶片上形成高k电介质层的方法。金属硅酸盐介电层最初沉积在晶片上。将具有可离解氧的掺杂剂引入到晶片上的金属硅酸盐中。根据一个实施方案，金属硅酸盐包含IV族金属，掺杂剂是碱金属和碱土金属之一的氧化物。根据另一个实施方案，金属硅酸盐包含III族金属。

40. 发明申请

US20060035455A1 Interconnect dielectric tuning 失效
公开(公告)号：US20060035455A1
公开(公告)日：2006-02-16
申请号：US10915719
申请日：2004-08-10
申请人： Wai Lo , Hong Lin , Shiqun Gu , Wilbur Catabay , Zhihai Wang , Wei-Jen Hsia
发明人： Wai Lo , Hong Lin , Shiqun Gu , Wilbur Catabay , Zhihai Wang , Wei-Jen Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76838 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.

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