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31. 发明授权

US5692138A Flexible user interface circuit in a memory device 失效
标题翻译：存储设备中灵活的用户界面电路
公开(公告)号：US5692138A
公开(公告)日：1997-11-25
申请号：US754104
申请日：1996-11-21
申请人： Mickey L. Fandrich , Richard J. Durante , Rodney R. Rozman
发明人： Mickey L. Fandrich , Richard J. Durante , Rodney R. Rozman
IPC分类号： G06F13/16 , G06F13/18 , G11C16/10 , G06F12/00 , G06F13/00
CPC分类号： G06F13/1642 , G06F13/18 , G11C16/102
摘要： A flash memory device having a flash cell array comprising a plurality of flash cells, a flash array controller circuit for performing program and erase operations on the flash cell array according to a queue operation, and an interface circuit for generating the queue operation according to a user command and a set of command parameters received over a host bus. The interface circuit determines a set of limited resource control bits for the user command and queues the user command and associated parameters to the flash array controller circuit.
摘要翻译：一种具有包括多个闪存单元的闪存单元阵列的闪速存储器件，用于根据队列操作对闪存单元阵列进行编程和擦除操作的闪存阵列控制器电路，以及用于根据队列操作产生队列操作的接口电路用户命令和一组通过主机总线接收的命令参数。接口电路确定用户命令的一组有限的资源控制位，并将用户命令和相关参数排队到闪存阵列控制器电路。

32. 发明授权

US5592641A Method and device for selectively locking write access to blocks in a memory array using write protect inputs and block enabled status 失效
标题翻译：使用写保护输入和块启用状态来选择性地锁定对存储器阵列中的块的写入访问的方法和设备
公开(公告)号：US5592641A
公开(公告)日：1997-01-07
申请号：US85546
申请日：1993-06-30
申请人： Mickey L. Fandrich , Salim B. Fedel , Thomas C. Price , Richard J. Durante , Geoffrey A. Gould , Timothy W. Goodell , Scott M. Doyle
发明人： Mickey L. Fandrich , Salim B. Fedel , Thomas C. Price , Richard J. Durante , Geoffrey A. Gould , Timothy W. Goodell , Scott M. Doyle
IPC分类号： G11C7/24 , G11C16/22 , G06F12/14
CPC分类号： G11C16/22 , G11C7/24
摘要： A method and device for selectively enabling and disabling write access to flash blocks in a flash memory device. A lock command locks and unlocks a flash block in a flash array containing a plurality of flash blocks. A block data row decoder selects a block data area of the flash block, and a block status row decoder selects a block status area of the flash block. A lock bit in the block status area is programmed to a first logic state if the lock command specifies a lock flash block operation, or to a second logic state if the lock command specifies a release flash block operation. If a write protect input, read from the write protect pin of the flash memory device, indicates that a write lock is enabled and if a block enabled status bit in a block status register corresponding to the block indicates that the block has the write lock, then the lock bit is read and stored into the block enabled status bit in the block status register corresponding to the block. The write protect input is read again from the write protect pin and if the write protect input indicates that the write lock is enabled, and if the block enabled status bit in the block status register corresponding to the block, as updated, indicates that the block has the write lock, then an error is signaled.
摘要翻译：一种用于选择性地启用和禁用对闪存设备中的闪存块的写入访问的方法和设备。锁定命令锁定并解锁包含多个闪存块的闪存阵列中的闪存块。块数据行解码器选择闪存块的块数据区，块状态行解码器选择闪存块的块状态区。如果锁定命令指定锁定闪存块操作，则块状态区域中的锁定位被编程为第一逻辑状态，如果锁定命令指定释放闪存块操作，则将其锁定到第二逻辑状态。如果写保护输入从闪存器件的写保护引脚读取，则指示写锁定被使能，并且如果与该块相对应的块状态寄存器中的块使能状态位指示该块具有写锁定，则锁定位被读取并存储到与块相对应的块状态寄存器中的块使能状态位。写保护输入再次从写保护引脚读取，如果写保护输入指示写锁定使能，并且如果块状态寄存器中对应于块更新的块状态寄存器位指示块有写锁定，然后发出错误信号。

33. 发明授权

US5537357A Method for preconditioning a nonvolatile memory array 失效
标题翻译：用于预处理非易失性存储器阵列的方法
公开(公告)号：US5537357A
公开(公告)日：1996-07-16
申请号：US266132
申请日：1994-06-27
申请人： Amit Merchant , Mickey L. Fandrich , Geoffrey Gould
发明人： Amit Merchant , Mickey L. Fandrich , Geoffrey Gould
IPC分类号： G11C16/10 , G11C16/34 , G11C7/02
CPC分类号： G11C16/107 , G11C16/10 , G11C16/3454 , G11C16/3459
摘要： A method of preconditioning a nonvolatile memory array including a first memory cell and a second memory cell. Preconditioning begins by applying an initial precondition pulse to all memory cells in the nonvolatile memory array without pausing to perform precondition verification. After this first step, precondition verification begins. The voltage level of the first memory cell is sensed and compared to a selected voltage level. If the threshold voltage of the first memory cell is below the selected voltage, the first memory cell did not precondition verify. In that case, another precondition pulse is then applied to the first memory cell. Application of precondition pulses and precondition verification continues until the first memory cell verifies as preconditioned. Attention turns to the second memory cell after the first memory cell precondition verifies. If the second memory cell does not precondition verify another precondition pulse is applied to the second memory cell. Application of precondition pulses and precondition verification continues until the second memory cell verifies as preconditioned.
摘要翻译：一种预处理包括第一存储单元和第二存储单元的非易失性存储器阵列的方法。通过向非易失性存储器阵列中的所有存储器单元应用初始预条件脉冲而不停止执行前提条件验证，开始预处理。在第一步之后，开始前提条件验证。感测第一存储器单元的电压电平并将其与选定的电压电平进行比较。如果第一存储单元的阈值电压低于所选择的电压，则第一存储单元未进行前提条件验证。在这种情况下，然后将另一个前提条件脉冲施加到第一存储器单元。预处理脉冲的应用和前提条件验证一直持续到第一个存储器单元验证为预处理。在第一个存储单元前提条件验证之后，注意转向第二个存储单元。如果第二存储器单元不是先决条件，则验证另一预条件脉冲被施加到第二存储器单元。预处理脉冲的应用和前提条件验证一直持续到第二个存储单元验证为预处理。

34. 发明授权

US5414829A Override timing control circuitry and method for terminating program and erase sequences in a flash memory 失效
标题翻译：覆盖定时控制电路和用于终止闪存中的程序和擦除序列的方法
公开(公告)号：US5414829A
公开(公告)日：1995-05-09
申请号：US119892
申请日：1993-09-10
申请人： Mickey L. Fandrich , Owen W. Jungroth
发明人： Mickey L. Fandrich , Owen W. Jungroth
IPC分类号： G11C17/00 , G11C16/02 , G11C16/16 , G11C16/32 , G06F13/00 , G06F1/04 , G11C16/06
CPC分类号： G11C16/16 , G11C16/32
摘要： Override control circuitry and a method for terminating a sequence for erasing or programming a computer memory are described. A command register is provided for storing a command sent by an external processor to the memory. A decoder circuit decodes the command and outputs an erase or program set-up signal if the command indicates the initiation of an erase or program sequence. A latch is coupled to the decode circuit for storing the erase or program set-up signal. An override timer is located between the latch and the memory. The override timer includes a counter which is initialized and begins counting when the erase or program set-up signal is latched. The override timer also includes a circuit that detects when the counter has reached a first count for an erase sequence and a second count for a program sequence. The circuit then generates an erase or program override signal. An erase switch detects the erase override signal and prevents the application of an erase voltage to the memory. A program switch detects the program override signal and prevents the application of a program voltage to the memory. A voltage detector is also provided to terminate the erase or program sequences when the erase voltage or program voltage falls below a selected voltage level.
摘要翻译：描述了覆盖控制电路和终止用于擦除或编程计算机存储器的序列的方法。提供了一个命令寄存器，用于将由外部处理器发送的命令存储到存储器中。如果命令指示擦除或程序序列的启动，则解码器电路对命令进行解码并输出擦除或程序设置信号。锁存器耦合到解码电路，用于存储擦除或程序设置信号。覆盖计时器位于锁存器和存储器之间。覆盖定时器包括一个初始化的计数器，当擦除或程序设置信号被锁存时开始计数。覆盖定时器还包括一个电路，用于检测计数器何时达到擦除序列的第一个计数以及程序序列的第二个计数。然后电路产生擦除或程序覆盖信号。擦除开关检测擦除覆盖信号，并防止对存储器施加擦除电压。程序开关检测程序覆盖信号并防止向存储器施加程序电压。还提供电压检测器以在擦除电压或编程电压低于所选电压电平时终止擦除或编程序列。

35. 发明授权

US5377199A Boundary test scheme for an intelligent device 失效
标题翻译：智能设备的边界测试方案
公开(公告)号：US5377199A
公开(公告)日：1994-12-27
申请号：US85644
申请日：1993-06-30
申请人： Mickey L. Fandrich
发明人： Mickey L. Fandrich
IPC分类号： G01R31/319 , G01R31/28
CPC分类号： G01R31/31919 , G01R31/31908
摘要： A testing apparatus for testing connectivity to a circuit board of an integrated circuit chip disposed on the circuit board. The circuit board has signal transmission circuitry. The integrated circuit chip has pins coupled to the signal transmission circuitry. The pins are for receiving digital signals asserted external to the chip. Each digital signal has a binary value depending upon whether the signal is asserted or not. The testing apparatus tests connectivity of the pins. The testing apparatus has signal assertion and reception circuitry that is coupled to the signal transmission circuitry of the circuit board but is not disposed on the chip. Command sensing, pin state storage, general storage, algorithm execution and general data output circuitry are all disposed on the chip to be tested. The command sensing circuitry is for sensing external assertion of a test command by the signal assertion and reception circuitry. The test command causes the chip to enter a test mode. The pin state storage circuitry is coupled to the pins and stores the binary values associated with the signals asserted by the signal assertion and reception circuitry. The general storage circuitry is for storing general digital data. The algorithm execution circuitry executes a test algorithm if the chip has entered the test mode. The test algorithm retrieves the binary values stored in the pin state storage circuitry, converts the binary values to general digital data, and stores the general digital data in the general storage circuitry. The general digital data output circuitry provides the general digital data stored in the general storage circuitry as output from the chip to the signal assertion and reception circuitry after the test algorithm has executed.
摘要翻译：一种用于测试与布置在电路板上的集成电路芯片的电路板的连接性的测试装置。电路板具有信号传输电路。集成电路芯片具有耦合到信号传输电路的引脚。引脚用于接收芯片外部断言的数字信号。每个数字信号具有二进制值，取决于信号是否被断言。测试设备测试引脚的连接性。测试装置具有耦合到电路板的信号传输电路但不设置在芯片上的信号断言和接收电路。命令感测，引脚状态存储，通用存储，算法执行和通用数据输出电路均放置在要测试的芯片上。命令感测电路用于通过信号断言和接收电路来感测测试命令的外部断言。测试命令使芯片进入测试模式。引脚状态存储电路耦合到引脚并且存储与由信号断言和接收电路断言的信号相关联的二进制值。通用存储电路用于存储通用数字数据。如果芯片进入测试模式，则算法执行电路执行测试算法。测试算法检索存储在引脚状态存储电路中的二进制值，将二进制值转换为通用数字数据，并将通用数字数据存储在通用存储电路中。一般的数字数据输出电路在测试算法执行之后提供存储在通用存储电路中的通用数字数据，作为从芯片到信号断言和接收电路的输出。

36. 发明授权

US5333300A Timing circuitry and method for controlling automated programming and erasing of a non-volatile semiconductor memory 失效
标题翻译：用于控制非易失性半导体存储器的自动编程和擦除的定时电路和方法
公开(公告)号：US5333300A
公开(公告)日：1994-07-26
申请号：US654385
申请日：1991-02-11
申请人： Mickey L. Fandrich
发明人： Mickey L. Fandrich
IPC分类号： G11C16/10 , G06F13/24
CPC分类号： G11C16/10 , G11C2216/20
摘要： Circuitry for handshaking between a command state machine and write state machine is described. The handshaking circuitry, the command state machine and the write state machine are part of a non-volatile semiconductor memory device that includes a memory array. The command state machine receives commands from a user and communicates valid commands to the write state machine, which responds by performing automated program and erasure operations on the memory array, as appropriate. The command state machine identifies valid commands based upon signals generated by the handshaking circuitry. The handshaking circuitry includes three latches, an OR gate and a NAND gate. The serially coupled latches store an idle signal from the write state machine. The OR gate is coupled to outputs from the second and third of the serially coupled latches and generates a signal indicative of the whether the write state machine is idle. The NAND gate generates another signal indicative of whether the write state machine is busy based upon a start signal, a finished signal and a delayed idle signal. Also described are a method of handshaking between the write state machine and the command state machine and circuitry for powering up and powering down the write state machine.
摘要翻译：描述了在命令状态机和写状态机之间进行握手的电路。握手电路，命令状态机和写状态机是包括存储器阵列的非易失性半导体存储器件的一部分。命令状态机从用户接收命令并将有效命令传送到写状态机，该状态机通过对存储器阵列执行自动程序和擦除操作来进行响应。命令状态机基于由握手电路产生的信号来识别有效命令。握手电路包括三个锁存器，一个或门和一个与非门。串行耦合的锁存器存储来自写入状态机的空闲信号。 OR门耦合到来自第二和第三串行耦合的锁存器的输出，并产生指示写状态机是否空闲的信号。 NAND门基于起始信号，完成信号和延迟空闲信号产生指示写状态机是否忙的另一信号。还描述了在写状态机和命令状态机之间握手的方法以及用于为写状态机供电和断电的电路。

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