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31. 发明授权

US07619917B2 Memory cell with trigger element 失效
标题翻译：具有触发元件的存储单元
公开(公告)号：US07619917B2
公开(公告)日：2009-11-17
申请号：US11605079
申请日：2006-11-28
申请人： Thomas Nirschl , Thomas Happ , Jan Boris Philipp
发明人： Thomas Nirschl , Thomas Happ , Jan Boris Philipp
IPC分类号： G11C11/39 , G11C11/36 , G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C2213/76
摘要： A memory device includes a plurality of word lines extending as rows and bit lines extending as columns. A memory cell is coupled between a word line and a bit line, wherein the memory cell includes a unipolar memory element selectively coupled to the bit line via a trigger element.
摘要翻译：存储器件包括作为列延伸的行和位线延伸的多个字线。存储器单元耦合在字线和位线之间，其中存储单元包括经由触发元件选择性地耦合到位线的单极存储器元件。

32. 发明授权

US07593255B2 Integrated circuit for programming a memory element 有权
标题翻译：用于编程存储器元件的集成电路
公开(公告)号：US07593255B2
公开(公告)日：2009-09-22
申请号：US11952462
申请日：2007-12-07
申请人： Thomas Happ , Thomas Nirschl , Jan Boris Philipp
发明人： Thomas Happ , Thomas Nirschl , Jan Boris Philipp
IPC分类号： G11C7/00
CPC分类号： G11C13/0064 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2013/0083 , G11C2013/0092 , G11C2211/5644
摘要： An integrated circuit includes a resistance changing memory element and a circuit. The circuit is configured to program the memory element by iteratively applying a variable program pulse to the memory element until a resistance of the memory element crosses a first reference resistance. The variable program pulse is adjusted for each iteration such that the resistance of the memory element approaches the first reference resistance.
摘要翻译：集成电路包括电阻变化存储元件和电路。电路被配置为通过向存储元件迭代地施加可变程序脉冲来对存储元件进行编程，直到存储元件的电阻跨过第一参考电阻。对于每次迭代调整可变编程脉冲，使得存储元件的电阻接近第一参考电阻。

33. 发明授权

US07545668B2 Mushroom phase change memory having a multilayer electrode 失效
标题翻译：具有多层电极的蘑菇相变存储器
公开(公告)号：US07545668B2
公开(公告)日：2009-06-09
申请号：US11766831
申请日：2007-06-22
申请人： Jan Boris Philipp , Thomas Happ
发明人： Jan Boris Philipp , Thomas Happ
IPC分类号： G11C11/00
CPC分类号： H01L45/144 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/148 , H01L45/1666
摘要： An integrated circuit includes a first electrode including at least two electrode material layers and a resistivity changing material including a first portion and a second portion. The first portion contacts the first electrode and has a same cross-sectional width as the first electrode. The second portion has a greater cross-sectional width than the first portion. The integrated circuit includes a second electrode coupled to the resistivity changing material.
摘要翻译：集成电路包括包括至少两个电极材料层的第一电极和包括第一部分和第二部分的电阻率变化材料。第一部分接触第一电极并具有与第一电极相同的横截面宽度。第二部分具有比第一部分更大的截面宽度。集成电路包括耦合到电阻率变化材料的第二电极。

34. 发明授权

US07515455B2 High density memory array for low power application 有权
标题翻译：高密度存储阵列，用于低功耗应用
公开(公告)号：US07515455B2
公开(公告)日：2009-04-07
申请号：US11650244
申请日：2007-01-05
申请人： Thomas Nirshl , Thomas Happ
发明人： Thomas Nirshl , Thomas Happ
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C7/04 , G11C13/0004 , G11C13/0033 , G11C16/3431
摘要： A memory device includes a first bit line in a first conducting layer and a second bit line parallel to the first bit line. The second bit line is in a second conducting layer. The memory device includes a MOS select transistor and a word line coupled to a gate of the MOS select transistor. The word line is at an angle with respect to the first bit line and the second bit line. The memory device includes a first resistive memory element coupled between a source of the MOS select transistor and the first bit line. The memory device includes a second resistive memory element coupled between a drain of the MOS select transistor and the second bit line.
摘要翻译：存储器件包括第一导电层中的第一位线和与第一位线平行的第二位线。第二位线在第二导电层中。存储器件包括MOS选择晶体管和耦合到MOS选择晶体管的栅极的字线。字线相对于第一位线和第二位线成一定角度。存储器件包括耦合在MOS选择晶体管的源极与第一位线之间的第一电阻性存储器元件。存储器件包括耦合在MOS选择晶体管的漏极和第二位线之间的第二电阻存储器元件。

35. 发明申请

US20090046499A1 INTEGRATED CIRCUIT INCLUDING MEMORY HAVING LIMITED READ 审中-公开
标题翻译：集成电路，包括有限读数的存储器
公开(公告)号：US20090046499A1
公开(公告)日：2009-02-19
申请号：US12026249
申请日：2008-02-05
申请人： Jan Boris Philipp , Luca De Ambroggi , Peter Schroegmeier , Gernot Steinlesberger , Christian Pho Duc , Franz Kreupl , Thomas Happ
发明人： Jan Boris Philipp , Luca De Ambroggi , Peter Schroegmeier , Gernot Steinlesberger , Christian Pho Duc , Franz Kreupl , Thomas Happ
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C7/1006 , G11C11/5678 , G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0059 , G11C13/0061 , G11C13/0097 , G11C16/3431 , G11C16/349 , G11C2013/0047 , G11C2013/0052 , G11C2013/0092
摘要： An integrated circuit including a memory with an array of memory cells, each memory cell comprising a non-volatile memory element; and a limited read circuit communicatively coupled to the array of memory cells.
摘要翻译：一种集成电路，包括具有存储器单元阵列的存储器，每个存储器单元包括非易失性存储元件; 以及通信地耦合到存储器单元阵列的有限读取电路。

36. 发明申请

US20090046498A1 INTEGRATED CIRCUIT INCLUDING MEMORY HAVING REDUCED CROSS TALK 失效
标题翻译：集成电路，包括具有减少交叉口的存储器
公开(公告)号：US20090046498A1
公开(公告)日：2009-02-19
申请号：US11948204
申请日：2007-11-30
申请人： Jan Boris Philipp , Thomas Happ
发明人： Jan Boris Philipp , Thomas Happ
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： H01L27/2472 , Y10S438/90
摘要： An integrated circuit includes a first electrode, a second, a first resistivity changing material contacting the first electrode at a first interface, and a second resistivity changing material contacting the second electrode at a second interface. A direct communication path between the first interface and the second interface is greater than the lateral distance.
摘要翻译：集成电路包括第一电极，第二电极，第一电阻率变化材料，在第一界面处接触第一电极，第二电阻率变化材料在第二界面处与第二电极接触。第一接口和第二接口之间的直接通信路径大于横向距离。

37. 发明申请

US20090003035A1 CONDITIONING OPERATIONS FOR MEMORY CELLS 失效
标题翻译：记忆细胞的调节操作
公开(公告)号：US20090003035A1
公开(公告)日：2009-01-01
申请号：US11778786
申请日：2007-07-17
申请人： Jan Boris Philipp , Thomas Happ , Thomas Nirschl
发明人： Jan Boris Philipp , Thomas Happ , Thomas Nirschl
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0011 , G11C13/0069 , G11C2013/0076 , G11C2013/0083 , G11C2213/31 , G11C2213/32
摘要： One embodiment of the invention relates to a method for conditioning resistive memory cells of a memory array with a number of reliable resistance ranges, where each reliable resistance range corresponds to a different data state. In the method, group of at least one resistive memory cell is accessed, which group includes at least one unreliable cell. At least one pulse is applied to the at least one unreliable cell to shift at least one resistance respectively associated with the at least one unreliable cell to the highest of the reliable resistance ranges. Other methods and systems are also disclosed.
摘要翻译：本发明的一个实施例涉及一种用于调节具有多个可靠电阻范围的存储器阵列的电阻性存储单元的方法，其中每个可靠的电阻范围对应于不同的数据状态。在该方法中，访问至少一个电阻性存储器单元的组，该组包括至少一个不可靠单元。至少一个脉冲被施加到至少一个不可靠的单元，以将至少一个不可靠单元相关联的至少一个电阻移动到可靠电阻范围的最高位置。还公开了其它方法和系统。

38. 发明申请

US20080315359A1 INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE 有权
标题翻译：集成电路，包括垂直二极管
公开(公告)号：US20080315359A1
公开(公告)日：2008-12-25
申请号：US11766290
申请日：2007-06-21
申请人： Thomas Happ , Jan Boris Philipp
发明人： Thomas Happ , Jan Boris Philipp
IPC分类号： H01L29/08 , H01L21/336 , H01L29/00
CPC分类号： H01L27/1021 , H01L27/101 , H01L27/24
摘要： An integrated circuit includes a vertical diode, a first electrode coupled to the vertical diode, and a resistivity changing material coupled to the first electrode. The integrated circuit includes a second electrode coupled to the resistivity changing material and a spacer having a first sidewall contacting a first sidewall of the first electrode and a sidewall of the resistivity changing material.
摘要翻译：集成电路包括垂直二极管，耦合到垂直二极管的第一电极和耦合到第一电极的电阻率变化材料。集成电路包括耦合到电阻率变化材料的第二电极和具有接触第一电极的第一侧壁和电阻率变化材料的侧壁的第一侧壁的间隔件。

39. 发明申请

US20080304311A1 INTEGRATED CIRCUIT INCLUDING LOGIC PORTION AND MEMORY PORTION 有权
标题翻译：集成电路，包括逻辑部分和存储器部分
公开(公告)号：US20080304311A1
公开(公告)日：2008-12-11
申请号：US11759528
申请日：2007-06-07
申请人： Jan Boris Philipp , Thomas Happ , Thomas Nirschl
发明人： Jan Boris Philipp , Thomas Happ , Thomas Nirschl
IPC分类号： G11C11/56 , H01L45/00
CPC分类号： G11C13/0011 , G11C11/5614 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/065 , H01L45/085 , H01L45/126 , H01L45/141 , H01L45/143 , H01L45/148 , H01L45/1683 , Y10S257/907 , Y10S257/91
摘要： An integrated circuit includes a logic portion including M conductive layers, a memory portion including N conductive layers, and at least one common top conductive layer over the logic portion and the memory portion. M is greater than N.
摘要翻译：集成电路包括包括M导电层的逻辑部分，包括N个导电层的存储部分，以及逻辑部分和存储器部分上的至少一个公共顶部导电层。 M大于N.

40. 发明申请

US20080273378A1 MULTI-LEVEL RESISTIVE MEMORY CELL USING DIFFERENT CRYSTALLIZATION SPEEDS 有权
标题翻译：使用不同结晶速度的多级电阻存储器单元
公开(公告)号：US20080273378A1
公开(公告)日：2008-11-06
申请号：US11743987
申请日：2007-05-03
申请人： Jan Boris Philipp , Thomas Happ
发明人： Jan Boris Philipp , Thomas Happ
IPC分类号： G11C11/00 , H01L47/00
CPC分类号： G11C13/0061 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0092 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/148 , Y10S977/754
摘要： An integrated circuit includes a first electrode and a second electrode. The integrated circuit includes a first resistivity changing material between the first electrode and the second electrode and a second resistivity changing material between the first electrode and the second electrode. The first resistivity changing material and the second resistivity changing material have different crystallization speeds.
摘要翻译：集成电路包括第一电极和第二电极。集成电路包括第一电极和第二电极之间的第一电阻率变化材料和第一电极和第二电极之间的第二电阻率变化材料。第一电阻率变化材料和第二电阻率变化材料具有不同的结晶速度。

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