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31. 发明授权

US5903461A Method of cell placement for an integrated circuit chip comprising chaotic placement and moving windows 失效
标题翻译：一种集成电路芯片的电池放置方法，包括混沌放置和移动窗口
公开(公告)号：US5903461A
公开(公告)日：1999-05-11
申请号：US862791
申请日：1997-05-23
申请人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
发明人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5072
摘要： In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement. Alternatively, the processors can perform different optimization processes simultaneously on a single initial placement, with the resulting processed placement having the highest fitness being selected as the optimized placement. The processors can further selectively reprocess areas of a placement having high cell interconnect congestion or other low fitness parameters.
摘要翻译：在用于生成用于集成电路芯片的优化的单元布置的物理设计自动化系统中，布局优化方法被分解成由并行处理器在表示芯片的输入数据上同时执行的多个单元布局优化处理。重组优化过程的结果以产生优化的细胞放置。分析优化的单元布局的适应性，并且如果适合度不满足预定标准，则并行处理器被控制以选择性地重复执行优化处理以进一步优化优化的单元布局。该系统可以应用于初始放置，布线，布局改进等问题。处理器可以对不同的展示位置或单个展示位置执行相同的优化过程。或者，处理器可以在单个初始放置上同时执行不同的优化过程，所得到的经处理的放置具有最佳适合度作为优化的位置。处理器可以进一步选择性地重新处理具有高单元互连拥塞或其他低适应度参数的位置的区域。

32. 发明授权

US5682322A Optimization processing for integrated circuit physical design automation system using chaotic fitness improvement method 失效
标题翻译：集成电路物理设计自动化系统优化处理采用混沌健身改进方法
公开(公告)号：US5682322A
公开(公告)日：1997-10-28
申请号：US229949
申请日：1994-04-19
申请人： Douglas B. Boyle , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Michael D. Rostoker
发明人： Douglas B. Boyle , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Michael D. Rostoker
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： The fitness of a cell placement for an integrated circuit chip is optimized by relocating at least some of cells to new locations that provide lower interconnect congestion. For each cell, the centroid of the net of cells to which the cell is connected is computed. The cell is then moved toward the centroid by a distance that is equal to the distance from the current position of the cell to the centroid multiplied by a "chaos" factor .lambda.. The value of .lambda. is selected such that the cell relocation operations will cause the placement to converge toward an optimal configuration without chaotic diversion, but with a sufficiently high chaotic element to prevent the optimization operation from becoming stuck at local fitness maxima. The new cell locations can be modified to include the effects of cells in other locations, such as by incorporating a function of cell density gradient or force direction into the computation. This spreads out clumps of cells so that the density of cells is more uniform throughout the placement. The attraction between cells in the nets is balanced against repulsion caused by a high local cell density, providing an optimized tradeoff of wirelength, feasibility and congestion.
摘要翻译：通过将至少一些单元重定位到提供较低互连拥塞的新位置来优化用于集成电路芯片的单元布局的适应性。对于每个单元，计算连接单元的单元格网格的质心。然后，电池向质心移动一个距离，该距离等于从电池的当前位置到质心乘以“混沌”因子λ的距离。选择λ的值，使得单元重定位操作将导致放置朝向最佳配置收敛而没有混沌转移，但是具有足够高的混沌元素以防止优化操作变得卡在局部适应度最大值。可以修改新的单元位置以将单元格的效果包括在其他位置，例如通过将单元密度梯度或力方向的函数合并到计算中。这扩散了细胞团，使得细胞的密度在整个放置期间更均匀。网络中的细胞之间的吸引力与由局部细胞密度较高引起的排斥平衡，从而提供了线长，可行性和拥塞的最优化折中。

33. 发明授权

US5636125A Computer implemented method for producing optimized cell placement for integrated circiut chip 失效
标题翻译：用于集成循环芯片生产优化的电池放置的计算机实现方法
公开(公告)号：US5636125A
公开(公告)日：1997-06-03
申请号：US559206
申请日：1995-11-13
申请人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
发明人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5072
摘要： In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement. Alternatively, the processors can perform different optimization processes simultaneously on a single initial placement, with the resulting processed placement having the highest fitness being selected as the optimized placement. The processors can further selectively reprocess areas of a placement having high cell interconnect congestion or other low fitness parameters.
摘要翻译：在用于产生用于集成电路芯片的优化的单元布局的物理设计自动化系统中，布局优化方法被分解成由并行处理器在表示芯片的输入数据上同时执行的多个单元布局优化处理。重组优化过程的结果以产生优化的细胞放置。分析优化的单元布局的适应性，并且如果适合度不满足预定标准，则并行处理器被控制以选择性地重复执行优化处理以进一步优化优化的单元布局。该系统可以应用于初始放置，布线，布局改进等问题。处理器可以对不同的展示位置或单个展示位置执行相同的优化过程。或者，处理器可以在单个初始放置上同时执行不同的优化过程，所得到的经处理的放置具有最佳适合度作为优化的位置。处理器可以进一步选择性地重新处理具有高单元互连拥塞或其他低适应度参数的位置的区域。

34. 发明授权

US5495419A Integrated circuit physical design automation system utilizing optimization process decomposition and parallel processing 失效
标题翻译：集成电路物理设计自动化系统利用优化过程分解和并行处理
公开(公告)号：US5495419A
公开(公告)日：1996-02-27
申请号：US229826
申请日：1994-04-19
申请人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
发明人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
IPC分类号： G06F17/50 , G06F17/00
CPC分类号： G06F17/5072
摘要： In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement. Alternatively, the processors can perform different optimization processes simultaneously on a single initial placement, with the resulting processed placement having the highest fitness being selected as the optimized placement. The processors can further selectively reprocess areas of a placement having high cell interconnect congestion or other low fitness parameters.
摘要翻译：在用于产生用于集成电路芯片的优化的单元布局的物理设计自动化系统中，布局优化方法被分解成由并行处理器在表示芯片的输入数据上同时执行的多个单元布局优化处理。重组优化过程的结果以产生优化的细胞放置。分析优化的单元布局的适应性，并且如果适合度不满足预定标准，则并行处理器被控制以选择性地重复执行优化处理以进一步优化优化的单元布局。该系统可以应用于初始放置，布线，布局改进等问题。处理器可以对不同的展示位置或单个展示位置执行相同的优化过程。或者，处理器可以在单个初始放置上同时执行不同的优化过程，所得到的经处理的放置具有最佳适合度作为优化的位置。处理器可以进一步选择性地重新处理具有高单元互连拥塞或其他低适应度参数的位置的区域。

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