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31. 发明授权

US07053692B2 Powergate control using boosted and negative voltages 有权
标题翻译：电源控制使用升压和负电压
公开(公告)号：US07053692B2
公开(公告)日：2006-05-30
申请号：US10325524
申请日：2002-12-19
申请人： Michael C. Parris , Kim C. Hardee
发明人： Michael C. Parris , Kim C. Hardee
IPC分类号： G05F3/02
CPC分类号： H03K17/6872 , H03K2217/0036
摘要： A powergating circuit includes an MOS circuit such as a memory circuit having a first power terminal and a second power terminal, a P-channel transistor having a drain coupled to the first power terminal of the MOS circuit, and an N-channel transistor having a drain coupled to the second power terminal of the MOS circuit. In order to minimize leakage current and resultant power dissipation a negative VGS voltage is established in the transistors during a standby mode and a boosted VGS voltage is established in the transistors during an active mode.
摘要翻译：电源电路包括诸如具有第一电源端和第二电源端的存储电路的MOS电路，具有耦合到MOS电路的第一电源端的漏极的P沟道晶体管和具有漏极耦合到MOS电路的第二电源端子。为了最小化泄漏电流和合成的功率耗散，在待机模式期间在晶体管中建立负的V GS电压，并且在晶体管中建立升压的V GS电压主动模式。

32. 发明授权

US06731156B1 High voltage transistor protection technique and switching circuit for integrated circuit devices utilizing multiple power supply voltages 失效
标题翻译：高压晶体管保护技术和采用多电源电压的集成电路器件的开关电路
公开(公告)号：US06731156B1
公开(公告)日：2004-05-04
申请号：US10360082
申请日：2003-02-07
申请人： Michael C. Parris , Kim C. Hardee
发明人： Michael C. Parris , Kim C. Hardee
IPC分类号： H03K17687
CPC分类号： H03K17/102
摘要： A high voltage transistor protection technique and switching circuit of especial applicability to integrated circuit devices utilizing multiple power supply voltages. In accordance with the technique of the present intention, the problems inherent in the amount of on-chip die area consumed and speed degradation of prior art circuit implementations are overcome by furnishing a substantially direct current voltage VHVP to the gate of a first transistor of a series connected thin gate oxide pair wherein VHVP≦VDSMAX (the maximum gate-to-source voltage of the first transistor) and VHVP≦VDSMAX+Vt (the maximum drain-to-source voltage of the second transistor plus the threshold voltage of the first transistor).
摘要翻译：一种高压晶体管保护技术和特别适用于利用多电源电压的集成电路器件的开关电路。根据本意图的技术，通过将基本上直流的电压VHVP提供给第一晶体管的栅极来克服现有技术电路实现中片上管芯面积消耗量和速度劣化所固有的问题，串联连接的薄栅极氧化物对，其中VHVP <= VDSMAX（第一晶体管的最大栅极 - 源极电压）和VHVP <= VDSMAX + Vt（第二晶体管的最大漏极 - 源极电压加上阈值电压第一晶体管）。

33. 发明授权

US5331601A DRAM variable row select 失效
标题翻译： DRAM变量行选择
公开(公告)号：US5331601A
公开(公告)日：1994-07-19
申请号：US13333
申请日：1993-02-04
申请人： Michael C. Parris
发明人： Michael C. Parris
IPC分类号： G11C11/406 , G11C11/408 , G11C8/00
CPC分类号： G11C11/406 , G11C11/408
摘要： A memory device circuit that alters the input refresh addresses to access fewer memory cells to save power, or to address more memory cells to decrease the refresh time. The circuit contains a simple transistor configuration that blocks certain address bits, then substitutes active bits in their place to the address decoder. The circuit also includes a controller that is responsive to the memory device entering the refresh mode. When the device is used in refresh mode, the address bits may be passed unblocked to the address decoder for full user control.
摘要翻译：一种存储器件电路，其改变输入刷新地址以访问更少的存储器单元以节省功率，或者寻址更多的存储器单元以减少刷新时间。该电路包含阻塞某些地址位的简单晶体管配置，然后将其位置的有效位代替到地址解码器。电路还包括响应于存储器件进入刷新模式的控制器。当设备在刷新模式下使用时，地址位可以被非阻塞地传送到地址解码器以进行完全用户控制。

34. 发明授权

US08692611B2 Power boosting circuit for semiconductor packaging 有权
标题翻译：半导体封装功率升压电路
公开(公告)号：US08692611B2
公开(公告)日：2014-04-08
申请号：US13287237
申请日：2011-11-02
申请人： Richard Dewitt Crisp , Michael C. Parris , Mark Kroot
发明人： Richard Dewitt Crisp , Michael C. Parris , Mark Kroot
IPC分类号： G05F1/10
CPC分类号： G06F1/26 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic package includes a microelectronic element operable to output a discrete-value logic signal indicating an imminent increase in demand for current by at least some portion of the microelectronic element. An active power delivery element within the package is operable by the logic signal to increase current delivery to the microelectronic element.
摘要翻译：微电子封装包括微电子元件，其可操作以输出离散值逻辑信号，该离散值逻辑信号指示微电子元件的至少一部分即将对电流的需求增加。封装内的有功功率输送元件可由逻辑信号操作，以增加对微电子元件的电流输送。

35. 发明授权

US07580304B2 Multiple bus charge sharing 有权
标题翻译：多路总线充电共享
公开(公告)号：US07580304B2
公开(公告)日：2009-08-25
申请号：US11764007
申请日：2007-06-15
申请人： Michael C. Parris
发明人： Michael C. Parris
IPC分类号： G11C7/00
CPC分类号： G06F13/4077 , Y02D10/14 , Y02D10/151
摘要： A charge-sharing circuit includes a first input bus pair, a second input bus pair, and an output bus pair. A capacitor is coupled between a first internal node and a second internal node. A first circuit selectively couples the first internal node to the first input bus pair, the second input bus pair and the output bus pair. A second circuit selectively couples the second internal node to the first input bus pair, the second input bus pair and the output bus pair. A third circuit selectively couples the first input bus pair to a reference voltage. A fourth circuit selectively couples the second input bus pair to the reference voltage. The third circuit is activated when the first input bus pair is inactive and charge is shared between the second bus pair and the output bus pair. The fourth circuit is activated when the second input bus pair is inactive and charge is shared between first bus pair and the output bus pair.
摘要翻译：电荷共享电路包括第一输入总线对，第二输入总线对和输出总线对。电容器耦合在第一内部节点和第二内部节点之间。第一电路选择性地将第一内部节点耦合到第一输入总线对，第二输入总线对和输出总线对。第二电路将第二内部节点选择性地耦合到第一输入总线对，第二输入总线对和输出总线对。第三电路将第一输入总线对选择性地耦合到参考电压。第四电路将第二输入总线对选择性地耦合到参考电压。当第一个输入总线对无效并且第二个总线对和输出总线对之间共享电荷时，第三个电路被激活。当第二个输入总线对不活动且第一个总线对和输出总线对共用电荷时，第四个电路被激活。

36. 发明申请

US20090073786A1 EARLY WRITE WITH DATA MASKING TECHNIQUE FOR INTEGRATED CIRCUIT DYNAMIC RANDOM ACCESS MEMORY (DRAM) DEVICES AND THOSE INCORPORATING EMBEDDED DRAM 审中-公开
标题翻译：用于集成电路动态随机存取存储器（DRAM）器件和嵌入式DRAM的数据显示技术的早期写入
公开(公告)号：US20090073786A1
公开(公告)日：2009-03-19
申请号：US11855804
申请日：2007-09-14
申请人： Michael C. Parris , Kim C. Hardee
发明人： Michael C. Parris , Kim C. Hardee
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G11C7/1006
摘要： An early write with data masking technique for dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM. The technique of the present invention allows for early writes to DRAM arrays with direct bit, byte or word data masking capability.
摘要翻译：早期为动态随机存取存储器（DRAM）器件和嵌入式DRAM的器件提供数据掩蔽技术。本发明的技术允许使用直接位，字节或字数据屏蔽能力对DRAM阵列的早期写入。

37. 发明申请

US20080174340A1 OPTIMIZED CHARGE SHARING FOR DATA BUS SKEW APPLICATIONS 有权
标题翻译：数据总线应用的优化充电共享
公开(公告)号：US20080174340A1
公开(公告)日：2008-07-24
申请号：US11759823
申请日：2007-06-07
申请人： Michael C. Parris , Kim C. Hardee
发明人： Michael C. Parris , Kim C. Hardee
IPC分类号： H03K19/0944
CPC分类号： G06F13/4077
摘要： A circuit and method provide a charge sharing function during skewed data bus conditions in an integrated circuit memory. The charge sharing circuit includes two additional circuit blocks, one coupled to each of the capacitive lines in the charge-sharing line set, to provide the charge recycling feature. An extra clock signal is active one cycle early during a first clock period to trigger an extra drive circuit to generate a voltage differential on a first capacitive line that is similar to the voltage level generated when real data is being propagated. The presence of an extra voltage signal on the first capacitive line takes place earlier than what would normally happen and allows for proper charge sharing between a second capacitive line and the first capacitive line. Also, there is an additional control signal associated with a last clock period following normal non-skewed charge sharing. The additional control signal triggers a reference read circuit to generate data and a voltage on the first capacitive lines similar to the voltage present during real data for proper charge sharing. The additional read and drive circuit blocks are partial copies of the normal read and drive circuits so that a matching voltage can be generated on the appropriate capacitive signal lines.
摘要翻译：电路和方法在集成电路存储器的偏斜数据总线条件下提供电荷共享功能。电荷共享电路包括两个额外的电路块，一个耦合到电荷共享线路组中的每个电容线，以提供电荷回收特征。额外的时钟信号在第一时钟周期内早一个周期激活，以触发额外的驱动电路，以在与传播实际数据时产生的电压电平类似的第一电容线上产生电压差。在第一电容线路上存在额外的电压信号比通常发生的情况更早发生，并允许在第二电容线路和第一电容线路之间进行适当的电荷共享。此外，存在与正常非偏斜电荷共享之后的最后时钟周期相关联的附加控制信号。附加控制信号触发参考读取电路，以在第一电容线路上产生数据和电压，类似于实际数据期间存在的用于适当电荷共享的电压。附加的读取和驱动电路块是正常读取和驱动电路的部分副本，使得可以在适当的电容性信号线上产生匹配的电压。

38. 发明授权

US06788590B2 Bitline reference voltage circuit 有权
标题翻译：位线参考电压电路
公开(公告)号：US06788590B2
公开(公告)日：2004-09-07
申请号：US10345736
申请日：2003-01-16
申请人： Michael C. Parris , Kim C. Hardee
发明人： Michael C. Parris , Kim C. Hardee
IPC分类号： G11C1604
CPC分类号： G11C11/4094 , G11C7/12
摘要： A bitline reference voltage circuit according to the present invention includes a first transistor having a current path coupled between a first bitline and an intermediate node, and a gate for receiving a first control signal, a second transistor having a current path coupled between a second bitline and the intermediate node, and a gate for receiving a second control signal, a third transistor having current path coupled between the intermediate node and a source of constant voltage, and a gate for receiving a third control signal, and a capacitor coupled between the intermediate node and the source of constant voltage.
摘要翻译：根据本发明的位线参考电压电路包括具有耦合在第一位线和中间节点之间的电流通路的第一晶体管和用于接收第一控制信号的栅极，第二晶体管具有耦合在第二位线中间节点和用于接收第二控制信号的栅极，具有耦合在中间节点和恒定电压源之间的电流路径的第三晶体管，以及用于接收第三控制信号的栅极和耦合在中间节点之间的电容器节点和恒压源。

39. 发明授权

US06738302B1 Optimized read data amplifier and method for operating the same in conjunction with integrated circuit devices incorporating memory arrays 有权
标题翻译：优化的读数据放大器及其操作方法与结合存储器阵列的集成电路器件结合使用
公开(公告)号：US06738302B1
公开(公告)日：2004-05-18
申请号：US10360146
申请日：2003-02-07
申请人： Michael C. Parris , Kim C. Hardee
发明人： Michael C. Parris , Kim C. Hardee
IPC分类号： G11C706
CPC分类号： G11C11/4091 , G11C7/065
摘要： An optimized read data amplifier for the output data path of integrated circuit memory arrays comprises a fast, low power and small on-chip area consuming circuit which is advantageously effectuated through the combined application of “current sensing” and “voltage sensing” techniques. In a particular embodiment disclosed herein, an amplifier enable signal is timed with the column read address so that the amplifier is turned “off” when not in use and both data read lines (“DR” and “DRB”) are precharged “high”. No clocking of the read data amplifier is required in order to obviate undesired clock latencies and pipelining and a simple mechanism is implemented such that control of power-up and power-down results in further power savings.
摘要翻译：用于集成电路存储器阵列的输出数据路径的优化读数据放大器包括快速，低功率和小片上区域消耗电路，其有利地通过组合应用“电流感测”和“电压感测”技术来实现。在本文公开的特定实施例中，放大器使能信号与列读取地址定时，使得放大器在不使用时被“关闭”，并且两个数据读取行（“DR”和“DRB”）都被预充电为“高” 。不需要读数据放大器的时钟，以便消除不期望的时钟延迟和流水线，并且实现简单的机制，使得上电和掉电的控制导致进一步的功率节省。

40. 发明授权

US06625069B1 Data path decoding technique for an embedded memory array 有权
公开(公告)号：US06625069B1
公开(公告)日：2003-09-23
申请号：US10374562
申请日：2003-02-25
申请人： Michael C. Parris , Kim C. Hardee
发明人： Michael C. Parris , Kim C. Hardee
IPC分类号： G11C700
CPC分类号： G11C11/4093 , G11C7/1006 , G11C2207/104
摘要： A data path decoding technique and architecture for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (“DRAM”) arrays provides an effective second level of decoding resulting in a need for routing fewer column select lines to the sense amplifiers as compared with existing designs while concomitantly providing for shortened local data lines resulting in less undesired resistance and capacitance. The technique and architecture of the present invention requires no additional on-chip area to that required by existing designs and adds no new gate delays or pass gates to the critical read data or write data paths. This is effectuated by the incorporation of an address function with the read/write enable (“RWEN”) or separate read enable (“REN”) and write enable (“WEN”) signals. Consequently, half as many column select lines need be routed to the sense amplifiers since a second level of column decoding is provided.

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