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31. 发明授权

US07911369B2 Pipelined AD converter 有权
标题翻译：流水线AD转换器
公开(公告)号：US07911369B2
公开(公告)日：2011-03-22
申请号：US12600784
申请日：2008-08-21
申请人： Takashi Morie , Kazuo Matsukawa , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga
发明人： Takashi Morie , Kazuo Matsukawa , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga
IPC分类号： H03M1/38
CPC分类号： H03M1/0678 , H03M1/0695 , H03M1/44
摘要： A pipelined AD converter (1) includes a plurality of conversion stages (11, 11, . . . ). In each of the conversion stages, an analog-to-digital conversion circuit (101) converts an input voltage (Vin) from the preceding stage to a digital code (Dout). A digital-to-analog conversion circuit (102) converts the digital code obtained by the analog-to-digital conversion circuit to an intermediate voltage (Vda). A charge operation circuit (103) has: a capacitor section (C1, C2) for sampling the input voltage; and an amplifier section (104) for amplifying a mixed voltage of the input voltage sampled by the capacitor section and the intermediate voltage obtained by the digital-to-analog conversion circuit. The amplifier section (104) includes a plurality of op-amps (amp1, amp1, . . . ) having the same configuration and connected in parallel with each other.
摘要翻译：流水线式AD转换器（1）包括多个转换级（11,11 ...）。在每个转换级中，模数转换电路（101）将来自前级的输入电压（Vin）转换为数字代码（Dout）。数模转换电路（102）将由模数转换电路获得的数字代码转换为中间电压（Vda）。充电操作电路（103）具有用于对输入电压进行采样的电容器部（C1，C2）以及用于放大由电容器部分采样的输入电压和由数模转换电路获得的中间电压的混合电压的放大器部分（104）。放大器部分（104）包括具有相同配置并且彼此并联的多个运算放大器（amp1，amp1 ...）。

32. 发明申请

US20100149010A1 PIPELINED AD CONVERTER 有权
标题翻译：管路AD转换器
公开(公告)号：US20100149010A1
公开(公告)日：2010-06-17
申请号：US12600784
申请日：2008-08-21
申请人： Takashi Morie , Kazuo Matsukawa , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga
发明人： Takashi Morie , Kazuo Matsukawa , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga
IPC分类号： H03M1/38 , H03M1/00
CPC分类号： H03M1/0678 , H03M1/0695 , H03M1/44
摘要： A pipelined AD converter (1) includes a plurality of conversion stages (11, 11, . . . ). In each of the conversion stages, an analog-to-digital conversion circuit (101) converts an input voltage (Vin) from the preceding stage to a digital code (Dout). A digital-to-analog conversion circuit (102) converts the digital code obtained by the analog-to-digital conversion circuit to an intermediate voltage (Vda). A charge operation circuit (103) has: a capacitor section (C1, C2) for sampling the input voltage; and an amplifier section (104) for amplifying a mixed voltage of the input voltage sampled by the capacitor section and the intermediate voltage obtained by the digital-to-analog conversion circuit. The amplifier section (104) includes a plurality of op-amps (amp1, amp1, . . . ) having the same configuration and connected in parallel with each other.
摘要翻译：流水线式AD转换器（1）包括多个转换级（11,11 ...）。在每个转换级中，模数转换电路（101）将来自前级的输入电压（Vin）转换为数字代码（Dout）。数模转换电路（102）将由模数转换电路获得的数字代码转换为中间电压（Vda）。充电操作电路（103）具有用于对输入电压进行采样的电容器部（C1，C2）以及用于放大由电容器部分采样的输入电压和由数模转换电路获得的中间电压的混合电压的放大器部分（104）。放大器部分（104）包括具有相同配置并且彼此并联的多个运算放大器（amp1，amp1 ...）。

33. 发明申请

US20090115502A1 REFERENCE CURRENT CIRCUIT, REFERENCE VOLTAGE CIRCUIT, AND STARTUP CIRCUIT 有权
标题翻译：参考电流电路，参考电压电路和启动电路
公开(公告)号：US20090115502A1
公开(公告)日：2009-05-07
申请号：US12093393
申请日：2007-09-04
申请人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Masayoshi Kinoshita
发明人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Masayoshi Kinoshita
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： A current mirror circuit 10 is formed to have a current ratio (a transistor size ratio) of 1:m. As well, respective pairs of nMOS transistors MN1, MN3 and nMOS transistors MN2, MN4 are formed to have a current ratio of 1:m. Two currents output from the current mirror circuit 10 are each distributed to two. The distributed currents flowing in the nMOS transistors MN2, MN4 are added and are then allowed to flow into one resistor R2. Hence, for the resistor R2, only one resistor in which current of double flows suffices when m=1, for example. This effortlessly reduces the necessary resistance to one fourth.
摘要翻译：电流镜电路10形成为具有1：m的电流比（晶体管尺寸比）。同样，各对nMOS晶体管MN1，MN3和nMOS晶体管MN2，MN4形成为具有1：m的电流比。从电流镜电路10输出的两个电流分别分配给两个。在nMOS晶体管MN2，MN4中流动的分布电流相加，然后被允许流入一个电阻器R2。因此，对于电阻器R2，例如当m = 1时，只有一个双电流的电流就足够了。这轻而易举地减少了四分之一的必要阻力。

34. 发明授权

US07495504B2 Reference voltage generation circuit 有权
标题翻译：参考电压发生电路
公开(公告)号：US07495504B2
公开(公告)日：2009-02-24
申请号：US10588191
申请日：2005-02-14
申请人： Masayoshi Kinoshita , Shiro Sakiyama
发明人： Masayoshi Kinoshita , Shiro Sakiyama
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F3/30 , H03F3/45183 , H03F3/45475 , H03F2200/153 , H03F2203/45136
摘要： In a reference voltage generation circuit, a bandgap reference circuit (BGR circuit) 1 includes diode element D1 and D2 having different current densities, three resistive elements R1, R2 and R3, a P-type first transistor Tr1 for supplying a current to a reference voltage output terminal O, a P-type second transistor Tr2 for determining a drain current flowing through the first transistor Tr1 by a current mirror structure, and a feedback type control circuit 11. The BGR circuit 1 is connected to a pull-down circuit 2. The pull-down circuit 2 includes a resistive element R4 and a P-type transistor Tr4 which are connected in series. The resistive element R4 is connected to a drain terminal of the second P-type transistor Tr2. The P-type transistor Tr4 has a gate terminal connected to the reference voltage output terminal O and a grounded drain terminal. Thus, the number of elements and current consumption in the start-up circuit which shifts the operation from an abnormal stabilization point to a normal stabilization point are reduced.
摘要翻译：在参考电压产生电路中，带隙参考电路（BGR电路）1包括具有不同电流密度的二极管元件D1和D2，三个电阻元件R1，R2和R3，用于向参考电压提供电流的P型第一晶体管Tr1 电压输出端子O，用于通过电流镜结构确定流过第一晶体管Tr1的漏极电流的P型第二晶体管Tr2和反馈型控制电路11.BGR电路1连接到下拉电路2 下拉电路2包括串联连接的电阻元件R4和P型晶体管Tr4。电阻元件R4连接到第二P型晶体管Tr2的漏极端子。 P型晶体管Tr4具有连接到参考电压输出端子O的栅极端子和接地漏极端子。因此，将操作从异常稳定点转移到正常稳定点的起动电路中的元件数量和电流消耗减少。

35. 发明申请

US20080315933A1 PULSE SYNTHESIS CIRCUIT 有权
标题翻译：脉冲合成电路
公开(公告)号：US20080315933A1
公开(公告)日：2008-12-25
申请号：US12133901
申请日：2008-06-05
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
IPC分类号： H03K3/00
CPC分类号： H03K5/00006 , H03K5/13
摘要： A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.
摘要翻译： n个第一脉冲信号中的每一个的高电平周期部分或全部与在所有n个第二脉冲信号都处于低电平的期间重叠。 n个第二脉冲信号中的每一个的高电平周期部分地或完全地重叠在所有n个第一脉冲信号处于低电平的时段。 n个第一驱动晶体管中的每一个包括连接到接地节点的源极，连接到第一节点的漏极以及接收相应的一个第一脉冲信号的栅极。 n个第二驱动晶体管中的每一个包括连接到接地节点的源极，连接到第二节点的漏极和接收相应的一个第二脉冲信号的栅极。电流镜电路允许对应于流过第二节点的电流的电流流过第一节点。

36. 发明申请

US20080068101A1 Coupled Ring Oscillator and Method for Laying Out the Same 有权
标题翻译：耦合振荡器及其放置方法
公开(公告)号：US20080068101A1
公开(公告)日：2008-03-20
申请号：US11884270
申请日：2006-05-25
申请人： Shiro Dosho , Shiro Sakiyama , Noriaki Takeda
发明人： Shiro Dosho , Shiro Sakiyama , Noriaki Takeda
IPC分类号： H03K3/03
CPC分类号： H03K3/0315
摘要： A coupled ring oscillator includes n ring oscillators (20) each including m inverter circuits (10), and a phase-coupling loop (40) in which m×n phase-coupling circuits (30), each of which couples signal phases at two points in a certain phase mode, are connected with each other to form a loop. Connection points at which the inverter circuits (10) are connected with each other and the connection points at which the phase-coupling circuits (30) are connected with each other are connected bijectively; and each of the inverter circuits (10) is connected between two points that divide the phase-coupling circuits (30) into two parts at a certain ratio.
摘要翻译：耦合环形振荡器包括n个环形振荡器（20），每个环形振荡器（20）包括m个逆变器电路（10）和相位耦合回路（40），其中mxn个相位耦合电路（30）一定的相位模式相互连接形成一个环路。逆变器电路（10）彼此连接的连接点和相位耦合电路（30）彼此连接的连接点彼此连接; 并且每个逆变器电路（10）连接在将相耦合电路（30）以一定比例分成两部分的两个点之间。

37. 发明申请

US20080007243A1 Reference voltage generation circuit 有权
标题翻译：参考电压发生电路
公开(公告)号：US20080007243A1
公开(公告)日：2008-01-10
申请号：US11783800
申请日：2007-04-12
申请人： Akinori Matsumoto , Shiro Sakiyama , Takashi Morie
发明人： Akinori Matsumoto , Shiro Sakiyama , Takashi Morie
IPC分类号： G05F3/16
CPC分类号： G05F3/30
摘要： A reference voltage generation circuit of the present invention includes: a band gap reference-type current generation circuit for controlling each of currents flowing through a first current path and a second current path, which are extending from a first node to a second node, to be a predetermined reference current, by utilizing a voltage difference occurring between a pair of transistors or diodes; and a resistive load circuit provided between the second node and a third node.
摘要翻译：本发明的参考电压产生电路包括：带隙基准电流产生电路，用于控制从第一节点延伸到第二节点的流过第一电流路径和第二电流路径的每个电流到通过利用在一对晶体管或二极管之间出现的电压差来作为预定的参考电流; 以及设置在第二节点和第三节点之间的电阻性负载电路。

38. 发明申请

US20070183175A1 Charge pumping circuit 有权
标题翻译：充电泵电路
公开(公告)号：US20070183175A1
公开(公告)日：2007-08-09
申请号：US11637687
申请日：2006-12-13
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata
IPC分类号： H02M7/00
CPC分类号： H02M3/07 , H03L7/0895 , H03L7/0896
摘要： A charge pumping circuit includes a first switch for controlling one of push and pull operations in accordance with a first control signal; a current mirror circuit constructed from transistors each having a different polarity from the first switch; a second switch for controlling current input to the current mirror circuit in accordance with a second control signal, the second switch being constructed from a transistor having the same characteristic as a transistor used for constructing the first switch; a first MOS capacitor one end of which is connected to an input side of the current mirror circuit; a second MOS capacitor receiving, at one end thereof, a current concerned with the push and pull operations; and a voltage buffer connected to the first and second MOS capacitors. The other of the push and pull operations is performed with an output current of the current mirror circuit.
摘要翻译：电荷泵浦电路包括：第一开关，用于根据第一控制信号控制推挽操作中的一个; 由与所述第一开关具有不同极性的晶体管构成的电流镜电路; 第二开关，用于根据第二控制信号控制到电流镜电路的电流输入，第二开关由具有与用于构造第一开关的晶体管相同的特性的晶体管构成; 第一MOS电容器，其一端连接到电流镜电路的输入侧; 在其一端接收与推挽操作有关的电流的第二MOS电容器; 以及连接到第一和第二MOS电容器的电压缓冲器。推挽操作中的另一个用电流镜电路的输出电流进行。

39. 发明授权

US07030688B2 Low-pass filter for a PLL, phase-locked loop and semiconductor integrated circuit 失效
标题翻译：用于PLL，锁相环和半导体集成电路的低通滤波器
公开(公告)号：US07030688B2
公开(公告)日：2006-04-18
申请号：US10500875
申请日：2003-05-22
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
IPC分类号： H03K5/00
CPC分类号： H03L7/0812 , H03L7/0891 , H03L7/0893 , H03L7/0896 , H03L7/093
摘要： The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.
摘要翻译：本发明提供一种适合用作PLL或DLL的环路滤波器的低通滤波器，其具有与常规滤波特性相同的滤波特性，并且可以在较小的电路面积中实现。低通滤波器包括第一滤波装置（31），用于接收输入到低通滤波器的输入信号作为输入，并输出第一电压; 包括在第一过滤装置（31）中的用于允许第一电流根据第一电压流动的电路元件（311）电流产生装置（32），用于以给定的速率产生与第一电流的第二电流; 第二滤波装置（33），用于接受第二电流作为输入并输出第二电压; 以及添加装置（34），用于将第一电压和第二电压相加，并输出低通滤波器的输出信号，其中第二电流被设置为小于第一电流。

40. 发明授权

US06914259B2 Multi-chip module, semiconductor chip, and interchip connection test method for multi-chip module 失效
标题翻译：多芯片模块，半导体芯片和芯片间连接测试方法
公开(公告)号：US06914259B2
公开(公告)日：2005-07-05
申请号：US10262669
申请日：2002-10-02
申请人： Shiro Sakiyama , Masayoshi Kinoshita , Jun Kajiwara
发明人： Shiro Sakiyama , Masayoshi Kinoshita , Jun Kajiwara
IPC分类号： G01R31/28 , G01R31/3185 , H01L21/822 , H01L23/52 , H01L25/18 , H01L27/04 , H01L23/58
CPC分类号： G11C29/022 , G01R31/2853 , G01R31/318505 , G01R31/318513 , H01L25/18 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2924/00014 , H01L2924/3011 , H01L2224/05599
摘要： A multi-chip module is implemented by connecting a plurality of connection pads provided on, for example, two semiconductor chips via a plurality of conductive connecting members. To carry out a test for determining the quality of the connection between the two semiconductor chips, the multi-chip module is further provided with a plurality of switch elements so that the plurality of connecting members can be electrically conducted in a serial manner via the connection pads of the semiconductor chips. During the connection test, all the switch elements are turned on, and the impedance between both ends of the line including the plurality of connecting members conducted in a serial manner is measured using two probing pads.
摘要翻译：通过经由多个导电连接构件连接设置在例如两个半导体芯片上的多个连接焊盘来实现多芯片模块。为了进行用于确定两个半导体芯片之间的连接质量的测试，多芯片模块还设置有多个开关元件，使得多个连接构件可以经由连接以串联方式导电半导体芯片的焊盘。在连接测试期间，所有的开关元件都被接通，并且使用两个探测器来测量包括以串行方式传导的多个连接构件的线的两端之间的阻抗。

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