专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07443043B2 Circuit device and method of manufacture thereof 有权
标题翻译：电路装置及其制造方法
公开(公告)号：US07443043B2
公开(公告)日：2008-10-28
申请号：US10733724
申请日：2003-12-11
申请人： Noriaki Sakamoto
发明人： Noriaki Sakamoto
IPC分类号： H01L21/44
CPC分类号： H01L24/97 , H01L23/3107 , H01L23/49548 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/32245 , H01L2224/451 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01059 , H01L2924/01078 , H01L2924/01082 , H01L2924/12042 , H01L2924/13055 , H01L2924/181 , H01L2924/19043 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2924/00015 , H01L2224/05599
摘要： A circuit device 10 comprises a die pad 11, bonding pads 12, a circuit element 9, affixed onto die pad 11, and an insulating resin 14, which seals die pad 11, bonding pads 12, and circuit element 9, and has a configuration wherein recessed parts 15 are formed at parts of the side surfaces of insulating resin 14, and side surface of the conductive patterns that are disposed at peripheral parts are exposed from recessed parts 15. By bonding pads 12, which are to become connecting electrodes to the exterior, being exposed at the side surfaces, fillets of a brazing material 19 are formed at the sides of the device when circuit device 10 is mounted.
摘要翻译：电路装置10包括贴片11，接合焊盘12，固定在芯片焊盘11上的电路元件9和密封管芯焊盘11，焊盘12和电路元件9的绝缘树脂14，并且具有其中凹部15形成在绝缘树脂14的侧表面的部分处，并且设置在周边部分的导电图案的侧表面从凹部15露出。通过将要成为外部的连接电极的焊盘12暴露在侧表面处，当安装电路装置10时，在装置的侧面形成钎焊材料19的圆角。

32. 发明授权

US07332808B2 Semiconductor module and method of manufacturing the same 有权
标题翻译：半导体模块及其制造方法
公开(公告)号：US07332808B2
公开(公告)日：2008-02-19
申请号：US11393531
申请日：2006-03-29
申请人： Noriaki Sakamoto , Chikara Kaneta , Yoshihiko Yanase , Yoshiyuki Kobayashi
发明人： Noriaki Sakamoto , Chikara Kaneta , Yoshihiko Yanase , Yoshiyuki Kobayashi
IPC分类号： H01L23/34
CPC分类号： H01L25/162 , G01D11/245 , H01L23/3121 , H01L23/3135 , H01L23/49531 , H01L24/45 , H01L24/48 , H01L25/165 , H01L2224/16 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2224/83192 , H01L2224/92247 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/19041 , H01L2924/19107 , H05K1/141 , H05K3/284 , H05K3/328 , H01L2924/00 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor module according to the invention includes: an island formed of a conductive material; a plurality of leads disposed in vicinity of the island; a resin sealing body which is mounted on the island and disposed such that a back surface of a circuit board on which semiconductor elements is exposed upward; a sensor which is mounted on the back surface of the circuit board; and a thin metallic wire which electrically connects the circuit board with the leads. The island, the resin sealing body, the sensor, and parts of the leads are sealed by a second sealing resin.
摘要翻译：根据本发明的半导体模块包括：由导电材料形成的岛; 设置在岛附近的多个引线; 树脂密封体，其安装在岛上并且设置成使得半导体元件向上露出的电路板的背面; 安装在电路板背面的传感器; 以及将电路板与引线电连接的细金属线。岛，树脂密封体，传感器和引线的一部分被第二密封树脂密封。

33. 发明申请

US20070254231A1 Toner for Electrophotography 审中-公开
标题翻译：调色剂用于电子照相
公开(公告)号：US20070254231A1
公开(公告)日：2007-11-01
申请号：US11740021
申请日：2007-04-25
申请人： Noriaki Sakamoto , Yasuko Nakagawa
发明人： Noriaki Sakamoto , Yasuko Nakagawa
IPC分类号： G03G9/08
CPC分类号： G03G9/0806 , G03G9/08708 , G03G9/08711 , G03G9/08728 , G03G9/08733 , G03G9/08793 , G03G9/08795 , G03G9/08797
摘要： A toner for electrophotography, wherein the toner is prepared by a suspension polymerization or emulsion polymerization from a monomer composition comprising a monovinyl monomer and a coloring agent, and a filtration velocity of the toner is in the range of 0.1 to 3.0 mL/min. The filtration velocity is obtained by an evaluation method comprising following evaluation steps: (i) 15 mg of a toner is added to 5 mL of THF, and soluble component in the toner is dissolved in THF completely to prepare a sample liquid; and (ii) the sample liquid is filtrated at the temperature of 25° C. and pressure of 0.15 kgf/cm2 is applied using a filter wherein an area thereof is 4.0 cm2 and a pore size thereof is 0.45 μm to measure a filtration time wherein 1 mL of the sample liquid is passed through the filter, and a filtration velocity is determined using the filtration time by a following formula, Filtration velocity (mL/min)=1 (mL)/filtration time (min).
摘要翻译：一种用于电子照相的调色剂，其中调色剂是由包含单乙烯基单体和着色剂的单体组合物的悬浮聚合或乳液聚合制备的，调色剂的过滤速度在0.1至3.0mL / min的范围内。通过包括以下评价步骤的评价方法获得过滤速度：（i）将15mg调色剂加入到5mL THF中，并将调色剂中的可溶成分完全溶解在THF中以制备样品液; 和（ii）样品液体在25℃的温度下过滤，并使用其面积为4.0cm 2的过滤器施加0.15kgf / cm 2的压力， SUP>，其孔径为0.45μm，以测量其中1mL样品液体通过过滤器的过滤时间，并且使用过滤时间通过下式确定过滤速度，<β在线式过滤速度（mL / min）= 1（mL）/过滤时间（min）。<？in-line-formula description =“In-line Formulas”end =“尾巴”？>

34. 发明授权

US07276793B2 Semiconductor device and semiconductor module 失效
标题翻译：半导体器件和半导体模块
公开(公告)号：US07276793B2
公开(公告)日：2007-10-02
申请号：US11054025
申请日：2005-02-08
申请人： Noriaki Sakamoto , Yoshiyuki Kobayashi , Junji Sakamoto , Shigeaki Mashimo , Katsumi Okawa , Eiju Maehara , Kouji Takahashi
发明人： Noriaki Sakamoto , Yoshiyuki Kobayashi , Junji Sakamoto , Shigeaki Mashimo , Katsumi Okawa , Eiju Maehara , Kouji Takahashi
IPC分类号： H01L23/48
CPC分类号： H05K1/188 , H01L21/4821 , H01L21/4832 , H01L21/56 , H01L21/561 , H01L21/565 , H01L23/3107 , H01L23/49541 , H01L23/49548 , H01L23/49575 , H01L23/49582 , H01L24/05 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/165 , H01L25/50 , H01L2221/68377 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05557 , H01L2224/05647 , H01L2224/16 , H01L2224/16245 , H01L2224/32057 , H01L2224/32245 , H01L2224/4807 , H01L2224/48091 , H01L2224/48247 , H01L2224/4845 , H01L2224/48464 , H01L2224/48465 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2224/83385 , H01L2224/85447 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01039 , H01L2924/01047 , H01L2924/0105 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/18301 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H05K1/187 , H05K3/06 , H05K3/202 , H01L2224/85 , H01L2924/00012 , H01L2224/45099 , H01L2924/00 , H01L2924/01046 , H01L2924/3512
摘要： A semiconductor device is provided wherein conductive paths 40, formed of crystal that grows better along the X-Y axis than along the Z axis, are embedded in an insulating resin 44, and the back surface of the conductive path 40 is exposed through the insulating resin 44 and sealed. With this arrangement, fractures of the conductive paths 40 embedded in the insulating resin 44 are suppressed.
摘要翻译：提供一种半导体器件，其中由晶体形成的导电路径40沿着XY轴比沿着Z轴更好地嵌入绝缘树脂44中，并且导电路径40的背表面通过绝缘树脂44暴露并密封。通过这种布置，抑制了嵌入绝缘树脂44中的导电通路40的断裂。

35. 发明申请

US20070205017A1 CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：电路装置及其制造方法
公开(公告)号：US20070205017A1
公开(公告)日：2007-09-06
申请号：US11307283
申请日：2006-01-30
申请人： Sadamichi Takakusaki , Noriaki Sakamoto , Motoichi Nezu , Yusuke Igarashi
发明人： Sadamichi Takakusaki , Noriaki Sakamoto , Motoichi Nezu , Yusuke Igarashi
IPC分类号： H05K1/16 , H05K7/00
CPC分类号： H05K3/341 , H01L24/83 , H01L2224/45124 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73265 , H01L2224/83 , H01L2924/01322 , H01L2924/01327 , H01L2924/14 , H01L2924/15787 , H01L2924/19105 , H01L2924/30107 , H05K3/243 , H05K3/244 , H05K3/284 , H05K3/3463 , H05K2201/0391 , H05K2201/10969 , Y02P70/613 , Y10T29/4913 , Y10T29/49155 , H01L2924/00014 , H01L2924/00
摘要： In a hybrid integrated circuit device that is a circuit device of the present invention, a conductive pattern including pads is formed on a surface of a substrate. A first pad is formed to be relatively large since a heat sink is mounted thereon. A second pad is a small pad to which a chip component or a small signal transistor is fixed. In the present invention, a plated film made of nickel is formed on a surface of the first pad. Therefore, the first pad and a solder never come into contact with each other. Thus, a Cu/Sn alloy layer having poor soldering properties is not generated but a Ni/Sn alloy layer having excellent soldering properties is generated. Consequently, occurrence of sink in the melted solder is suppressed.
摘要翻译：在作为本发明的电路装置的混合集成电路装置中，在基板的表面上形成包括焊盘的导电图案。由于在其上安装散热器，所以形成第一焊盘相对较大。第二焊盘是固定芯片部件或小信号晶体管的小焊盘。在本发明中，在第一焊盘的表面上形成由镍制成的镀膜。因此，第一焊盘和焊料不会彼此接触。因此，不会产生焊接性差的Cu / Sn合金层，而是产生焊接性优异的Ni / Sn合金层。因此，抑制熔融焊料中的沉陷的发生。

36. 发明授权

US07138296B2 Board for manufacturing a BGA and method of manufacturing semiconductor device using thereof 有权
标题翻译：制造BGA的板以及使用该半导体器件的制造方法
公开(公告)号：US07138296B2
公开(公告)日：2006-11-21
申请号：US10854946
申请日：2004-05-26
申请人： Noriaki Sakamoto , Yoshiyuki Kobayashi , Junji Sakamoto , Shigeaki Mashimo , Katsumi Okawa , Eiju Maehara , Kouji Takahashi
发明人： Noriaki Sakamoto , Yoshiyuki Kobayashi , Junji Sakamoto , Shigeaki Mashimo , Katsumi Okawa , Eiju Maehara , Kouji Takahashi
IPC分类号： H01L21/44
CPC分类号： H01L24/32 , H01L21/4832 , H01L21/561 , H01L23/3128 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2221/68377 , H01L2224/05554 , H01L2224/16225 , H01L2224/16245 , H01L2224/32057 , H01L2224/32225 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/484 , H01L2224/48463 , H01L2224/48472 , H01L2224/48599 , H01L2224/48639 , H01L2224/48644 , H01L2224/48655 , H01L2224/48669 , H01L2224/48699 , H01L2224/48739 , H01L2224/48744 , H01L2224/48755 , H01L2224/48769 , H01L2224/49171 , H01L2224/73265 , H01L2224/83385 , H01L2224/85201 , H01L2224/85205 , H01L2224/85439 , H01L2224/85444 , H01L2224/85455 , H01L2224/85469 , H01L2224/92 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/014 , H01L2924/07802 , H01L2924/10161 , H01L2924/14 , H01L2924/15183 , H01L2924/15184 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/19043 , H01L2924/00014 , H01L2224/85 , H01L2224/83 , H01L2224/81 , H01L2224/92247 , H01L2924/00 , H01L2924/01026 , H01L2924/00012
摘要： A method of manufacturing a semiconductor device is described. A board that includes a flat back face, corresponding to a resin sealing area, and a front face that has projections is provided. The projections are formed of a metal that is integral with the board and include (a) a bonding pad provided in an area surrounded by an area that contacts an upper die, (b) a wiring that is integrated with the bonding pad and which extends to a semiconductor element mounting area, and (c) an electrode provided in one body with the wiring. A semiconductor element is mounted on the semiconductor element area and electrically connected to the bonding pad. The board is placed on a lower die and resin is filled into a space formed by the board and upper die. The board is divided into multiple devices such that the projections are separated by removing the board exposed at the back face of the resin.
摘要翻译：对半导体装置的制造方法进行说明。提供了包括对应于树脂密封区域的平坦背面和具有突起的前表面的板。突起由与板成一体的金属形成，并且包括（a）设置在由与上模接触的区域包围的区域中的接合焊盘，（b）与焊盘一体化的布线，并且延伸涉及半导体元件安装区域，以及（c）在一个主体中设置有布线的电极。半导体元件安装在半导体元件区域上并电连接到接合焊盘。将板放在下模上，将树脂填充到由板和上模形成的空间中。板被分成多个装置，使得通过移除在树脂的背面露出的板来分离突起。

37. 发明申请

US20060065421A1 Circuit device and manufacturing method thereof 审中-公开
标题翻译：电路装置及其制造方法
公开(公告)号：US20060065421A1
公开(公告)日：2006-03-30
申请号：US11237856
申请日：2005-09-29
申请人： Kazumasa Arai , Yutaka Kubota , Yusuke Igarashi , Hidefumi Saito , Masami Motegi , Noriaki Sakamoto
发明人： Kazumasa Arai , Yutaka Kubota , Yusuke Igarashi , Hidefumi Saito , Masami Motegi , Noriaki Sakamoto
IPC分类号： H05K5/06
CPC分类号： H01L21/565 , H01L23/293 , H01L23/3121 , H01L23/3135 , H01L23/49531 , H01L24/45 , H01L24/48 , H01L24/97 , H01L2224/451 , H01L2224/48091 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/01322 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3511 , H05K1/0271 , H05K1/056 , H05K3/284 , H05K3/285 , H05K2201/0209 , H05K2201/068 , H05K2203/0315 , H01L2224/85 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： Warping of a hybrid integrated circuit device 10 due to shrinkage on curing of a sealing resin 14 is suppressed. The hybrid integrated circuit device 10 includes: a conductive pattern 13 provided on a surface of a circuit board 11; circuit elements 15 fixed to the conductive pattern 13; thin metal wires 17 electrically connecting the circuit elements 15 to the conductive pattern; leads 16 which are connected to the conductive pattern 13 to become output or input and extended to the outside; and a sealing resin 14 which is made of a thermosetting resin and covers the circuit board 11 by transfer molding while at least a rear surface of the circuit board is exposed. Here, a thermal expansion coefficient of the sealing resin 14 is set to be smaller than a thermal expansion coefficient of the circuit board 11. Thus, warping of the circuit board 11 in an after cure step can be prevented.
摘要翻译：由于密封树脂14的固化收缩而导致混合集成电路装置10的翘曲被抑制。混合集成电路装置10包括：设置在电路板11的表面上的导电图案13; 固定到导电图案13的电路元件15; 将电路元件15电连接到导电图案的细金属线17; 引线16，其连接到导电图案13以输出或输入并延伸到外部; 以及密封树脂14，其由热固性树脂制成，并且在电路板的至少后表面露出时通过传递模塑覆盖电路板11。这里，将密封树脂14的热膨胀系数设定为小于电路基板11的热膨胀系数。因此，可以防止在后固化步骤中的电路板11的翘曲。

38. 发明申请

US20050230801A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050230801A1
公开(公告)日：2005-10-20
申请号：US11049993
申请日：2005-02-04
申请人： Hiroshi Kuroda , Noriaki Sakamoto , Takafumi Kikuchi
发明人： Hiroshi Kuroda , Noriaki Sakamoto , Takafumi Kikuchi
IPC分类号： H01L23/12 , H01L21/48 , H01L23/495 , H01L23/498 , H01L23/538 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L24/06 , H01L23/49816 , H01L23/5386 , H01L24/48 , H01L25/0657 , H01L2223/5442 , H01L2223/54473 , H01L2224/0401 , H01L2224/05554 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/45147 , H01L2224/48227 , H01L2224/73204 , H01L2225/0651 , H01L2225/06517 , H01L2225/06555 , H01L2225/06562 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01055 , H01L2924/01056 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10161 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a semiconductor device including a package board, a first DRAM that is flip-chip connected on the package board, a second DRAM that is of the same type as the first DRAM and is mounted face up on the first DRAM such that the orientation of the arrangement of the pads is at 90° from that of the first DRAM, a microcomputer chip disposed on the second DRAM, wires, and a sealing medium. The package board has a plurality of common wires for electrically connecting first electrodes for the first DRAM and second electrodes for the second DRAM. The common wires can be disposed without crossing on the surface wire layer of the package board, since the orientation of the arrangement of the pads of the second DRAM forms an angle of 90° relative to that of the first DRAM.
摘要翻译：本发明涉及一种包括封装板的半导体器件，在封装板上连接倒装芯片的第一DRAM，与第一DRAM相同类型的第二DRAM，并面向上安装在第一DRAM上，如焊盘的布置方向与第一DRAM的方向成90°，设置在第二DRAM上的微计算机芯片，导线和密封介质。封装板具有用于电连接第一DRAM的第一电极和第二DRAM的第二电极的多条公共电线。由于第二DRAM的焊盘的排列方向相对于第一DRAM的90°的角度形成角度，所以可以将普通的布线布置成不会交叉在封装板的表面布线层上。

39. 发明申请

US20050230796A1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US20050230796A1
公开(公告)日：2005-10-20
申请号：US11105482
申请日：2005-04-14
申请人： Noriaki Sakamoto , Takehisa Yokohama , Tomoru Sato , Takafumi Kikuchi , Fujio Ito
发明人： Noriaki Sakamoto , Takehisa Yokohama , Tomoru Sato , Takafumi Kikuchi , Fujio Ito
IPC分类号： G01R31/28 , G11C29/00 , G11C29/56 , H01L21/822 , H01L23/02 , H01L23/31 , H01L23/495 , H01L23/544 , H01L25/18 , H01L27/04
CPC分类号： H01L24/49 , H01L22/34 , H01L23/3128 , H01L23/49575 , H01L24/32 , H01L24/45 , H01L24/48 , H01L25/18 , H01L2224/05554 , H01L2224/29007 , H01L2224/32014 , H01L2224/32245 , H01L2224/45099 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/4943 , H01L2224/73265 , H01L2224/92247 , H01L2225/06596 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/01055 , H01L2924/01079 , H01L2924/01082 , H01L2924/10161 , H01L2924/10162 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/3011 , H01L2924/00 , H01L2924/3512 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： To provide a test technology capable of reducing a package size by reducing a number of terminals (pins) in a semiconductor integrated circuit of SIP or the like constituted by mounting a plurality of semiconductor chips to a single package, in SIP 102 constituted by mounting a plurality of semiconductor chips to a signal package of ASIC 100, SDRAM 101 and the like, a circuit of testing SDRAM 101 (SDRAMBIST 109) is provided at inside of ASIC 100, and SDRAM 101 is tested from outside of SDRAM 101, that is, from ASIC 100. By providing the test circuit of SDRAM 101 at inside of ASIC 100, it is not necessary to extrude a terminal for testing SDRAM 101 to outside of SIP 102.
摘要翻译：为了提供一种测试技术，能够通过将通过将多个半导体芯片安装到单个封装构成的SIP等的半导体集成电路中的多个端子（引脚）减少到封装尺寸，在通过安装将多个半导体芯片连接到ASIC 100，SDRAM 101等的信号封装，在ASIC 100的内部提供测试SDRAM 101（SDRAMBIST 109）的电路，并且从RAM 101的外部测试SDRAM 101，通过在ASIC100的内部提供SDRAM 101的测试电路，不需要将用于测试SDRAM 101的终端拉伸到SIP 102的外部。

40. 发明申请

US20050230793A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20050230793A1
公开(公告)日：2005-10-20
申请号：US11106678
申请日：2005-04-15
申请人： Fujio Ito , Hiromichi Suzuki , Akihiko Kameoka , Noriaki Sakamoto
发明人： Fujio Ito , Hiromichi Suzuki , Akihiko Kameoka , Noriaki Sakamoto
IPC分类号： H01L21/60 , H01L21/48 , H01L21/607 , H01L23/495 , H01L23/50
CPC分类号： H01L24/85 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/06153 , H01L2224/32245 , H01L2224/45144 , H01L2224/4809 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/48465 , H01L2224/4903 , H01L2224/49051 , H01L2224/4912 , H01L2224/49171 , H01L2224/49175 , H01L2224/4943 , H01L2224/73265 , H01L2224/78743 , H01L2224/85148 , H01L2224/92 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/01055 , H01L2924/01079 , H01L2924/01082 , H01L2924/10162 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/19043 , H01L2924/3011 , H01L2224/78 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device comprises a microcomputer chip, an SDRAM which is disposed alongside the microcomputer chip and is thinner than the microcomputer chip, a tub, a plurality of inner leads and outer leads, first wires that connect pads of the microcomputer chip and pads of the SDRAM, and second wires which connect the pads of the microcomputer chip and the inner leads and which are disposed so as to bridge over the SDRAM and are formed with loops at positions higher than loops of the first wires. An interface circuit for a memory bus is connected only between the chips, without connecting to external terminals, and is closed within a package. Therefore, pins can be utilized for other functions correspondingly and a multi-pin configuration can be achieved. Further, the cost of an SIP (semiconductor device) can be reduced owing to the adoption of a frame type.
摘要翻译：半导体器件包括微计算机芯片，与微计算机芯片一起设置并且比微计算机芯片薄的SDRAM，多个内引线和外引线，连接微计算机芯片的焊盘和第二引线的第一引线 SDRAM和第二线，其连接微型计算机芯片的焊盘和内部引线，并布置成跨越SDRAM并且在高于第一线的环的位置处形成有环。用于存储器总线的接口电路仅在芯片之间连接，而不连接到外部端子，并且在封装内封闭。因此，可以相应地使用引脚用于其他功能，并且可以实现多引脚配置。此外，由于采用帧类型，可以降低SIP（半导体器件）的成本。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式