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31. 发明授权

US4950925A Pre-charge circuit with a bipolar transistor 失效
标题翻译：带双极晶体管的预充电电路
公开(公告)号：US4950925A
公开(公告)日：1990-08-21
申请号：US246196
申请日：1988-09-19
申请人： Toshio Doi , Takehisa Hayashi , Kenichi Ishibashi
发明人： Toshio Doi , Takehisa Hayashi , Kenichi Ishibashi
IPC分类号： H03K17/567 , H03K19/017 , H03K19/08 , H03K19/0944 , H03K19/096
CPC分类号： H03K19/01721 , H03K19/01742 , H03K19/09448
摘要： An output signal of a logic portion is inputted to the gate of FET inside an output buffer portion to inverse the signal polarity by this FET and is outputted through a bipolar transistor effecting an emitter follower operation or the like. An FET controlled by a clock signal is disposed between the base of the bipolar transistor and the ground and an FET which is turned ON during a pre-charge operation and when the bipolar transistor is OFF during logic calculation is disposed between the emitter and the ground so as to short-circuit the emitter and the ground during the pre-charge operation. In this manner, higher operation speed, higher integration density and high operation margin can be accomplished without losing the characteristic features of a Bi-CMOS dynamic logic circuit in its high operation speed and low power dissipation.
摘要翻译：逻辑部分的输出信号被输入到输出缓冲器部分内的FET的栅极，以通过该FET反转信号极性，并通过实现射极跟随器操作等的双极晶体管输出。由时钟信号控制的FET设置在双极晶体管的基极和地之间，在预充电操作期间被接通的FET和在逻辑运算期间当双极晶体管截止时被布置在发射极和地之间以便在预充电操作期间短路发射极和地。以这种方式，可以实现更高的操作速度，更高的集成密度和高的操作裕度，而不会在其高操作速度和低功耗中丧失Bi-CMOS动态逻辑电路的特征。

32. 发明授权

US06728258B1 Multi-processor system and its network 失效
标题翻译：多处理器系统及其网络
公开(公告)号：US06728258B1
公开(公告)日：2004-04-27
申请号：US09456383
申请日：1999-12-08
申请人： Tetsuhiko Okada , Naoki Hamanaka , Naohiko Irie , Takehisa Hayashi , Tetsuya Mochida , Masabumi Shibata , Youichi Tanaka , Yasuhiro Ishii
发明人： Tetsuhiko Okada , Naoki Hamanaka , Naohiko Irie , Takehisa Hayashi , Tetsuya Mochida , Masabumi Shibata , Youichi Tanaka , Yasuhiro Ishii
IPC分类号： H04L1266
CPC分类号： G06F15/17375 , G06F12/0833 , G06F2212/1016 , G06F2212/206
摘要： In a multi-processor system interconnecting processor units, memory units, and input/output units connected to input/output devices via a crossbar switch having a plurality of ports, the transmitter of each processor unit has a circuit for determining a destination of an access request in the following manner. For an access request to a main memory, the access request is transferred to all processor units and one memory unit storing the data to be accessed. For an access request to a memory mapped register of the input/output device, the access request is broadcast to all input/output units. For an access request to a memory mapped register belonging to any one of the processor units, memory units, and input/output units, the access request is broadcast to all units via the crossbar switch.
摘要翻译：在通过具有多个端口的交叉开关连接到处理器单元，存储器单元和连接到输入/输出设备的输入/输出单元的多处理器系统中，每个处理器单元的发射器具有用于确定接入的目的地的电路请求以下列方式。对于对主存储器的访问请求，访问请求被传送到存储要访问的数据的所有处理器单元和一个存储单元。对于对输入/输出设备的存储器映射寄存器的访问请求，将访问请求广播到所有输入/输出单元。对于属于处理器单元，存储器单元和输入/输出单元中的任何一个的存储器映射寄存器的访问请求，访问请求经由交叉开关广播到所有单元。

33. 发明授权

US06519667B2 Bus control system 失效
公开(公告)号：US06519667B2
公开(公告)日：2003-02-11
申请号：US09991925
申请日：2001-11-26
申请人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
发明人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
IPC分类号： G06F1300
CPC分类号： G06F13/4027 , G06F13/36
摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

34. 发明授权

US6011791A Multi-processor system and its network 失效
标题翻译：多处理器系统及其网络
公开(公告)号：US6011791A
公开(公告)日：2000-01-04
申请号：US747344
申请日：1996-11-12
申请人： Tetsuhiko Okada , Naoki Hamanaka , Naohiko Irie , Takehisa Hayashi , Tetsuya Mochida , Masabumi Shibata , Youichi Tanaka , Yasuhiro Ishii
发明人： Tetsuhiko Okada , Naoki Hamanaka , Naohiko Irie , Takehisa Hayashi , Tetsuya Mochida , Masabumi Shibata , Youichi Tanaka , Yasuhiro Ishii
IPC分类号： G06F15/173 , G06F13/38 , H04L12/56
CPC分类号： G06F15/17375
摘要： In a multi-processor system interconnecting processor units, memory units, and input/output units connected to input/output devices via a crossbar switch having a plurality of ports, the transmitter of each processor unit has a circuit for determining a destination of an access request in the following manner. For an access request to a main memory, the access request is transferred to all processor units and one memory unit storing the data to be accessed. For an access request to a memory mapped register of the input/output device, the access request is broadcast to all input/output units. For an access request to a memory mapped register belonging to any one of the processor units, memory units, and input/output units, the access request is broadcast to all units via the crossbar switch.
摘要翻译：在通过具有多个端口的交叉开关连接到处理器单元，存储器单元和连接到输入/输出设备的输入/输出单元的多处理器系统中，每个处理器单元的发射器具有用于确定接入的目的地的电路请求以下列方式。对于对主存储器的访问请求，访问请求被传送到存储要访问的数据的所有处理器单元和一个存储单元。对于对输入/输出设备的存储器映射寄存器的访问请求，将访问请求广播到所有输入/输出单元。对于属于处理器单元，存储器单元和输入/输出单元中的任何一个的存储器映射寄存器的访问请求，访问请求经由交叉开关广播到所有单元。

35. 发明授权

US5794020A Data transfer apparatus fetching reception data at maximum margin of timing 失效
标题翻译：数据传送装置以最大的定时边缘取出接收数据
公开(公告)号：US5794020A
公开(公告)日：1998-08-11
申请号：US663982
申请日：1996-06-14
申请人： Akira Tanaka , Toshio Doi , Kenichi Ishibashi , Takehisa Hayashi , Akira Yamagiwa
发明人： Akira Tanaka , Toshio Doi , Kenichi Ishibashi , Takehisa Hayashi , Akira Yamagiwa
IPC分类号： H04L7/00 , G06F1/12 , H04L7/02 , H04L7/033 , H04L7/08
CPC分类号： H04L7/0337 , H04L7/0008 , H04L7/0041
摘要： A first variable delay circuit delays the reception data from the transmitting unit which is outputted from an input buffer and generates the delayed data to a data unidentifying time detecting portion. First and second latches have latch timings at regular intervals before and after a latch timing of a third latch for receiving and outputting by second and third variable delay circuits, respectively. In an adjusting operation, delay amounts of the second and third variable delay circuits are fixed to a value which is sufficiently smaller than a transfer period, a delay amount of the variable delay circuit is increased, a judging circuit detects a preceding edge of the reception data, subsequently, the delay amounts of the second and third variable delay circuits are sequentially increased while maintaining to the same value, and a following edge of the reception data is detected. In this instance, the timing of the third latch is set to the optimum point of the maximum margin. In a normal operation, the judging circuit detects a deviation from the optimum point and the delay amount of the first variable delay circuit is finely adjusted in accordance with the detection, thereby maintaining the latch timing of the reception data at the optimum point.
摘要翻译：第一可变延迟电路延迟从输入缓冲器输出的发送单元的接收数据，并将延迟的数据生成到数据未识别时间检测部分。第一和第二锁存器分别在第三锁存器的锁存定时之前和之后以规则的间隔分别具有第二和第三可变延迟电路接收和输出的锁存定时。在调整操作中，第二和第三可变延迟电路的延迟量被固定为足够小于传送周期的值，可变延迟电路的延迟量增加，判断电路检测到接收的前一边缘数据，随后，第二和第三可变延迟电路的延迟量依次增加同时保持相同的值，并且检测接收数据的后沿。在这种情况下，第三锁存器的定时被设置为最大裕量的最佳点。在正常操作中，判断电路检测到与最佳点的偏差，并且根据检测精细地调整第一可变延迟电路的延迟量，从而将接收数据的锁存定时保持在最佳点。

36. 发明授权

US5165010A Information processing system 失效
标题翻译：信息处理系统
公开(公告)号：US5165010A
公开(公告)日：1992-11-17
申请号：US461080
申请日：1990-01-04
申请人： Noboru Masuda , Moritoshi Yasunaga , Minoru Yamada , Akira Masaki , Mitsuo Asai , Yuzo Hirai , Masayoshi Yagyu , Takehisa Hayashi , Toshio Doi , Kenichi Ishibashi
发明人： Noboru Masuda , Moritoshi Yasunaga , Minoru Yamada , Akira Masaki , Mitsuo Asai , Yuzo Hirai , Masayoshi Yagyu , Takehisa Hayashi , Toshio Doi , Kenichi Ishibashi
IPC分类号： G06N3/04 , G06N3/063
CPC分类号： G06N3/063 , G06N3/04
摘要： An information processing system includes a plurality of functional blocks (neurons) and a data bus for transmitting in common the outputs of the individual functional blocks (neurons). Data transaction among the functional blocks (neurons) is performed through the data bus on the time-division basis. For preventing the outputs from conflicting or competition, addresses are assigned to the individual blocks (neurons), respectively, so that only the functional blocks (neuron) having the own address designated by the address signal supplied through an address bus outputs data signal onto the data bus, while the other functional blocks (neurons) receive the information on the data bus as the signal originating in the functional block whose address is designated at that time point. The addresses are sequentially changed. During a round of the address signals, data are transmitted from given functional blocks (neurons) to other given functional blocks (neurons).

37. 发明授权

US5132752A Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US5132752A
公开(公告)日：1992-07-21
申请号：US658463
申请日：1991-02-22
申请人： Yasunari Umemoto , Nobuo Kotera , Kiichi Ueyanagi , Norikazu Hashimoto , Nobutoshi Matsunaga , Yasuo Wada , Shoji Shukuri , Noboru Masuda , Takehisa Hayashi , Hirotoshi Tanaka
发明人： Yasunari Umemoto , Nobuo Kotera , Kiichi Ueyanagi , Norikazu Hashimoto , Nobutoshi Matsunaga , Yasuo Wada , Shoji Shukuri , Noboru Masuda , Takehisa Hayashi , Hirotoshi Tanaka
IPC分类号： H01L29/10 , H01L29/812
CPC分类号： H01L29/1075 , H01L29/812 , Y10S257/903
摘要： A field effect transistor formed on a semi-insulator or compound semiconductor substrate comprises a first semiconductor layer forming a source region, a drain region and a channel layer, and a second semiconductor layer having a reverse conduction type to that of the first semiconductor layer. The second semiconductor layer is doped so that it will be totally depleted. Therefore, a portion of the second semiconductor layer adjacent to the substrate will remain conductive. The field effect transistor with this structure prevents the short channel effect and the soft error due to .alpha.-particles. A threshold voltage control arrangement is also provided using the feature of a control electrode coupled to the second semiconductor layer and a feedback arrangement.
摘要翻译：形成在半绝缘体或化合物半导体衬底上的场效应晶体管包括形成源极区，漏极区和沟道层的第一半导体层以及具有与第一半导体层相反的导通型的第二半导体层。第二半导体层被掺杂以使其完全耗尽。因此，与衬底相邻的第二半导体层的一部分将保持导电。具有这种结构的场效应晶体管防止短沟道效应和由于α-粒子引起的软误差。还使用耦合到第二半导体层的控制电极的特征和反馈装置来提供阈值电压控制装置。

38. 发明授权

US5043990A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5043990A
公开(公告)日：1991-08-27
申请号：US279034
申请日：1988-12-02
申请人： Toshio Doi , Takehisa Hayashi , Kenichi Ishibashi
发明人： Toshio Doi , Takehisa Hayashi , Kenichi Ishibashi
IPC分类号： G06F7/00 , G06F11/10 , G06F11/16
CPC分类号： G06F11/1641 , G06F11/10 , G06F7/57
摘要： A semiconductor integrated circuit device is provided which includes a logic circuit utilizing an error detection code. The device has a first circuit train including a series connection of plural stages of operation circuits for receiving input data, performing predetermined operations while the input data propagates through the operation circuits and providing output data; a second circuit train including a series connection of plural stages of error detection code correction circuits for receiving error detection code input corresponding to the input data, applying corrections to the error detection code in correspondence to the operations in the operation circuits in the first circuit train, and outputting an error detection code corresponding to the output data; and at least one error detection circuit for performing a comparison and check of the output of the operation circuit in the first circuit train and the output of a corresponding error detection code correction circuit in the second circuit train. Also, the semiconductor integrated circuit device of this invention comprises a logic circuit incorporating therein an error detection function by doubling the circuits which comprise a logic circuit using the error detection code, doubled operation circuits having the same function and inputted with the same signal, and a comparison circuit for mutually comparing the outputs of the doubled operation circuits.
摘要翻译：提供一种半导体集成电路器件，其包括利用错误检测码的逻辑电路。该装置具有第一电路列，其包括用于接收输入数据的多级操作电路的串联连接，当输入数据通过操作电路传播并提供输出数据时执行预定操作; 包括多级错误检测码校正电路的串联连接的第二电路列，用于接收对应于输入数据的错误检测码输入，对应于第一电路列中的操作电路中的操作对错误检测码进行校正并且输出与所述输出数据相对应的错误检测码; 以及至少一个误差检测电路，用于对第一电路列中的运算电路的输出和第二电路列中相应的检错码校正电路的输出进行比较和检查。此外，本发明的半导体集成电路器件包括一个逻辑电路，其中结合有误差检测功能，通过使用误差检测码将包括逻辑电路的电路加倍，具有相同功能的双倍运算电路并输入相同的信号，以及比较电路，用于相互比较双重运算电路的输出。

39. 发明授权

US4849660A BICMOS output interface circuit for level-shifting ECL to CMOS 失效
标题翻译： BICMOS输出接口电路，用于将ECL电平转换为CMOS
公开(公告)号：US4849660A
公开(公告)日：1989-07-18
申请号：US201961
申请日：1988-06-03
申请人： Takehisa Hayashi , Kenichi Ishibashi , Toshio Doi
发明人： Takehisa Hayashi , Kenichi Ishibashi , Toshio Doi
IPC分类号： H03K19/0175 , H03K19/0944
CPC分类号： H03K19/017518 , H03K19/09448
摘要： An output interface circuit comprises a CMOS circuit including a pair of complementary MOS transistors and receiving an input signal at the gates of the paired MOS transistors, a bipolar transistor having its base connected to the output of the CMOS circuit and its emitter from which an output signal is delivered, and a control circuit connected between the paired MOS transistors and operable, upon the fall of the output signal, to cut off a current flowing through any one of the paired MOS transistors so as to control the low level at the output of the CMOS circuit such that the low level does not fall before a potential level by which the low level of the output signal is permitted to be at a desirable predetermined potential level. Specifically, the CMOS circuit includes a pair of complementary MOS transistors comprised of a P-type MOS transistor and an N-type MOS transistor and receives an input signal of CMOS level to operate in inverter fashion. The bipolar transistor connected to the output of the CMOS circuit operates as an emitter follower to deliver an output signal of ECL level. Upon the fall of the output signal, the control circuit operates to cut off a current flowing through the N-type MOS transistor so as to control the low level at the output of the CMOS circuit such that the low level does not fall below a level which is about 0.5 to 0.8 volts higher than the low level of the output signal (ECL level) of the bipolar transistor.
摘要翻译：输出接口电路包括CMOS电路，其包括一对互补MOS晶体管，并在所述成对MOS晶体管的栅极处接收输入信号;双极晶体管，其基极连接到CMOS电路的输出端及其发射极，信号被输送，以及控制电路，连接在成对的MOS晶体管之间，并且在输出信号的下降时可以切断流过成对的MOS晶体管中的任何一个的电流，以便控制在输出端的低电平 CMOS电路使得低电平不会落在允许输出信号的低电平处于期望的预定电位电平的电位电平之前。具体地说，CMOS电路包括由P型MOS晶体管和N型MOS晶体管组成的一对互补MOS晶体管，并接收CMOS电平的输入信号以逆变器方式工作。连接到CMOS电路的输出的双极晶体管用作射极跟随器来传送ECL电平的输出信号。在输出信号的下降时，控制电路工作以切断流过N型MOS晶体管的电流，以便控制CMOS电路的输出处的低电平，使得低电平不低于电平其比双极晶体管的输出信号（ECL电平）的低电平高约0.5至0.8伏。

40. 发明授权

US4803527A Semiconductor integrated circuit device having semi-insulator substrate 失效
标题翻译：具有半绝缘体衬底的半导体集成电路器件
公开(公告)号：US4803527A
公开(公告)日：1989-02-07
申请号：US876466
申请日：1986-06-20
申请人： Yasushi Hatta , Kazumichi Mitsusada , Hirotoshi Tanaka , Takehisa Hayashi
发明人： Yasushi Hatta , Kazumichi Mitsusada , Hirotoshi Tanaka , Takehisa Hayashi
IPC分类号： H01L29/812 , H01L21/338 , H01L21/8232 , H01L27/02 , H01L27/06 , H01L29/90 , H01L29/78
CPC分类号： H01L27/0605 , H01L27/0251
摘要： Disclosed is a semiconductor integrated circuit device forming MESFETs by use of a semi-insulator GaAs substrate which prevents destruction of an electrostatic destruction protect circuit and a Schottky junction of an internal circuit by causing a part of electrostatic energy, which is applied to external terminals, to flow from a semiconductor region connected to the external terminals into another semiconductor region which is formed in the vicinity of the semiconductor region described above and to which a predetermined fixed potential is applied.
摘要翻译：公开了一种通过使用半绝缘体GaAs衬底形成MESFET的半导体集成电路器件，其通过施加施加到外部端子的一部分静电能来防止静电破坏保护电路和内部电路的肖特基结的破坏，从连接到外部端子的半导体区域流到形成在上述半导体区域附近并且施加预定固定电位的另一个半导体区域。

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