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31. 发明授权

US07605646B2 Low glitch offset correction circuit for auto-zero sensor amplifiers and method 有权
标题翻译：用于自动调零传感器放大器和方法的低毛刺偏移校正电路
公开(公告)号：US07605646B2
公开(公告)日：2009-10-20
申请号：US11890204
申请日：2007-08-03
申请人： Dimitar T. Trifonov , Tony R. Larson , Jerry L. Doorenbos
发明人： Dimitar T. Trifonov , Tony R. Larson , Jerry L. Doorenbos
IPC分类号： H03F1/02
CPC分类号： H03F3/45968 , H03F3/387 , H03F3/45475 , H03F2200/261 , H03F2203/45138 , H03F2203/45212
摘要： An instrumentation amplifier includes first (11A) and second (12A) input amplifiers having outputs (15A,B) coupled to an output amplifier (13). A first auto-zero stage (20) in the first input amplifier is auto-zeroed to a first voltage level (VREFL), a first input signal (Vin+) is amplified by a second auto-zero stage (24) in the first input amplifier, and the amplified first input signal is coupled to the output amplifier, during a first phase (A). A third auto-zero stage (44) in the second input amplifier is auto-zeroed to a second voltage level (VREFH), a second input signal (Vin−) is amplified by a fourth auto-zero stage (40) in the second input amplifier, and the amplified second input signal is coupled to the output amplifier, during a second phase (B). The second auto-zero stage is auto-zeroed to the first voltage level, the first input signal is amplified by the first auto-zero stage (20), and the amplified first input signal is coupled to the output amplifier, during a third phase (C). The fourth auto-zero stage is auto-zeroed to a the second voltage level, the second input signal is amplified by the third auto-zero stage, and the amplified second input signal is coupled to the output amplifier, during a fourth phase (D).
摘要翻译：仪表放大器包括具有耦合到输出放大器（13）的输出（15A，B）的第一（11A）和第二（12A）输入放大器。第一输入放大器中的第一自动归零级（20）被自动归零到第一电压电平（VREFL），第一输入信号（Vin +）被第一输入端的第二自动调零级（24）放大放大器，并且放大的第一输入信号在第一阶段（A）期间耦合到输出放大器。第二输入放大器中的第三自动调零级（44）自动归零至第二电压电平（VREFH），第二输入信号（Vin-）由第二自动调零级（40）放大，第二自动调零级输入放大器，并且放大的第二输入信号在第二阶段（B）期间被耦合到输出放大器。第二自动归零级自动归零到第一电压电平，第一输入信号由第一自动调零级（20）放大，放大的第一输入信号在第三阶段耦合到输出放大器（C）。第四自动调零级自动归零至第二电压电平，第二输入信号由第三自动调零级放大，放大后的第二输入信号在第四阶段（D ）。

32. 发明授权

US07511648B2 Integrating/SAR ADC and method with low integrator swing and low complexity 有权
标题翻译：集成/ SAR ADC和低积分摆幅和低复杂度的方法
公开(公告)号：US07511648B2
公开(公告)日：2009-03-31
申请号：US12072968
申请日：2008-02-29
申请人： Dimitar T. Trifonov , Jerry L. Doorenbos
发明人： Dimitar T. Trifonov , Jerry L. Doorenbos
IPC分类号： H03M3/00
CPC分类号： H03M1/145 , H03M1/46 , H03M3/46
摘要： A reconfigurable circuit (10) includes an integrator (30) having switches (SW1-6) for selectively coupling input capacitors (C0,1,2,3,6,7) and integrating capacitors (C4,5) to terminals of the integrator (30) for operation of a hybrid delta-sigma/SAR ADC (400) so as to create a reference voltage value (Vref) equal to the sum of a first voltage (ΔVbe) and a second voltage (Vbe). A first integration is performed to reduce the integrator output voltage swing. A residue (Vresidue) of the integrator is multiplied by 2. Then the second voltage (Vbe) is integrated in a first direction if a comparator (22) coupled to the integrator changes state or in an opposite direction if the comparator does not change state. The first voltage (ΔVbe) is integrated in a direction that causes the integrator output voltage (Vout) to equal either 2×Vresidue−Vref or 2×Vresidue+Vref.
摘要翻译：可重构电路（10）包括积分器（30），其具有用于选择性地将输入电容器（C0,1,2,3,6,7）和积分电容器（C4,5）耦合到积分器的端子的开关（SW1-6）（30），用于操作混合Δ-Σ/ SAR ADC（400），以便产生等于第一电压（DeltaVbe）和第二电压（Vbe）之和的参考电压值（Vref）。执行第一次积分以减小积分器输出电压摆幅。如果比较器（22）耦合到积分器，则如果比较器不改变状态，则将第二电压（Vbe）积分在第一方向上。如果比较器（22）耦合到积分器，则将积分器的残余（Vresidue）乘以2.然后，。第一电压（DeltaVbe）集成在使积分器输出电压（Vout）等于2xVresidue-Vref或2xVresidue + Vref的方向上。

33. 发明授权

US07501970B2 Digital to analog converter architecture and method having low switch count and small output impedance 有权
标题翻译：具有低开关数和小输出阻抗的数模转换器结构和方法
公开(公告)号：US07501970B2
公开(公告)日：2009-03-10
申请号：US11880568
申请日：2007-07-23
申请人： Dimitar T. Trifonov , Jerry L. Doorenbos
发明人： Dimitar T. Trifonov , Jerry L. Doorenbos
IPC分类号： H03M1/66
CPC分类号： H03M1/682 , H03M1/765 , H03M1/785
摘要： A digital to analog converter includes a coarse resolution resistor circuit (11) coupled between a first voltage (Vin) and an intermediate voltage (V0) to produce coarse resolution node voltages (V0, . . . V240), and also includes a fine resolution resistor circuit (20) coupled between the intermediate voltage and a second voltage (GND). One of the coarse resolution node voltages is selected in response to a group of MSB bits of a digital input (D0,1 . . . ) to produce a first output voltage (Vout2), and one of the fine resolution node voltages is selected in response to group of LSB bits of the digital input to produce a second output voltage (Vout1), the second output voltage (Vout1) and the first output voltage (Vout2) providing a differential analog output signal (Vout1−Vout2). In one embodiment, the coarse resolution and fine resolution resistor circuits are string resistor circuits, and in another embodiment they are modified R-2R networks.
摘要翻译：数模转换器包括耦合在第一电压（Vin）和中间电压（V0）之间以产生粗分辨率节点电压（V0，...，V240）的粗分辨率电阻器电路（11），并且还包括精细分辨率电阻电路（20）耦合在中间电压和第二电压（GND）之间。响应于数字输入（D0,1 ...）的一组MSB位来选择粗分辨率节点电压之一以产生第一输出电压（Vout2），并且选择精细分辨率节点电压中的一个响应于数字输入的一组LSB位以产生第二输出电压（Vout1），第二输出电压（Vout1）和提供差分模拟输出信号（Vout1-Vout2）的第一输出电压（Vout2）。在一个实施例中，粗分辨率和精细分辨率电阻电路是串电阻电路，在另一实施例中，它们是修改的R-2R网络。

34. 发明授权

US07495589B1 Circuit and method for gain error correction in ADC 有权
标题翻译： ADC中增益误差校正的电路和方法
公开(公告)号：US07495589B1
公开(公告)日：2009-02-24
申请号：US11901355
申请日：2007-09-17
申请人： Dimitar T. Trifonov , Jerry L. Doorenbos
发明人： Dimitar T. Trifonov , Jerry L. Doorenbos
IPC分类号： H03M1/06
CPC分类号： H03M1/1019 , H03M1/40 , H03M1/46 , H03M3/382 , H03M3/43 , H03M3/456
摘要： Gain errors are corrected in an ADC chip including an integrator (17), a comparator (30), and a digital filter (37) by storing a gain-adjusted LSB size based on measured gain error in a memory (44). The gain-adjusted LSB size is applied to the digital filter to cause gain-adjusted LSB size values to be added to or subtracted from accumulated content of the digital filter in accordance with a first or second state, respectively, of the comparator (30) during each cycle of the ADC. The final accumulated content after all required cycles of the ADC is a gain-corrected digital output signal (Dout(gain-corrected)).
摘要翻译：通过将经增益调整的LSB大小基于测量的增益误差存储在存储器（44）中，在包括积分器（17），比较器（30）和数字滤波器（37）的ADC芯片中校正增益误差。经增益调整的LSB大小被施加到数字滤波器，以使得根据比较器（30）的第一或第二状态，增加经调整的LSB大小值被添加到数字滤波器的累积内容或从累积内容中减去，在ADC的每个周期。 ADC所需的所有周期之后的最终累加内容是增益校正的数字输出信号（Dout（增益校正））。

35. 发明申请

US20090009239A1 Low glitch offset correction circuit for auto-zero sensor amplifiers and method 有权
公开(公告)号：US20090009239A1
公开(公告)日：2009-01-08
申请号：US11890204
申请日：2007-08-03
申请人： Dimitar T. Trifonov , Tony R. Larson , Jerry L. Doorenbos
发明人： Dimitar T. Trifonov , Tony R. Larson , Jerry L. Doorenbos
IPC分类号： H03F1/02
CPC分类号： H03F3/45968 , H03F3/387 , H03F3/45475 , H03F2200/261 , H03F2203/45138 , H03F2203/45212
摘要： An instrumentation amplifier includes first (11A) and second (12A) input amplifiers having outputs (15A,B) coupled to an output amplifier (13). A first auto-zero stage (20) in the first input amplifier is auto-zeroed to a first voltage level (VREFL), a first input signal (Vin+) is amplified by a second auto-zero stage (24) in the first input amplifier, and the amplified first input signal is coupled to the output amplifier, during a first phase (A). A third auto-zero stage (44) in the second input amplifier is auto-zeroed to a second voltage level (VREFH), a second input signal (Vin−) is amplified by a fourth auto-zero stage (40) in the second input amplifier, and the amplified second input signal is coupled to the output amplifier, during a second phase (B). The second auto-zero stage is auto-zeroed to the first voltage level, the first input signal is amplified by the first auto-zero stage (20), and the amplified first input signal is coupled to the output amplifier, during a third phase (C). The fourth auto-zero stage is auto-zeroed to a the second voltage level, the second input signal is amplified by the third auto-zero stage, and the amplified second input signal is coupled to the output amplifier, during a fourth phase (D).

36. 发明申请

US20080288662A1 Identification address configuration circuit and method without use of dedicated address pins 有权
标题翻译：识别地址配置电路和方法，不使用专用地址引脚
公开(公告)号：US20080288662A1
公开(公告)日：2008-11-20
申请号：US11803465
申请日：2007-05-15
申请人： Jerry L. Doorenbos
发明人： Jerry L. Doorenbos
IPC分类号： G06F3/00 , H01L29/10
CPC分类号： G06F13/385 , G06F13/4291
摘要： An identification address of a sensor interface device is configured in response to the order of connection of first (DXP1) and second (DXN1) package pins to electrodes of a sensor (Q0). A sensor signal processing circuit (23) has first and second inputs coupled through the first and second pins to the sensor for converting a parameter sensed by the sensor to a different representation. A current is forced through the first pin to produce either a high or low voltage on the first pin depending on the order of connection of the first and second pins to the electrodes of the sensor. A voltage on the first pin is compared with a reference voltage to produce a comparison signal which is mapped to produce the identification address.
摘要翻译：响应于第一（DXP1）和第二（DXN1）封装引脚到传感器（Q 0）的电极的连接顺序来配置传感器接口器件的识别地址。传感器信号处理电路（23）具有通过第一和第二引脚耦合到传感器的第一和第二输入，用于将由传感器感测的参数转换成不同的表示。根据第一和第二引脚与传感器的电极的连接顺序，迫使电流通过第一引脚产生第一引脚上的高电压或低电压。将第一引脚上的电压与参考电压进行比较，以产生映射以产生识别地址的比较信号。

37. 发明授权

US06801075B2 Method and circuit for base current compensation 有权
标题翻译：基极电流补偿方法及电路
公开(公告)号：US06801075B2
公开(公告)日：2004-10-05
申请号：US10263262
申请日：2002-10-02
申请人： David A. Gammie , Jeffery B. Parfenchuck , Jerry L. Doorenbos
发明人： David A. Gammie , Jeffery B. Parfenchuck , Jerry L. Doorenbos
IPC分类号： G06G714
CPC分类号： G05F3/265
摘要： A base current compensation circuit is configured for injecting base current to the base of a transistor device to compensate for the lost current demanded by a transistor base. The base current compensation circuit is configured to inject current into the base of the transistor without the headroom requirements, as well as being less complex than other approaches. An exemplary base current compensation circuit comprises a sampling circuit and a current mirror feedback circuit configured for providing multiples of the base current demanded by the transistor device.
摘要翻译：基极电流补偿电路被配置为将基极电流注入到晶体管器件的基极以补偿晶体管基极所需的损耗电流。基极电流补偿电路被配置为将电流注入晶体管的基极，而没有余量要求，并且不如其他方法复杂。示例性基极电流补偿电路包括采样电路和被配置为提供晶体管器件所要求的基极电流倍数的电流镜反馈电路。

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