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31. 发明授权

US06559855B1 Method for transferring image information, method for updating image information, transferring apparatus and updating apparatus 有权
标题翻译：传送图像信息的方法，更新图像信息的方法，传送装置和更新装置
公开(公告)号：US06559855B1
公开(公告)日：2003-05-06
申请号：US09300956
申请日：1999-04-28
申请人： Kei Kawase , Takao Moriyama , Fusashi Nakamura
发明人： Kei Kawase , Takao Moriyama , Fusashi Nakamura
IPC分类号： G09G502
CPC分类号： G09G5/006 , G09G3/3629 , G09G2310/04
摘要： The present invention enables image information of high resolution to be transferred via a transmission line with limited band width using a simple configuration. In transferring image information between a main body of a computer and a display, a dither matrix is used to update images stored in the display. That is, a plurality of blocks whose size is of a predetermined dither matrix are defined in an image, and information of each pixel in each block is transferred to the display in order of a value of a corresponding element in the dither matrix. Transfer of unchanged pixel data can be omitted. In addition, in transferring image information between the main body of the computer and the display, image information stored in the computer is divided into a plurality of blocks, for each of which the number of changed pixels or the number of writings to pixels in the block is calculated so that image information in blocks which exceed a predetermined number is transferred to the display block by block.
摘要翻译：本发明使得能够通过简单的配置通过具有有限带宽的传输线传送高分辨率的图像信息。在计算机主体和显示器之间传送图像信息时，使用抖动矩阵来更新存储在显示器中的图像。也就是说，在图像中定义尺寸为预定的抖动矩阵的多个块，并且按照抖动矩阵中的相应元素的值，按顺序将每个块中的每个像素的信息传送到显示。可以省略未改变的像素数据的传送。此外，在计算机主体和显示器之间传送图像信息时，存储在计算机中的图像信息被划分为多个块，对于每个块，改变的像素的数量或写入的像素的数量计算块，使得超过预定数量的块中的图像信息被块传送到显示块。

32. 发明授权

US5584011A Multiprocessor system with parallel execution of data 失效
标题翻译：具有并行执行数据的多处理器系统
公开(公告)号：US5584011A
公开(公告)日：1996-12-10
申请号：US372614
申请日：1995-01-13
申请人： Kei Kawase , Takao Moriyama
发明人： Kei Kawase , Takao Moriyama
IPC分类号： G06F15/16 , G06F12/08 , G06F12/02 , G06F13/00
CPC分类号： G06F12/0831
摘要： Data sets of sequential data strings at a particular point in time are assigned to processing elements of a multiprocessor system at high speed and processing is executed efficiently in parallel. A mechanism for preventing allocation due to all-read to a cache block which has not yet been referred from another cache is added by providing a reference bit with respect to cache blocks. The reference bit becomes 0 when new data is read to the cache block and becomes 1 when the cache block is referenced by a CPU. In the case of reading data from another cache, if a block corresponding thereto can be replaced without the need to be written back to the other cache and the reference bit is 1, data is fetched to the shared cache memory.
摘要翻译：在特定时间点的顺序数据串的数据集以高速被分配给多处理器系统的处理元件，并行地执行有效的处理。通过提供关于高速缓存块的参考比特来添加用于防止由于全部读取到尚未被从另一个高速缓存引用的高速缓存块的分配的机制。当新数据被读取到高速缓存块时，参考位变为0，当CPU引用高速缓存块时，参考位变为1。在从另一个高速缓存读取数据的情况下，如果与其相对应的块可以被替换而不需要被写回到另一个高速缓存并且参考位为1，则将数据提取到共享高速缓冲存储器。

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