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31. 发明授权

US08753935B1 High frequency switching MOSFETs with low output capacitance using a depletable P-shield 有权
标题翻译：具有低输出电容的高频开关MOSFET，采用可消耗P型屏蔽
公开(公告)号：US08753935B1
公开(公告)日：2014-06-17
申请号：US13724093
申请日：2012-12-21
申请人： Madhur Bobde , Hamza Yilmaz , Sik Lui , Daniel Ng
发明人： Madhur Bobde , Hamza Yilmaz , Sik Lui , Daniel Ng
IPC分类号： H01L21/336 , H01L21/28 , H01L29/40 , H01L29/423
CPC分类号： H01L29/7813 , H01L21/2257 , H01L27/0251 , H01L27/04 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/4238 , H01L29/456 , H01L29/47 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7808 , H01L29/7811
摘要： Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：本公开的方面描述了具有自对准源触点的高密度沟槽基功率MOSFET和用于制造这种器件的方法。源触点与间隔物自对准，并且有源器件可以具有两步栅极氧化物。下部可以具有比栅极氧化物的上部的厚度大的厚度。 MOSFET也可以在衬底的下部包括可消除的屏蔽。可消除的屏蔽可以被配置成使得在高排水偏压期间，屏蔽件基本上消耗掉。要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

32. 发明授权

US08710585B1 High voltage fast recovery trench diode 有权
公开(公告)号：US08710585B1
公开(公告)日：2014-04-29
申请号：US13776497
申请日：2013-02-25
申请人： Jun Hu , Karthik Padmanabhan , Madhur Bobde , Hamza Yilmaz
发明人： Jun Hu , Karthik Padmanabhan , Madhur Bobde , Hamza Yilmaz
IPC分类号： H01L29/66
CPC分类号： H01L29/0615 , H01L21/02104 , H01L29/0692 , H01L29/36 , H01L29/66136 , H01L29/861
摘要： Aspects of the present disclosure describe high voltage fast recovery trench diodes and methods for make the same. The device may have trenches that extend at least through a top P-layer and an N-barrier layer. A conductive material may be disposed in the trenches with a dielectric material lining the trenches between the conductive material and sidewalls of the trenches. A highly doped P-pocket may be formed in an upper portion of the top P-layer between the trenches. A floating N-pocket may be formed directly underneath the P-pocket. The floating N-pocket may be as wide as or wider than the P-pocket. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

33. 发明授权

US10199455B2 Dual-gate trench IGBT with buried floating P-type shield 有权
公开(公告)号：US10199455B2
公开(公告)日：2019-02-05
申请号：US15600782
申请日：2017-05-21
申请人： Jun Hu , Madhur Bobde , Hamza Yilmaz
发明人： Jun Hu , Madhur Bobde , Hamza Yilmaz
IPC分类号： H01L29/739 , H01L29/06 , H01L29/66 , H01L29/423 , H01L29/10 , H01L29/40 , H01L21/265
摘要： A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.

34. 发明申请

US20170271441A1 DUAL-GATE TRENCH IGBT WITH BURIED FLOATING P-TYPE SHIELD 审中-公开
公开(公告)号：US20170271441A1
公开(公告)日：2017-09-21
申请号：US15600782
申请日：2017-05-21
申请人： Jun Hu , Madhur Bobde , Hamza Yilmaz
发明人： Jun Hu , Madhur Bobde , Hamza Yilmaz
IPC分类号： H01L29/06 , H01L29/66 , H01L21/266 , H01L21/265 , H01L29/423 , H01L29/739 , H01L29/40
CPC分类号： H01L29/0623 , H01L21/265 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/42364 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66 , H01L29/66333 , H01L29/66348 , H01L29/7395 , H01L29/7397
摘要： A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.

35. 发明授权

US08878292B2 Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method 有权
标题翻译：自对准开槽积分型场效应晶体管（AccuFET）结构及方法
公开(公告)号：US08878292B2
公开(公告)日：2014-11-04
申请号：US12074280
申请日：2008-03-02
申请人： François Hébert , Madhur Bobde , Anup Bhalla
发明人： François Hébert , Madhur Bobde , Anup Bhalla
IPC分类号： H01L29/739
CPC分类号： H01L29/7828 , H01L29/0619 , H01L29/0623 , H01L29/0847 , H01L29/41766 , H01L29/456 , H01L29/66666
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.
摘要翻译：本发明公开了一种设置在半导体衬底中的半导体功率器件。半导体功率器件包括沟槽栅极，每个沟槽栅极具有在由侧壁间隔物围绕的半导体衬底的顶表面之上延伸的伸出栅极段。半导体功率器件还包括与基本上平行于沟槽栅极的侧壁间隔开的开口的槽。粘贴门区段还包括由侧壁间隔物围绕的绝缘材料构成的盖。阻挡金属层覆盖盖的顶表面并且覆盖在侧壁间隔物上并在槽的顶表面上方延伸。这些槽填充有与栅极段相同的栅极材料，用作附加栅电极，用于提供向沟槽栅极延伸的耗尽层，借此栅极与沟槽栅极之间的漂移区域完全耗尽栅极 - 漏极电压Vgs = 0伏。

36. 发明授权

US08803251B2 Termination of high voltage (HV) devices with new configurations and methods 有权
标题翻译：用新的配置和方法终止高压（HV）设备
公开(公告)号：US08803251B2
公开(公告)日：2014-08-12
申请号：US13135982
申请日：2011-07-19
申请人： Yeeheng Lee , Madhur Bobde , Yongping Ding , Jongoh Kim , Anup Bhalla
发明人： Yeeheng Lee , Madhur Bobde , Yongping Ding , Jongoh Kim , Anup Bhalla
IPC分类号： H01L29/06 , H01L21/76
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0623 , H01L29/0649 , H01L29/407 , H01L29/66734 , H01L29/7813
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.
摘要翻译：本发明公开了一种设置在半导体衬底中的半导体功率器件，包括形成在轻掺杂区域上并具有有源电池区域和边缘端接区域的重掺杂区域。边缘终止区域包括形成在重掺杂区域中的多个端接沟槽，其中端接沟槽衬有介电层并在其中填充有导电材料。边缘终端还包括多个掩埋保护环，其形成为紧邻端接沟槽的半导体衬底的轻掺杂区域中的掺杂区域。

37. 发明授权

US08441046B2 Topside structures for an insulated gate bipolar transistor (IGBT) device to achieve improved device performances 有权
标题翻译：用于绝缘栅双极晶体管（IGBT）器件的顶部结构，以实现改进的器件性能
公开(公告)号：US08441046B2
公开(公告)日：2013-05-14
申请号：US12925869
申请日：2010-10-31
申请人： Madhur Bobde , Anup Bhalla
发明人： Madhur Bobde , Anup Bhalla
IPC分类号： H01L29/66
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/402 , H01L29/66348
摘要： This invention discloses an insulated gate bipolar transistor (IGBT) device formed in a semiconductor substrate. The IGBT device has a split-shielded trench gate that includes an upper gate segment and a lower shield segment. The IGBT device may further include a dummy trench filled with a dielectric layer disposed at a distance away from the split-shielded trench gate. The IGBT device further includes a body region extended between the split-shielded trench gate and the dummy trench encompassing a source region surrounding the split-shielded trench gate near a top surface of the semiconductor substrate. The IGBT device further includes a heavily doped N region disposed below the body region and above a source-dopant drift region above a bottom body-dopant collector region at a bottom surface of the semiconductor substrate. In an alternative embodiment, the IGBT may include a planar gate with a trench shield electrode.
摘要翻译：本发明公开了一种形成在半导体衬底中的绝缘栅双极晶体管（IGBT）器件。 IGBT器件具有分裂屏蔽沟槽栅极，其包括上栅极段和下屏蔽段。 IGBT器件还可以包括填充有离开分屏蔽沟槽栅极一定距离设置的电介质层的虚拟沟槽。 IGBT器件还包括在分屏蔽沟槽栅极和虚拟沟槽之间延伸的体区，其围绕半导体衬底的顶表面附近的分离屏蔽沟槽栅极的源极区域。所述IGBT器件还包括设置在所述体区域的下方且位于所述半导体衬底的底表面的底体 - 掺杂剂集电极区域上方的源 - 掺杂剂漂移区上方的重掺杂N区域。在替代实施例中，IGBT可以包括具有沟槽屏蔽电极的平面栅极。

38. 发明申请

US20130001695A1 UNI-DIRECTIONAL TRANSIENT VOLTAGE SUPPRESSOR (TVS) 有权
标题翻译：单向瞬态电压抑制器（TVS）
公开(公告)号：US20130001695A1
公开(公告)日：2013-01-03
申请号：US13171037
申请日：2011-06-28
申请人： Lingpeng Guan , Madhur Bobde , Anup Bhalla
发明人： Lingpeng Guan , Madhur Bobde , Anup Bhalla
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/0262 , H01L21/8222 , H01L27/0255 , H01L27/0259 , H01L27/0814 , H01L27/082
摘要： An epitaxial layer is supported on top of a substrate. First and second body regions are formed within the epitaxial layer separated by a predetermined lateral distance. Trigger and source regions are formed within the epitaxial layer. A first source region is transversely adjacent the first body region between first and second trigger regions laterally adjacent the first source region and transversely adjacent the first body region. A second source region is located transversely adjacent the second body region between third and fourth trigger regions laterally adjacent the second source region and transversely adjacent the second body region. A third source region is laterally adjacent the fourth trigger region. The fourth trigger region is between the second and third source regions. An implant region within the fourth trigger region is laterally adjacent the third source region.
摘要翻译：外延层支撑在基板的顶部。第一和第二体区域形成在外延层中以预定的横向距离分开。在外延层内形成触发源区和源极区。第一源区域横向地邻近第一和第二触发区域之间的与第一源区域相邻并且横向邻近第一体区域的第一体区域相邻。第二源区域横向地邻近第二和第四触发区域之间的第二体区横向邻近第二源区域并且横向邻近第二体区域定位。第三源区域与第四触发区域横向相邻。第四触发区域在第二和第三源区之间。第四触发区域内的植入区域与第三源区域横向相邻。

39. 发明申请

US20140264433A1 DUAL-GATE TRENCH IGBT WITH BURIED FLOATING P-TYPE SHIELD 有权
标题翻译：双栅双极型IGBT，带有浮动P型屏蔽
公开(公告)号：US20140264433A1
公开(公告)日：2014-09-18
申请号：US13831066
申请日：2013-03-14
申请人： Jun Hu , Madhur Bobde , Hamza Yilmaz
发明人： Jun Hu , Madhur Bobde , Hamza Yilmaz
IPC分类号： H01L29/739 , H01L29/66
CPC分类号： H01L29/7395 , H01L29/0623 , H01L29/0696 , H01L29/407 , H01L29/42368 , H01L29/4238 , H01L29/66333
摘要： A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.
摘要翻译：一种制造绝缘栅双极晶体管（IGBT）器件的方法，包括：1）制备具有第一导电类型的外延层的半导体衬底，该半导体衬底支撑在第二导电类型的半导体衬底上; 2）施加栅极沟槽掩模以打开第一沟槽和第二沟槽，随后形成栅极绝缘层以衬垫沟槽并用多晶硅层填充沟槽以形成第一沟槽栅极和第二沟槽栅极; 3）注入第一导电类型的掺杂剂以在外延层中形成上重掺杂区; 以及4）在所述第一沟槽栅极的顶部上形成平面栅极，并且将注入掩模施加到植入物体掺杂剂和源掺杂剂以在所述半导体衬底的顶表面附近形成体区域和源极区域。

40. 发明申请

US20140175540A1 HIGH FREQUENCY SWITCHING MOSFETS WITH LOW OUTPUT CAPACITANCE USING A DEPLETABLE P-SHIELD 有权
标题翻译：具有低输出电容的高频开关MOSFET使用可折叠P型屏蔽
公开(公告)号：US20140175540A1
公开(公告)日：2014-06-26
申请号：US13724093
申请日：2012-12-21
申请人： Madhur Bobde , Hamza Yilmaz , Sik Lui , Daniel Ng
发明人： Madhur Bobde , Hamza Yilmaz , Sik Lui , Daniel Ng
IPC分类号： H01L27/04 , H01L21/82
CPC分类号： H01L29/7813 , H01L21/2257 , H01L27/0251 , H01L27/04 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/4238 , H01L29/456 , H01L29/47 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7808 , H01L29/7811
摘要： Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：本公开的方面描述了具有自对准源触点的高密度沟槽基功率MOSFET和用于制造这种器件的方法。源触点与间隔物自对准，并且有源器件可以具有两步栅极氧化物。下部可以具有比栅极氧化物的上部的厚度大的厚度。 MOSFET也可以在衬底的下部包括可消除的屏蔽。可消除的屏蔽可以被配置成使得在高排水偏压期间，屏蔽件基本上消耗掉。要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

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