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31. 发明授权

US07338865B2 Method for manufacturing dual work function gate electrodes through local thickness-limited silicidation 有权
标题翻译：通过局部厚度限制硅化物制造双功能功能栅电极的方法
公开(公告)号：US07338865B2
公开(公告)日：2008-03-04
申请号：US10897846
申请日：2004-07-23
申请人： Robert W. Murto , Luigi Colombo , Mark R. Visokay
发明人： Robert W. Murto , Luigi Colombo , Mark R. Visokay
IPC分类号： H01L21/8234
CPC分类号： H01L21/823835 , H01L21/823842
摘要： The present invention provides a method of manufacturing a semiconductor device. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first transistor (120) has a gate electrode (135) that includes a metal silicide layer 135a over which is located a silicon gate layer (135b) together which have a work function associated therewith, and a second transistor (125) located over the semiconductor substrate (110) and proximate the first transistor (120), wherein the second transistor (125) also includes a gate electrode (160) that includes a metal silicide layer (160a) over which is located a silicon gate layer (160b) together which have a different work function from that of the first gate electrode (135) associated therewith.
摘要翻译：本发明提供一种制造半导体器件的方法。除了其它可能的元件之外，半导体器件（100）包括位于半导体衬底（110）上方的第一晶体管（120），其中第一晶体管（120）具有包括金属硅化物层135a的栅电极（135）位于硅栅极层（135b）上，其具有与其相关联的功函数;以及第二晶体管（125），位于半导体衬底（110）之上并且靠近第一晶体管（120），其中第二晶体管 125）还包括栅电极（160），其包括金属硅化物层（160a），栅极电极（160a）位于硅栅极层（160b）上，其具有与第一栅电极（135）的功函数不同的功函随之而来。

32. 发明授权

US07233035B2 Dual work function gate electrodes using doped polysilicon and a metal silicon germanium compound 有权
标题翻译：使用掺杂多晶硅和金属硅锗化合物的双功函数栅电极
公开(公告)号：US07233035B2
公开(公告)日：2007-06-19
申请号：US11463128
申请日：2006-08-08
申请人： Antonio L. P. Rotondaro , Mark R. Visokay , Luigi Colombo
发明人： Antonio L. P. Rotondaro , Mark R. Visokay , Luigi Colombo
IPC分类号： H01L29/80 , H01L21/336
CPC分类号： H01L21/28097 , H01L21/823842 , H01L29/4975
摘要： A dielectric layer (50) is formed over a semiconductor (10) that contains a first region (20) and a second region (30). A polysilicon layer is formed over the dielectric layer (50) and over the first region (20) and the second region (30). The polysilicon layer can comprise 0 to 50 atomic percent of germanium. A metal layer is formed over the polysilicon layer and one of the regions and reacted with the underlying polysilicon layer to form a metal silicide or a metal germano silicide. The polysilicon and metal silicide or germano silicide regions are etched to form transistor gate regions (60) and (90) respectively. If desired a cladding layer (100) can be formed above the metal gate structures.
摘要翻译：在包含第一区域（20）和第二区域（30）的半导体（10）上形成介电层（50）。在电介质层（50）上并在第一区域（20）和第二区域（30）之上形成多晶硅层。多晶硅层可以包含0至50原子％的锗。在多晶硅层和其中一个区域上形成金属层，并与下面的多晶硅层反应形成金属硅化物或金属锗化硅。蚀刻多晶硅和金属硅化物或锗硅化物区域以分别形成晶体管栅极区域（60）和（90）。如果需要，可以在金属栅极结构上方形成包覆层（100）。

33. 发明授权

US07018902B2 Gate dielectric and method 有权
公开(公告)号：US07018902B2
公开(公告)日：2006-03-28
申请号：US10165888
申请日：2002-06-10
申请人： Mark R. Visokay , Antonio L. P. Rotondaro , Luigi Colombo
发明人： Mark R. Visokay , Antonio L. P. Rotondaro , Luigi Colombo
IPC分类号： H01L21/00
CPC分类号： H01L21/823857 , H01L21/823842
摘要： A MOSFET structure with high-k gate dielectric layer and silicon or metal gates, amorphizing treatment of the high-k gate dielectric layer as with a plasma or ion implantation.

34. 发明授权

US06821873B2 Anneal sequence for high-&kgr; film property optimization 有权
标题翻译：用于高Kappa膜性质优化的退火序列
公开(公告)号：US06821873B2
公开(公告)日：2004-11-23
申请号：US10185326
申请日：2002-06-28
申请人： Mark R. Visokay , Luigi Colombo , Antonio L. P. Rotondaro
发明人： Mark R. Visokay , Luigi Colombo , Antonio L. P. Rotondaro
IPC分类号： H01L213105
CPC分类号： H01L21/02323 , H01L21/02142 , H01L21/02175 , H01L21/02337 , H01L21/02348 , H01L21/28185 , H01L21/28194 , H01L21/31691 , H01L21/324 , H01L29/517 , H01L29/518
摘要： A method for improving high-&kgr; gate dielectric film (104) properties. The high-&kgr; film (104) is subjected to a two step anneal sequence. The first anneal is a high temperature anneal in a non-oxidizing ambient (106) such as N2 to densify the high-&kgr; film (104). The second anneal is a lower temperature anneal in an oxidizing ambient (108) to perform a mild oxidation that heals the high-&kgr; film and reduces interface defects.
摘要翻译：一种改善高卡门电介质膜（104）性能的方法。对高卡帕膜（104）进行两步退火处理。第一退火是在非氧化性环境（106）如N 2中的高温退火以致密化高卡帕膜（104）。第二退火是在氧化环境（108）中的较低温度退火，以进行温和氧化，以愈合高κ薄膜并减少界面缺陷。

35. 发明申请

US20090227117A1 GATE STRUCTURE AND METHOD 有权
标题翻译：门结构和方法
公开(公告)号：US20090227117A1
公开(公告)日：2009-09-10
申请号：US12421036
申请日：2009-04-09
申请人： Antonio L.P. Rotondaro , Luigi Colombo , Mark R. Visokay , Rajesh Khamankar , Douglas E. Mercer
发明人： Antonio L.P. Rotondaro , Luigi Colombo , Mark R. Visokay , Rajesh Khamankar , Douglas E. Mercer
IPC分类号： H01L21/31
CPC分类号： H01L21/28194 , H01L21/28202 , H01L21/823857 , H01L21/823871 , H01L27/092 , H01L29/517 , H01L29/518
摘要： A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition.
摘要翻译：一种MOSFET结构，包括在栅极材料沉积之前具有栅极电介质的氮化处理的硅酸盐栅极电介质。

36. 发明授权

US07183221B2 Method of fabricating a semiconductor having dual gate electrodes using a composition-altered metal layer 有权
标题翻译：使用组成改变的金属层制造具有双栅电极的半导体的方法
公开(公告)号：US07183221B2
公开(公告)日：2007-02-27
申请号：US10703388
申请日：2003-11-06
申请人： Mark R. Visokay , Luigi Colombo
发明人： Mark R. Visokay , Luigi Colombo
IPC分类号： H01L21/302
CPC分类号： H01L21/823842
摘要： Fabricating a semiconductor includes depositing a metal layer outwardly from a dielectric layer and forming a mask layer outwardly from a first portion of the metal layer. Atoms are incorporated into an exposed second portion of the metal layer to form a composition-altered portion of the metal layer. The mask layer is removed from the first portion of the metal layer and a barrier layer is deposited outwardly from the metal layer. A poly-Si layer is deposited outwardly from the barrier layer to form a semiconductor layer, where the barrier layer substantially prevents reaction of the metal layer with the poly-Si layer. The semiconductor layer is etched to form gate stacks, where each gate stack operates according to one of a plurality of work functions.
摘要翻译：制造半导体包括从电介质层向外沉积金属层并从金属层的第一部分向外形成掩模层。将原子并入金属层的暴露的第二部分中以形成金属层的组合物改变部分。掩模层从金属层的第一部分去除，并且阻挡层从金属层向外沉积。多晶硅层从阻挡层向外沉积形成半导体层，其中阻挡层基本上防止了金属层与多晶硅层的反应。蚀刻半导体层以形成栅极堆叠，其中每个栅极堆叠根据多个功函数中的一个工作。

37. 发明授权

US06783997B2 Gate structure and method 有权
标题翻译：门结构和方法
公开(公告)号：US06783997B2
公开(公告)日：2004-08-31
申请号：US10325371
申请日：2002-12-19
申请人： Antonio L. P. Rotondaro , Mark R. Visokay , Luigi Colombo
发明人： Antonio L. P. Rotondaro , Mark R. Visokay , Luigi Colombo
IPC分类号： H01L2100
CPC分类号： H01L22/20 , H01L21/28194 , H01L21/28202 , H01L21/3143 , H01L21/31604 , H01L21/823857 , H01L29/42376 , H01L29/517 , H01L29/518 , H01L29/66545
摘要： MOSFET fabrication methods with high-k gate dielectrics for silicon or metal gates with gate dielectric deposition control including TXRF. TXRF permits analysis of gate (or capacitor) high-k dielectrics down to about 5 nm thickness.
摘要翻译：具有用于硅或具有栅介质沉积控制（包括TXRF）的硅或金属栅极的高k栅极电介质的MOSFET制造方法。 TXRF允许将栅极（或电容器）高k电介质的厚度分析到约5nm。

38. 发明授权

US06600183B1 Integrated circuit capacitor and memory 失效
标题翻译：集成电路电容和存储器
公开(公告)号：US06600183B1
公开(公告)日：2003-07-29
申请号：US09105830
申请日：1998-06-26
申请人： Mark R. Visokay , Luigi Colombo , Rajesh Khamankar , Mark A. Kressley
发明人： Mark R. Visokay , Luigi Colombo , Rajesh Khamankar , Mark A. Kressley
IPC分类号： H01L2976
CPC分类号： H01L21/7685 , H01L21/32136 , H01L21/32139 , H01L21/76802 , H01L21/7687 , H01L21/76889 , H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/75
摘要： An electrode structure for a capacitor. The electrode structure includes a contact plug comprising an oxidation barrier 208 and a bottom electrode comprising a conductive adhesion-promoting portion 210 and an oxidation-resistant portion 204, the adhesion-promoting portion contacting the oxidation barrier of the contact plug. In further embodiments, the oxidation barrier and adhesion-promoting portion comprise Ti—Al—N.
摘要翻译：电容器的电极结构。电极结构包括接触塞，其包括氧化屏障208和包括导电粘附促进部分210和抗氧化部分204的底部电极，所述粘合促进部分接触接触插塞的氧化屏障。在另外的实施方案中，氧化屏障和增粘部分包括Ti-Al-N。

39. 发明授权

US06544906B2 Annealing of high-k dielectric materials 有权
标题翻译：高k电介质材料的退火
公开(公告)号：US06544906B2
公开(公告)日：2003-04-08
申请号：US10011219
申请日：2001-10-25
申请人： Antonio L. P. Rotondaro , Mark R. Visokay , Luigi Colombo
发明人： Antonio L. P. Rotondaro , Mark R. Visokay , Luigi Colombo
IPC分类号： H01L21469
CPC分类号： H01L21/02323 , H01L21/02148 , H01L21/02156 , H01L21/02159 , H01L21/02178 , H01L21/02181 , H01L21/02183 , H01L21/02189 , H01L21/02192 , H01L21/02194 , H01L21/02337 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/3144 , H01L21/3165 , H01L21/318 , H01L29/517 , H01L29/518
摘要： A method for annealing a high dielectric constant (high-k) gate dielectric layer includes placing a wafer including one or more partially formed transistors in an ambient. The ambient may include hydrogen and an oxidizing gas or the ambient may include nitrous oxide. Each transistor includes a high-k gate dielectric layer coupled to a substrate. The method further includes heating the high-k gate dielectric layer to a temperature greater than 650° C. while the gate dielectric layer is in the ambient. The ambient prevents or reduces the formation of lower dielectric constant (lower-k) material between the high-k gate dielectric layer and the substrate. Another method for annealing a high-k gate dielectric layer includes the use of an ambient including chemically active oxygen gas. When such an ambient is used, the high-k gate dielectric layer is heated to a temperature not greater than 600° C. while the gate dielectric layer is in the ambient.
摘要翻译：用于退火高介电常数（高k）栅介质层的方法包括将包括一个或多个部分形成的晶体管的晶片放置在环境中。环境可以包括氢气和氧化气体，或者环境可以包括一氧化二氮。每个晶体管包括耦合到衬底的高k栅介质层。该方法还包括在栅介质层处于环境中时将高k栅介质层加热到大于650℃的温度。环境防止或减少在高k栅极电介质层和衬底之间的较低介电常数（低k）材料的形成。用于退火高k栅介质层的另一种方法包括使用包括化学活性氧气的环境。当使用这样的环境时，高k栅极电介质层被加热到不高于600℃的温度，同时栅介质层处于环境中。

40. 发明授权

US07799668B2 Formation of uniform silicate gate dielectrics 有权
标题翻译：均匀硅酸盐栅极电介质的形成
公开(公告)号：US07799668B2
公开(公告)日：2010-09-21
申请号：US11205477
申请日：2005-08-17
申请人： Hiroaki Niimi , Luigi Colombo , James J. Chambers
发明人： Hiroaki Niimi , Luigi Colombo , James J. Chambers
IPC分类号： H01L21/3205
CPC分类号： H01L21/823462 , H01L21/28185 , H01L21/28229 , H01L21/31645 , H01L21/823857 , H01L21/8249 , H01L29/517
摘要： The present invention provides method of forming a gate dielectric that includes forming a metal source layer (210) comprising a metal and at least one nonmetallic element over a substrate (110). The metal source layer (210) is formed having a composition rich in the metal. A dielectric layer (310) comprising the metal is formed over the metal source layer (210).
摘要翻译：本发明提供了形成栅极电介质的方法，其包括在衬底（110）上形成包括金属和至少一种非金属元素的金属源层（210）。金属源层（210）形成为具有富含金属的组成。在金属源层（210）之上形成包括金属的电介质层（310）。

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