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31. 发明授权

US10095636B2 Secure computing 有权
公开(公告)号：US10095636B2
公开(公告)日：2018-10-09
申请号：US15824395
申请日：2017-11-28
申请人： Laurence H. Cooke
发明人： Laurence H. Cooke
IPC分类号： G06F21/00 , G06F12/14 , G06F12/0875 , G06F12/0811 , G06F9/30 , G06F21/52 , G06F21/75 , G06F21/85 , G06F11/30
摘要： Techniques and logic are presented for encrypting and decrypting applications and related data within a multi-processor system to prevent tampering. The decryption and encryption may be performed either between a system bus and a processor's individual L1 cache memory or between a processor's instruction and execution unit and their respective L1 caches. The logic may include one or more linear feedback shift registers (LFSRs) that may be used for generation of unique sequential address related codes to perform the decryption of instructions and transformation logic that may be used for generation of equivalent offset address related codes to perform decryption and encryption of data. The logic may also be programmable and may be used for test purposes.

32. 发明授权

US08928387B2 Tunable clock distribution system 有权
标题翻译：可调时钟分配系统
公开(公告)号：US08928387B2
公开(公告)日：2015-01-06
申请号：US13891328
申请日：2013-05-10
申请人： Laurence H. Cooke
发明人： Laurence H. Cooke
IPC分类号： H03K3/00 , H03K5/15
CPC分类号： H03K5/15 , H03K5/131 , H03K5/133 , H03K5/15013 , H03K2005/00065 , H03K2005/00247
摘要： A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-flop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented.
摘要翻译：由可变电阻器元件组成的存储器状结构，用于调整时钟分配结构的相应分支和叶片，其可用于补偿逐芯片和/或组合逻辑逐个路径延迟变化，其中可能是因为例如深亚微米器件和互连中的物理变化。还提供了具有执行延迟测试测量功能的单个系统时钟扫描触发器。还提出了用于测量组合逻辑路径延迟以确定最大时钟频率和编程可变电阻器的延迟的方法，以及用于校准和测量编程的可变电阻器的方法。

33. 发明申请

US20150001577A1 DESIGN AND MANUFACTURE OF A TUNNEL DIODE MEMORY 审中-公开
标题翻译：隧道二极管存储器的设计与制造
公开(公告)号：US20150001577A1
公开(公告)日：2015-01-01
申请号：US13927835
申请日：2013-06-26
申请人： Laurence H. Cooke
发明人： Laurence H. Cooke
IPC分类号： H01L29/66 , H01L49/02 , H01L21/02 , H01L27/10
CPC分类号： G11C11/419 , G11C11/418 , H01L27/0207 , H01L27/0676 , H01L27/1021 , H01L28/40 , H01L29/66151
摘要： A design of a non-transistor memory core with corresponding shift register control logic may be all comprised of tunnel diodes and capacitors, and a method for fabricating such memories and control logic may use a stencil and non-lithographic self-aligning semiconductor processing steps to minimize cost. Designs and fabrication processes for I/O pads connected to the memory core and control logic are also presented.
摘要翻译：具有相应的移位寄存器控制逻辑的非晶体管存储器核心的设计可以全部由隧道二极管和电容器组成，并且用于制造这种存储器和控制逻辑的方法可以使用模板和非光刻自对准半导体处理步骤最小化成本。还介绍了连接到存储器核心和控制逻辑的I / O焊盘的设计和制造工艺。

34. 发明申请

US20140333364A1 TUNABLE CLOCK DISTRIBUTION SYSTEM 有权
标题翻译：时钟分配系统
公开(公告)号：US20140333364A1
公开(公告)日：2014-11-13
申请号：US13891328
申请日：2013-05-10
申请人： Laurence H. Cooke
发明人： Laurence H. Cooke
IPC分类号： H03K5/15
CPC分类号： H03K5/15 , H03K5/131 , H03K5/133 , H03K5/15013 , H03K2005/00065 , H03K2005/00247
摘要： A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-flop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented.
摘要翻译：由可变电阻器元件组成的存储器状结构，用于调整时钟分配结构的相应分支和叶片，其可用于补偿逐芯片和/或组合逻辑逐个路径延迟变化，其中可能是因为例如深亚微米器件和互连中的物理变化。还提供了具有执行延迟测试测量功能的单个系统时钟扫描触发器。还提出了用于测量组合逻辑路径延迟以确定最大时钟频率和编程可变电阻器的延迟的方法，以及用于校准和测量编程的可变电阻器的方法。

35. 发明授权

US08743578B2 Use of hydrocarbon nanorings for data storage 有权
标题翻译：使用碳氢化合物纳米数据进行数据存储
公开(公告)号：US08743578B2
公开(公告)日：2014-06-03
申请号：US13559842
申请日：2012-07-27
申请人： Laurence H. Cooke
发明人： Laurence H. Cooke
IPC分类号： G11C19/08 , H01F10/24 , H01L51/00 , H01L51/05
CPC分类号： H01F10/24 , G11C11/14 , H01L51/0048 , H01L51/0508
摘要： Hydro-carbon nanorings may be used in storage. Sufficiently cooled, an externally hydrogen doped carbon nanoring may be used to create a radial dipole field to contain streams of electrons. Similarly, an internally hydrogen doped carbon nanoring may be used to create a radial dipole field to contain streams of positrons. When matched streams of positrons and electrons are sufficiently compressed they may form Cooper pairs with magnetic moments aligned to the movement of the stream. Matched adjacent Cooper pairs of electrons and positrons may contain information within their magnetic moments, and as such, may transmit and store information with little or no energy loss.
摘要翻译：水碳纳米管可用于储存。足够冷却，可以使用外部氢掺杂的碳纳米来产生径向偶极场以包含电子流。类似地，内部氢掺杂的碳纳米可用于产生径向偶极场以包含正电子流。当正电子和电子的匹配流被充分压缩时，它们可以形成具有与流的运动对准的磁矩的Cooper对。匹配的Cooper对电子和正电子可能包含其磁矩内的信息，因此，可以很少或没有能量损失传输和存储信息。

36. 发明申请

US20140115423A1 NON-VOLATILE MEMORY ERROR CORRECTION 审中-公开
公开(公告)号：US20140115423A1
公开(公告)日：2014-04-24
申请号：US13667298
申请日：2012-11-02
申请人： Laurence H. Cooke
发明人： Laurence H. Cooke
IPC分类号： H03M13/05 , G06F11/08
CPC分类号： H03M13/2909 , G06F11/1012 , H03M13/09 , H03M13/11 , H03M13/15 , H03M13/151 , H03M13/2927
摘要： Improving the performance, life and amount of data storage in write limited non-volatile memory may be achieved by: a) utilizing a serial content-addressable memory (CAM) to perform logical address translation, b) a minimum CAM function to perform erase error count wear leveling, c) increasingly refining a two dimensional error-correction coding (ECC) method as needed to correct for degrading storage, and/or d) serially generating ECC and using an ECC serial decoder to correct the data.

37. 发明授权

US08656143B2 Variable clocked heterogeneous serial array processor 有权
标题翻译：可变时钟异构串行数组处理器
公开(公告)号：US08656143B2
公开(公告)日：2014-02-18
申请号：US12699548
申请日：2010-02-03
申请人： Laurence H. Cooke
发明人： Laurence H. Cooke
IPC分类号： G06F9/22
CPC分类号： G06F1/12 , G06F1/06 , G06F9/30014 , G06F9/30032 , G06F15/7867 , G06F15/8015 , G11C11/405
摘要： A serial array processor may have an execution unit, which is comprised of a multiplicity of single bit arithmetic logic units (ALUs), and which may perform parallel operations on a subset of all the words in memory by serially accessing and processing them, one bit at a time, while an instruction unit of the processor is pre-fetching the next instruction, a word at a time, in a manner orthogonal to the execution unit.
摘要翻译：串行阵列处理器可以具有执行单元，其由多个单位算术逻辑单元（ALU）组成，并且可以通过串行访问和处理存储器中的所有字的子集来执行并行操作，一位同时处理器的指令单元以与执行单元正交的方式一次预取下一个指令，一个字。

38. 发明申请

US20130159618A1 NEAREST NEIGHBOR SERIAL CONTENT ADDRESSABLE MEMORY 审中-公开
公开(公告)号：US20130159618A1
公开(公告)日：2013-06-20
申请号：US13765976
申请日：2013-02-13
申请人： Laurence H. Cooke
发明人： Laurence H. Cooke
IPC分类号： G06F17/30
CPC分类号： G06F17/30982 , G06K9/00986 , G06K9/6215 , G06K9/6276 , G11C15/04
摘要： A digital design and technique may be used to implement a Manhattan Nearest Neighbor content addressable memory function by augmenting a serial content addressable memory design with additional memory and counters for bit serially accumulating in parallel and subsequently comparing in parallel all the Manhattan distances between a serially inputted vector and all corresponding vectors resident in the CAM. Other distance measures, besides a Manhattan distance, may optionally be used in conjunction with similar techniques and designs.

39. 发明授权

US07890899B2 Variable clocked scan test improvements 有权
标题翻译：可变时钟扫描测试改进
公开(公告)号：US07890899B2
公开(公告)日：2011-02-15
申请号：US12046336
申请日：2008-03-11
申请人： Laurence H. Cooke , Bulent I. Dervisoglu
发明人： Laurence H. Cooke , Bulent I. Dervisoglu
IPC分类号： G06F17/50
CPC分类号： G01R31/318552
摘要： Addition of specific test logic may improve the level of test vector compression achieved from existing variable scan test logic. Methods for determining the compressed vectors' states, given the desired uncompressed vectors' values may be used, and techniques for selectively enabling test or other features on a chip by inserting the proper code or codes into the chip may further be used. Techniques may be used to incorporate and apply various types of reset operations to multiple strings of variable scan test logic, as may methods to minimize the test vector compression computation time.
摘要翻译：添加特定的测试逻辑可以提高从现有的可变扫描测试逻辑实现的测试向量压缩的水平。可以使用给定期望的未压缩向量值来确定压缩向量状态的方法，并且还可以使用用于通过将适当的代码或代码插入到芯片中来选择性地启用芯片上的测试或其他特征的技术。技术可以用于将各种类型的复位操作并入并应用于多个可变扫描测试逻辑串，作为使测试向量压缩计算时间最小化的方法。

40. 发明授权

US07818538B2 Hashing and serial decoding techniques 有权
标题翻译：散列和串行解码技术
公开(公告)号：US07818538B2
公开(公告)日：2010-10-19
申请号：US12199024
申请日：2008-08-27
申请人： Laurence H. Cooke
发明人： Laurence H. Cooke
IPC分类号： G06F12/00
CPC分类号： G06F9/345
摘要： A serial decoding technique may employ one or more circular shift register strings in which an input to an element of a shift register string may be gated by either an address input or the inverse of the address input. An output word line of the decoder may be driven by a respective shift register stage in the case of a single shift register string, or by a logical combination of shift register stages from respective shift register strings in the case of multiple shift register strings.
摘要翻译：串行解码技术可以采用一个或多个循环移位寄存器串，其中移位寄存器串的元素的输入可以通过地址输入或地址输入的反相来选通。在单个移位寄存器串的情况下，解码器的输出字线可以由相应的移位寄存器级驱动，或者在多个移位寄存器串的情况下由各移位寄存器串的移位寄存器级的逻辑组合来驱动。

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