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31. 发明授权

US07864574B2 Memory device and memory programming method 有权
标题翻译：存储器和存储器编程方法
公开(公告)号：US07864574B2
公开(公告)日：2011-01-04
申请号：US12453108
申请日：2009-04-29
申请人： Kyoung Lae Cho , Yong June Kim , Seung-Hwan Song , Jun Jin Kong
发明人： Kyoung Lae Cho , Yong June Kim , Seung-Hwan Song , Jun Jin Kong
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C2211/5621
摘要： Provided are memory devices and memory programming methods. A memory device may include a multi-bit cell array including a plurality of multi-bit cells, a programming unit configured to program a first data page in the plurality of multi-bit cells and to program a second data page in the multi-bit cells with the programmed first data page, a first controller configured to divide the multi-bit cells with the programmed first data page into a first group and a second group, and a second controller configured to set a target threshold voltage interval of each of the multi-bit cells included in the first group based on first read voltage levels and the second data page, and to set a target threshold voltage interval of each of the multi-bit cells included in the second group based on second read threshold voltage levels and the second data page.
摘要翻译：提供的是存储器件和存储器编程方法。存储器件可以包括包括多个多位单元的多位单元阵列，编程单元，被配置为对多个多位单元中的第一数据页进行编程，并编程多位单元中的第二数据页具有编程的第一数据页的单元，被配置为将多位单元与编程的第一数据页划分为第一组和第二组的第一控制器，以及配置成将每个的第一数据页的目标阈值电压间隔基于第一读取电压电平和第二数据页面包括在第一组中的多位单元，并且基于第二读取阈值电压电平来设置包括在第二组中的每个多位单元的目标阈值电压间隔，以及第二个数据页面。

32. 发明申请

US20090182934A1 Memory device and method of multi-bit programming 失效
标题翻译：多位编程的存储器件和方法
公开(公告)号：US20090182934A1
公开(公告)日：2009-07-16
申请号：US12155647
申请日：2008-06-06
申请人： Jaehong Kim , Kyoung Lae Cho , Jun Jin Kong , Heeseok Eun , Seung-Hwan Song
发明人： Jaehong Kim , Kyoung Lae Cho , Jun Jin Kong , Heeseok Eun , Seung-Hwan Song
IPC分类号： G06F12/02 , G11C16/04 , G11C7/00
CPC分类号： G11C11/5628 , G11C11/5671 , G11C29/00
摘要： Memory devices and multi-bit programming methods are provided. A memory device may include a plurality of memory units; a data separator that separates data into a plurality of groups; a selector that rotates each of the plurality of groups and transmits each of the groups to at least one of the plurality of memory units. The plurality of memory units may include page buffers that may program the transmitted group in a plurality of multi-bit cell arrays using a different order of a page programming operation. Through this, evenly reliable data pages may be generated.
摘要翻译：提供了存储器件和多位编程方法。存储器件可以包括多个存储器单元; 数据分离器，将数据分离成多个组; 选择器，其使所述多个组中的每一个旋转，并将所述组中的每一个发送到所述多个存储器单元中的至少一个。多个存储器单元可以包括可以使用页面编程操作的不同顺序对多个多位单元阵列中的发送组进行编程的页缓冲器。通过此，可能会生成均匀可靠的数据页。

33. 发明授权

US08276046B2 Apparatus for determining number of bits to be stored in memory cell 失效
标题翻译：用于确定要存储在存储单元中的位数的装置
公开(公告)号：US08276046B2
公开(公告)日：2012-09-25
申请号：US12219103
申请日：2008-07-16
申请人： Seung-Hwan Song , Kyoung Lae Cho , Jun Jin Kong , Jae Hong Kim
发明人： Seung-Hwan Song , Kyoung Lae Cho , Jun Jin Kong , Jae Hong Kim
IPC分类号： H03M13/00
CPC分类号： G11C11/56 , G06F11/1012 , G11C29/00
摘要： Example embodiments relate to an apparatus which may determine a length of data to be stored in a memory cell, and may store the data in a memory based on the determined length. A memory data storage apparatus according to example embodiments may, include: a determination unit that may determine a number of bits of data and a number of bits of data detection information to be stored in a memory cell; a data receiving unit that may receive data corresponding to the determined number of bits; an error correction coding unit that may perform an error correction coding with respect to the received data and generate data detection information corresponding to the number of bits of the data detection information; and a data storage unit that may store the received data and generated data detection information in the memory cell.
摘要翻译：示例性实施例涉及可以确定要存储在存储器单元中的数据的长度的装置，并且可以基于所确定的长度将数据存储在存储器中。根据示例实施例的存储器数据存储装置可以包括：确定单元，其可以确定要存储在存储器单元中的数据的位数和数据检测信息的位数; 数据接收单元，其可以接收与所确定的位数相对应的数据; 纠错编码单元，其可以对所接收的数据执行纠错编码，并生成与数据检测信息的位数相对应的数据检测信息; 以及数据存储单元，其可以将所接收的数据和生成的数据检测信息存储在存储单元中。

34. 发明授权

US08112693B2 Error control code apparatuses and methods of using the same 有权
标题翻译：错误控制代码设备及其使用方法
公开(公告)号：US08112693B2
公开(公告)日：2012-02-07
申请号：US11905734
申请日：2007-10-03
申请人： Jun Jin Kong , Seung-Hwan Song , Dong Hyuk Chae , Kyoung Lae Cho , Seung Jae Lee , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
发明人： Jun Jin Kong , Seung-Hwan Song , Dong Hyuk Chae , Kyoung Lae Cho , Seung Jae Lee , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
IPC分类号： G11C29/00
CPC分类号： G06F11/1072
摘要： An Error Control Code (ECC) apparatus applied to a memory of a Multi-Level Cell (MLC) method may include: a bypass control signal generator generating a bypass control signal; and an ECC performing unit that may include at least two ECC decoding blocks, determining whether to bypass a portion of the at least two ECC decoding blocks based on the bypass control signal, and/or performing an ECC decoding. In addition or in the alternative, the ECC performing unit may include at least two ECC encoding blocks, determining whether to bypass a portion of the at least two ECC encoding blocks based on the bypass control signal, and/or performing an ECC encoding. An ECC method applied to a memory of a MLC method and a computer-readable recording medium storing a program for implementing an EEC method applied to a memory of a MLC method are also disclose.
摘要翻译：应用于多电平单元（MLC）方法的存储器的错误控制码（ECC）装置可以包括：旁路控制信号发生器，其生成旁路控制信号; 以及ECC执行单元，其可以包括至少两个ECC解码块，基于旁路控制信号确定是否绕过所述至少两个ECC解码块的一部分，和/或执行ECC解码。另外或在替代方案中，ECC执行单元可以包括至少两个ECC编码块，基于旁路控制信号确定是否绕过至少两个ECC编码块的一部分，和/或执行ECC编码。还公开了应用于MLC方法的存储器的ECC方法和存储用于实现应用于MLC方法的存储器的EEC方法的程序的计算机可读记录介质。

35. 发明授权

US08004886B2 Apparatus and method of multi-bit programming 有权
标题翻译：多位编程的装置和方法
公开(公告)号：US08004886B2
公开(公告)日：2011-08-23
申请号：US12073101
申请日：2008-02-29
申请人： Seung-Hwan Song , Kyoung Lae Cho , Heeseok Eun , Dong Hyuk Chae , Jun Jin Kong , Sung Chung Park
发明人： Seung-Hwan Song , Kyoung Lae Cho , Heeseok Eun , Dong Hyuk Chae , Jun Jin Kong , Sung Chung Park
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/3418 , G11C2211/5621
摘要： Multi-bit programming apparatuses and/or methods are provided. A multi-bit programming apparatus may comprise: a multi-bit cell array that includes a first multi-bit cell and a second multi-bit cell; a programming unit for programming first data in the first multi-bit cell, and programming second data in the second multi-bit cell; and a verification unit for verifying whether the first data is programmed in the first multi-bit cell using a first verification voltage, and verifying whether the second data is programmed in the second multi-bit cell using a second verification voltage. The multi-bit programming apparatus may generate better threshold voltage distributions in a multi-bit cell memory.
摘要翻译：提供了多位编程设备和/或方法。多比特编程装置可以包括：包括第一多比特小区和第二多比特小区的多比特单元阵列; 编程单元，用于对第一多位单元中的第一数据进行编程，以及编程第二多位单元中的第二数据; 以及验证单元，用于使用第一验证电压来验证第一数据是否被编程在第一多位单元中，以及使用第二验证电压来验证第二数据是否被编程在第二多位单元中。多比特编程装置可以在多比特单元存储器中产生更好的阈值电压分布。

36. 发明申请

US20090285023A1 Memory device and memory programming method 有权
标题翻译：存储器和存储器编程方法
公开(公告)号：US20090285023A1
公开(公告)日：2009-11-19
申请号：US12453108
申请日：2009-04-29
申请人： Kyoung Lae Cho , Yong June Kim , Seung-Hwan Song , Jun Jin Kong
发明人： Kyoung Lae Cho , Yong June Kim , Seung-Hwan Song , Jun Jin Kong
IPC分类号： G11C16/02 , G11C7/00 , G11C16/06
CPC分类号： G11C16/10 , G11C11/5628 , G11C2211/5621
摘要： Provided are memory devices and memory programming methods. A memory device may include a multi-bit cell array including a plurality of multi-bit cells, a programming unit configured to program a first data page in the plurality of multi-bit cells and to program a second data page in the multi-bit cells with the programmed first data page, a first controller configured to divide the multi-bit cells with the programmed first data page into a first group and a second group, and a second controller configured to set a target threshold voltage interval of each of the multi-bit cells included in the first group based on first read voltage levels and the second data page, and to set a target threshold voltage interval of each of the multi-bit cells included in the second group based on second read threshold voltage levels and the second data page.
摘要翻译：提供的是存储器件和存储器编程方法。存储器件可以包括包括多个多位单元的多位单元阵列，编程单元，被配置为对多个多位单元中的第一数据页进行编程，并编程多位单元中的第二数据页具有编程的第一数据页的单元，被配置为将多位单元与编程的第一数据页划分为第一组和第二组的第一控制器，以及配置成将每个的第一数据页的目标阈值电压间隔基于第一读取电压电平和第二数据页面包括在第一组中的多位单元，并且基于第二读取阈值电压电平来设置包括在第二组中的每个多位单元的目标阈值电压间隔，以及第二个数据页面。

37. 发明申请

US20090207659A1 Memory device and memory data read method 有权
标题翻译：内存设备和内存数据读取方式
公开(公告)号：US20090207659A1
公开(公告)日：2009-08-20
申请号：US12219665
申请日：2008-07-25
申请人： Seung-Hwan Song , Heeseok Eun , Dong Hun Yu , Jun Jin Kong
发明人： Seung-Hwan Song , Heeseok Eun , Dong Hun Yu , Jun Jin Kong
IPC分类号： G11C16/26 , G11C16/34
CPC分类号： G11C16/26 , G11C11/5642 , G11C29/00
摘要： Provided are memory devices and memory data read methods. A method device may include: a multi-bit cell array; a decision unit that may detect threshold voltages of multi-bit cells of the multi-bit cell array to decide first data from the detected threshold voltages, using a first decision value; an error detector that may detect an error bit of the first data; and a determination unit that may determine whether the decision unit decides second data from the detected threshold voltages using a second decision value, based on a number of detected error bits, the second decision value being different from the first decision value. Through this, it is possible to reduce time spent for reading data stored in the multi-bit cell.
摘要翻译：提供的是存储器件和存储器数据读取方法。方法设备可以包括：多比特单元阵列; 判定单元，其可以使用第一判定值来检测所述多比特单元阵列的多比特单元的阈值电压以从所述检测到的阈值电压中确定第一数据; 可以检测第一数据的错误位的错误检测器; 以及确定单元，其可以基于检测到的错误位的数量来确定判定单元是否使用第二判定值从检测到的阈值电压确定第二数据，第二判定值与第一判定值不同。通过这种方式，可以减少读取存储在多位单元中的数据所花费的时间。

38. 发明授权

US07872909B2 Memory device and memory data read method 有权
标题翻译：内存设备和内存数据读取方式
公开(公告)号：US07872909B2
公开(公告)日：2011-01-18
申请号：US12219665
申请日：2008-07-25
申请人： Seung-Hwan Song , Heeseok Eun , Dong Hun Yu , Jun Jin Kong
发明人： Seung-Hwan Song , Heeseok Eun , Dong Hun Yu , Jun Jin Kong
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C29/00
摘要： Provided are memory devices and memory data read methods. A method device may include: a multi-bit cell array; a decision unit that may detect threshold voltages of multi-bit cells of the multi-bit cell array to decide first data from the detected threshold voltages, using a first decision value; an error detector that may detect an error bit of the first data; and a determination unit that may determine whether the decision unit decides second data from the detected threshold voltages using a second decision value, based on a number of detected error bits, the second decision value being different from the first decision value. Through this, it is possible to reduce time spent for reading data stored in the multi-bit cell.
摘要翻译：提供的是存储器件和存储器数据读取方法。方法设备可以包括：多比特单元阵列; 判定单元，其可以使用第一判定值来检测所述多比特单元阵列的多比特单元的阈值电压以从所述检测到的阈值电压中确定第一数据; 可以检测第一数据的错误位的错误检测器; 以及确定单元，其可以基于检测到的错误位的数量来确定判定单元是否使用第二判定值从检测到的阈值电压确定第二数据，第二判定值与第一判定值不同。通过这种方式，可以减少读取存储在多位单元中的数据所花费的时间。

39. 发明授权

US08028215B2 Error control code apparatuses and methods of using the same 有权
标题翻译：错误控制代码设备及其使用方法
公开(公告)号：US08028215B2
公开(公告)日：2011-09-27
申请号：US11905733
申请日：2007-10-03
申请人： Jun Jin Kong , Seung-Hwan Song , Young Hwan Lee , Dong Hyuk Chae , Kyong Lae Cho , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
发明人： Jun Jin Kong , Seung-Hwan Song , Young Hwan Lee , Dong Hyuk Chae , Kyong Lae Cho , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
IPC分类号： H03M13/00 , G06F11/00
CPC分类号： G06F11/1008
摘要： An Error Control Code (ECC) apparatus may include a control signal generator that generates an ECC control signal based on channel information. The ECC apparatus also may include: a plurality of ECC encoding controllers that output data respectively inputted via storage elements corresponding to the ECC control signal; and/or an encoding unit that encodes, using a plurality of data outputted from the plurality of ECC encoding controllers, encoding input data into a number of subdata corresponding to the ECC control signal. In addition or in the alternative, the ECC apparatus may include: a plurality of ECC decoding controllers that output data respectively inputted via the storage elements corresponding to the ECC control signal; and/or a decoding unit that decodes, using a plurality of data outputted from the plurality of ECC decoding controllers, a number of decoding input data corresponding to the ECC control signal into one piece of output data.
摘要翻译：错误控制码（ECC）装置可以包括基于频道信息产生ECC控制信号的控制信号发生器。 ECC装置还可以包括：多个ECC编码控制器，其输出经由与ECC控制信号对应的存储元件分别输入的数据; 和/或编码单元，其使用从所述多个ECC编码控制器输出的多个数据，将输入数据编码为对应于所述ECC控制信号的多个子数据进行编码。另外或者可选地，ECC装置可以包括：多个ECC解码控制器，其输出经由与ECC控制信号对应的存储元件分别输入的数据; 和/或解码单元，其使用从所述多个ECC解码控制器输出的多个数据将对应于所述ECC控制信号的多个解码输入数据解码为一条输出数据。

40. 发明授权

US08422307B2 Nonvolatile memory device and read method using dynamically determined read voltages 有权
标题翻译：非易失性存储器件和使用动态确定的读取电压的读取方法
公开(公告)号：US08422307B2
公开(公告)日：2013-04-16
申请号：US12797668
申请日：2010-06-10
申请人： Han Woong Yoo , Seung-Hwan Song , Hee seok Eun , Jun jin Kong
发明人： Han Woong Yoo , Seung-Hwan Song , Hee seok Eun , Jun jin Kong
IPC分类号： G11C16/04
CPC分类号： G11C16/34 , G11C11/5642
摘要： A method of reading a nonvolatile memory device comprises measuring threshold voltage distributions of a plurality of memory cells, combining the measured threshold voltage distributions, and determining local minimum points in the combined threshold voltage distributions to determine read voltages for a predetermined group of memory cells.
摘要翻译：读取非易失性存储器件的方法包括测量多个存储器单元的阈值电压分布，组合测量的阈值电压分布，以及确定组合阈值电压分布中的局部最小点，以确定预定组的存储器单元的读取电压。

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