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31. 发明授权

US06171923B2 Method for fabricating a DRAM cell structure on an SOI wafer incorporating a two dimensional trench capacitor 有权
标题翻译：在包含二维沟槽电容器的SOI晶片上制造DRAM单元结构的方法
公开(公告)号：US06171923B2
公开(公告)日：2001-01-09
申请号：US09379228
申请日：1999-08-23
申请人： Min-Hwa Chi , Chih-Yuan Lu
发明人： Min-Hwa Chi , Chih-Yuan Lu
IPC分类号： H01L2120
CPC分类号： H01L27/1087 , H01L21/84 , H01L27/10832 , H01L27/1203
摘要： A method for fabricating a DRAM cell, on a SOI layer, is described, featuring the incorporation of a two dimensional, trench capacitor structure, for increased DRAM cell signal, and the use of a polysilicon storage node structure to connect the SOI layer to the semiconductor substrate, to eliminate a floating body effect. A two dimensional trench is created by initially forming a vertical trench, through the SOI layer, through the underlying insulator layer, and into the semiconductor substrate. An isotropic etch is than performed to laterally remove a specific amount of insulator layer, exposed in the vertical trench, creating the lateral component of the two dimensional trench. A deposited polysilicon layer, coating the sides of the two dimensional trench, is used as the storage node structure, for the two dimensional, trench capacitor structure, while also connecting the SOI layer to the semiconductor substrate.
摘要翻译：描述了在SOI层上制造DRAM单元的方法，其特征在于结合用于增加的DRAM单元信号的二维沟槽电容器结构，以及使用多晶硅存储节点结构将SOI层连接到半导体衬底，消除浮体效应。通过初始形成穿过SOI层的垂直沟槽，穿过下面的绝缘体层并进入半导体衬底而形成二维沟槽。进行各向同性蚀刻以横向移除在垂直沟槽中暴露的特定量的绝缘体层，产生二维沟槽的横向分量。作为二维沟槽电容器结构的存储节点结构，同时也将SOI层与半导体基板连接，使用涂覆二维沟槽的侧面的沉积多晶硅层。

32. 发明授权

US6071774A Method for forming a capacitor with a multiple pillar structure 失效
标题翻译：一种形成具有多支柱结构的电容器的方法
公开(公告)号：US6071774A
公开(公告)日：2000-06-06
申请号：US121709
申请日：1998-07-24
申请人： Jan Mye Sung , Howard C. Kirsch , Chih-Yuan Lu
发明人： Jan Mye Sung , Howard C. Kirsch , Chih-Yuan Lu
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10817 , H01L27/10852 , H01L28/92 , H01L28/84 , Y10S438/947 , Y10S438/968
摘要： The present invention provides a method for fabricating a multiple pillar shaped capacitor which has pillars of a smaller dimension than the resolution of the photolithography tool. The invention has two embodiments for forming the pillars and third embodiment for patterning a conductive layer into discrete bottom electrodes. The method begins by forming a conductive layer on a first planarization layer. For the first embodiment, the pillars are formed using a photolithography mask with a pattern of spaced transparent areas. The dimensions of the spaced transparent areas and distances between the spaced transparent areas are smaller that the resolution of the lithographic tool. Spaced oxide islands are formed with the mask and are used as an etch mask to form spaced pillars from the conductive layer. The second embodiment for forming the pillars involves using small titanium silicide islands as an etch mask to define the pillars. The third embodiment uses two resist layers and a photo mask shifting (offset) technique to form small spaces between the electrodes. Lastly, a capacitor dielectric layer and a top electrode are formed over the bottom electrodes thereby completing the capacitor with a pillar structure.
摘要翻译：本发明提供一种制造多柱形电容器的方法，该多柱形电容器的尺寸小于光刻工具的分辨率。本发明具有用于形成支柱的两个实施例和用于将导电层图案化成离散底部电极的第三实施例。该方法开始于在第一平坦化层上形成导电层。对于第一实施例，使用具有间隔透明区域的图案的光刻掩模形成柱。间隔透明区域的尺寸和间隔开的透明区域之间的距离小于光刻工具的分辨率。用掩模形成间隔氧化物岛，并用作蚀刻掩模以与导电层形成间隔的柱。用于形成柱的第二实施例涉及使用小的硅化钛岛作为蚀刻掩模来限定柱。第三实施例使用两个抗蚀剂层和光掩模移位（偏移）技术在电极之间形成小的空间。最后，在底部电极上形成电容器电介质层和顶部电极，由此完成具有柱状结构的电容器。

33. 发明授权

US6057573A Design for high density memory with relaxed metal pitch 有权
标题翻译：设计用于高密度存储器，具有轻松的金属间距
公开(公告)号：US6057573A
公开(公告)日：2000-05-02
申请号：US313305
申请日：1999-05-17
申请人： Howard C. Kirsch , Chih-Yuan Lu
发明人： Howard C. Kirsch , Chih-Yuan Lu
IPC分类号： H01L23/522 , H01L23/528 , H01L27/105 , H01L27/108 , H01L21/8242
CPC分类号： H01L27/105 , H01L23/5221 , H01L23/5283 , H01L27/10805 , H01L2924/0002
摘要： A method and design for stitching polysilicon wordlines to straps formed of interconnected metal line segments formed in two or more metallization levels. Each strap comprises a continuous conductive metal line passing alternatively from one metal layer to another in a selected sequence. The sequence of segments in each strap alternates in phase with the sequence in next nearest neighbor straps but may be in phase with second nearest neighbor straps. Thereby the pitch of strap segments on each metallization level is at least twice that of the subjacent polysilicon wordlines. The total length of each metal in each strap is the same in all straps. This arrangement allows the use of metals having different resistivities in each strap with all the straps having identical overall resistance. The metals used in the two or more levels may also have different minimum design rules without compromising the identical overall performance of all the straps. In a second embodiment a method and design is described for doubling the length of polysilicon sub-wordlines in a sub-wordline memory array without reducing performance by connecting sub-wordline to sub-wordline decoders by metal straps connected to the sub-wordlines midpoints.
摘要翻译：一种用于将多晶硅字线拼接到由形成在两个或更多个金属化层级中的互连金属线段形成的带的方法和设计。每个带包括以选定的顺序交替地从一个金属层传递到另一个金属层的连续导电金属线。每个带中的段序列与下一个最近邻带中的序列相交，但是可以与第二最近邻带相同步。因此，每个金属化水平上的带段的间距至少是下面的多晶硅字线的两倍。每个皮带中的每个金属的总长度在所有带中是相同的。这种布置允许在每个带中使用具有不同电阻率的金属，其中所有带具有相同的整体电阻。在两个或更多个级别中使用的金属也可以具有不同的最小设计规则，而不会影响所有带的相同的整体性能。在第二实施例中，描述了一种方法和设计，用于使子字线存储器阵列中的多晶硅子字线的长度加倍，而不会通过连接到子字线中点的金属带将子字线连接到子字线解码器来降低性能。

34. 发明授权

US5759894A Method for forming a DRAM capacitor using HSG-Si 失效
标题翻译：使用HSG-Si形成DRAM电容器的方法
公开(公告)号：US5759894A
公开(公告)日：1998-06-02
申请号：US808338
申请日：1997-02-28
申请人： Horng-Huei Tseng , Chih-Yuan Lu
发明人： Horng-Huei Tseng , Chih-Yuan Lu
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/82 , H01L28/92
摘要： A method for forming a DRAM capacitor using HSG-Si includes forming a dielectric layer over a substrate. A portion of the dielectric layer is removed to expose a contact area on the substrate. A polysilicon layer is then formed over the dielectric layer and in the first trench. Then, a hemispherical-grained silicon (HSG-Si) layer is formed on the polysilicon layer using an initial phase HSG-Si process, thereby forming a large number of silicon grains on the polysilicon layer. Next, nitrogen atoms are implanted into the polysilicon layer using the HSG-Si layer as a mask to form nitrogen regions in the polysilicon layer. The HSG-Si layer is then removed and the polysilicon layer is thermally oxidized. The nitrogen regions function as an anti-oxidation mask so that polysilicon-oxide regions are formed between the nitrogen regions in the polysilicon layer. Afterwards, an etching process is performed using the polysilicon-oxide regions as a mask so that the nitrogen regions and portions of the polysilicon layer beneath the nitrogen regions are removed. This etching step forms second trenches in the polysilicon layer between the polysilicon-oxide regions, which are subsequently removed. After removing the polysilicon-oxide regions, the polysilicon layer is patterned and etched to form a bottom electrode of the capacitor of the dynamic random access memory. The capacitor dielectric and the top electrode of the capacitor are then formed using conventional methods.
摘要翻译：使用HSG-Si形成DRAM电容器的方法包括在衬底上形成电介质层。去除介电层的一部分以露出衬底上的接触区域。然后在电介质层上和第一沟槽中形成多晶硅层。然后，使用初始相HSG-Si工艺在多晶硅层上形成半球状硅（HSG-Si）层，从而在多晶硅层上形成大量的硅晶粒。接下来，使用HSG-Si层作为掩模将氮原子注入到多晶硅层中，以在多晶硅层中形成氮区。然后去除HSG-Si层，并且多晶硅层被热氧化。氮区域用作抗氧化掩模，使得在多晶硅层中的氮区域之间形成多晶氧化物区域。然后，使用多晶硅氧化物区域作为掩模进行蚀刻处理，使得氮区域和氮区域下方的多晶硅层的部分被去除。该蚀刻步骤在多晶硅层之间形成第二沟槽，该多晶硅层随后被去除。在去除多晶硅氧化物区域之后，对多晶硅层进行图案化和蚀刻以形成动态随机存取存储器的电容器的底部电极。然后使用常规方法形成电容器电介质和电容器的顶部电极。

35. 发明授权

US5552620A Vertical transistor with high density DRAM cell and method of making 失效
标题翻译：具有高密度DRAM单元的垂直晶体管及其制造方法
公开(公告)号：US5552620A
公开(公告)日：1996-09-03
申请号：US428763
申请日：1995-04-24
申请人： Chih-Yuan Lu , Horng-Huei Tseng
发明人： Chih-Yuan Lu , Horng-Huei Tseng
IPC分类号： H01L27/108
CPC分类号： H01L27/10841 , Y10S257/90
摘要： There is shown a method for fabricating a vertical DRAM cell which includes a field effect transistor having a gate electrode and source/drain elements and a capacitor. There is provided a pattern of field oxide isolation in a silicon substrate wherein there are a pattern of openings to the silicon substrate. A pattern is formed of bit lines and a pattern of lines of holes with a hole located within each of the openings to said silicon substrate which lines of holes and bit lines are perpendicular to one another and which the lines cross at the planned locations of the vertical DRAM cell at the pattern of openings to the silicon substrate. A gate dielectric is formed on the surfaces of the holes. A doped polysilicon layer is formed in and over the holes so that it covers the gate dielectric and the field oxide isolation. A silicon nitride layer is formed over the doped polysilicon layer. Patterning and etching is done to the silicon nitride layer and doped polysilicon layer to form the opening for the capacitor node contact to the buried source/drain of the vertical field effect transistor (switching device for the storage signal) and establish said gate electrode in the hole and word line pattern over the field oxide insulator. A silicon oxide spacer is formed over the sidewalls of the silicon nitride and doped polysilicon layer. A capacitor is formed in and over the hole to complete the vertical DRAM cell.
摘要翻译：示出了制造垂直DRAM单元的方法，其包括具有栅电极和源极/漏极元件的电场效应晶体管和电容器。在硅衬底中提供了场氧化物隔离的图案，其中存在到硅衬底的开口图案。图案由位线和具有位于每个到所述硅衬底的每个开口内的孔的线的图案形成，孔和位线的线彼此垂直，并且线在所述硅衬底的计划位置处交叉垂直DRAM单元以与硅衬底的开口的图案形成。在孔的表面上形成栅极电介质。在孔内和上方形成掺杂多晶硅层，使其覆盖栅极电介质和场氧化物隔离。在掺杂多晶硅层上形成氮化硅层。对氮化硅层和掺杂多晶硅层进行图案化和蚀刻，以形成用于电容器节点接触到垂直场效应晶体管（用于存储信号的开关器件）的掩埋源极/漏极的开口，并在孔和字线图形在场氧化物绝缘体上。在氮化硅和掺杂多晶硅层的侧壁上形成氧化硅隔离物。在孔内和上方形成电容器以完成垂直DRAM单元。

36. 发明授权

US5550077A DRAM cell with a comb-type capacitor 失效
标题翻译：具有梳状电容器的DRAM单元
公开(公告)号：US5550077A
公开(公告)日：1996-08-27
申请号：US435203
申请日：1995-05-05
申请人： Horng-Huei Tseng , Chih-Yuan Lu
发明人： Horng-Huei Tseng , Chih-Yuan Lu
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： An efficient method for manufacturing a comb-type capacitor for use as part of a DRAM cell in a silicon integrated circuit is described. A three toothed comb is created by first forming a central pedestal of polysilicon, providing oxide spacers on the vertical sides of said pedestal, coating said spacers with an additional layer of polysilicon, and then etching away said spacers thereby creating the comb structure. In addition to the comb, the method of the present invention also leads to the formation of a projecting rim of polysilicon that runs around all four sides of the capacitor structure, thereby further increasing its effective surface beyond that due to the comb.
摘要翻译：描述了一种用于制造用作硅集成电路中的DRAM单元的一部分的梳状电容器的有效方法。通过首先形成多晶硅的中心基座，在所述基座的垂直侧上提供氧化物隔离物，用附加的多晶硅层涂覆所述间隔物，然后蚀刻所述间隔物从而形成梳状结构，从而产生三齿梳。除了梳子之外，本发明的方法还导致在电容器结构的所有四个侧面上形成突出的多晶硅边缘，从而进一步增加其有效表面超过由于梳子的有效表面。

37. 发明授权

US5534457A Method of forming a stacked capacitor with an "I" shaped storage node 失效
标题翻译：用“I”形存储节点形成堆叠电容器的方法
公开(公告)号：US5534457A
公开(公告)日：1996-07-09
申请号：US375783
申请日：1995-01-20
申请人： Horng-Huei Tseng , Chih-Yuan Lu
发明人： Horng-Huei Tseng , Chih-Yuan Lu
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/60 , H01L28/86
摘要： A DRAM having a high capacitance stacked capacitor is fabricated by forming gate structures in the device areas and lines over field oxide areas on a substrate. A first insulating layer is formed and patterned to leave the source/drain structures open in the device areas where electrical contact is desired to the stacked capacitors. A bottom electrode of the capacitor is now formed by depositing and patterning a second polysilicon layer and a second insulating layer. Next the second polysilicon layer is laterally etched so that portions of the second polysilicon layer are etched out underneath from the second insulating layer. A third polysilicon layer is formed on the vertical sidewalls of the second polysilicon layer. A capacitor dielectric layer is deposited over the substrate surface and patterned so that portions remain covering the second and third polysilicon layers. A top electrode is formed over the capacitor dielectric layer.
摘要翻译：通过在衬底上的场氧化物区域上的器件区域和线中形成栅极结构来制造具有高电容层叠电容器的DRAM。第一绝缘层被形成并图案化以使得源极/漏极结构在需要电接触到堆叠的电容器的器件区域中断开。电容器的底部电极现在通过沉积和构图第二多晶硅层和第二绝缘层而形成。接下来，第二多晶硅层被横向蚀刻，使得第二多晶硅层的部分在第二绝缘层的下方被蚀刻掉。在第二多晶硅层的垂直侧壁上形成第三多晶硅层。电容器介电层沉积在衬底表面上并被图案化，使得部分保持覆盖第二和第三多晶硅层。在电容器电介质层上形成顶部电极。

38. 发明授权

US07180767B2 Multi-level memory device and methods for programming and reading the same 有权
标题翻译：多级存储器件及其编程和读取方法
公开(公告)号：US07180767B2
公开(公告)日：2007-02-20
申请号：US10465012
申请日：2003-06-18
申请人： Yi Chou Chen , Chih-Yuan Lu
发明人： Yi Chou Chen , Chih-Yuan Lu
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0069
摘要： A multilevel memory core includes a word line and a bit line. The multilevel memory core also includes a core cell in electrical communication with the word line and the bit line. The core cell includes a threshold changing material. The threshold changing material is programmed to define multiple levels for storage where each of the multiple levels for storage is associated with a corresponding threshold voltage. Methods for reading the multilevel memory core also are described.
摘要翻译：多级存储器核心包括字线和位线。多级存储器核心还包括与字线和位线电通信的核心单元。核心单元包括阈值变化材料。阈值改变材料被编程为定义用于存储的多个级别，其中用于存储的多个级别中的每一个与相应的阈值电压相关联。还描述了读取多级存储器核心的方法。

39. 发明授权

US06828081B2 Method and system for lithography using phase-change material 有权
公开(公告)号：US06828081B2
公开(公告)日：2004-12-07
申请号：US10315003
申请日：2002-12-10
申请人： Yi-Chou Chen , Chih-Yuan Lu , Hsiang-Lan Lung , Li-Hsin Chuang
发明人： Yi-Chou Chen , Chih-Yuan Lu , Hsiang-Lan Lung , Li-Hsin Chuang
IPC分类号： H01L2182
CPC分类号： H01L45/1213 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： Methods and systems are provided for forming an electrical interconnect layer between two layers of an integrated circuit. The interconnect layer is formed using a material having a first electrical conductivity corresponding to a first state and a second electrical conductivity corresponding to a second state, where the first electrical conductivity is different from the second electrical conductivity. An area of the material of the interconnect layer may be selected, for example, using a mask. Then energy may be applied to the selected area to change the electrical conductivity of the material in the selected area of the interconnect layer. Thus, the present invention may be used to implement optical memory devices which may be read by an electrical circuit.

40. 发明授权

US06479341B1 Capacitor over metal DRAM structure 失效
标题翻译：金属DRAM结构电容器
公开(公告)号：US06479341B1
公开(公告)日：2002-11-12
申请号：US09033102
申请日：1998-03-02
申请人： Chih-Yuan Lu
发明人： Chih-Yuan Lu
IPC分类号： H01L218242
CPC分类号： H01L27/10855 , H01L27/10814 , H01L27/10885 , H01L27/10894 , H01L28/91
摘要： A method of creating a Capacitor Over Metal, (COM), stacked capacitor structure, for a DRAM device, has been developed. The process features creating metal interconnect structures, prior to the creation of the COM, stacked capacitor structure. The metal structures are connected to underlying regions of the semiconductor substrate via polysilicon contact plugs, and metal studs, while the same metal structures are connected to overlying structures, such as the COM stacked capacitor structure, via additional metal studs. Planarization of passivating insulator layers, result in topology reductions, reducing the severity of opening via holes to specific metal structures.
摘要翻译：已经开发了一种为DRAM器件制造电容器金属（COM），堆叠电容器结构的方法。该工艺的特点是在创建COM堆叠电容器结构之前创建金属互连结构。金属结构通过多晶硅接触塞和金属螺柱连接到半导体衬底的下面的区域，而相同的金属结构通过额外的金属螺柱连接到覆盖结构，例如COM堆叠电容器结构。钝化绝缘体层的平面化，导致拓扑结构的减少，减少了通孔到特定金属结构的开孔严重性。

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