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31. 发明授权

US6055605A Technique for reducing latency of inter-reference ordering using commit signals in a multiprocessor system having shared caches 失效
标题翻译：用于在具有共享高速缓存的多处理器系统中使用提交信号来减少参考间排序的等待时间的技术
公开(公告)号：US6055605A
公开(公告)日：2000-04-25
申请号：US957544
申请日：1997-10-24
申请人： Madhumitra Sharma , Simon C. Steely, Jr. , Kourosh Gharachorloo , Stephen R. Van Doren
发明人： Madhumitra Sharma , Simon C. Steely, Jr. , Kourosh Gharachorloo , Stephen R. Van Doren
IPC分类号： G06F12/08 , G06F13/00 , G06F12/00
CPC分类号： G06F12/084
摘要： A technique reduces the latency of inter-reference ordering between sets of memory reference operations in a multiprocessor system having a shared memory that is distributed among a plurality of processors that share a cache. According to the technique, each processor sharing a cache inherits a commit-signal that is generated by control logic of the multiprocessor system in response to a memory reference operation issued by another processor sharing that cache. The commit-signal facilitates serialization among the processors and shared memory entities of the multiprocessor system by indicating the apparent completion of the memory reference operation to those entities of the system.
摘要翻译：一种技术减少了具有分配在共享高速缓存的多个处理器之间的共享存储器的多处理器系统中的存储器参考操作组之间的参考间排序的等待时间。根据该技术，共享高速缓存的每个处理器响应由共享该高速缓存的另一个处理器发出的存储器引用操作而继承由多处理器系统的控制逻辑产生的提交信号。提交信号通过指示对系统的那些实体的存储器参考操作的明显完成来促进多处理器系统的处理器和共享存储器实体之间的串行化。

32. 发明授权

US08762280B1 Method and system for using a network analysis system to verify content on a website 有权
标题翻译：使用网络分析系统验证网站内容的方法和系统
公开(公告)号：US08762280B1
公开(公告)日：2014-06-24
申请号：US12917190
申请日：2010-11-01
申请人： Victor Bennett , Shrish Agrawal , Niels Provos , Jayesh Sharma , Kourosh Gharachorloo , Gokul Rajaram
发明人： Victor Bennett , Shrish Agrawal , Niels Provos , Jayesh Sharma , Kourosh Gharachorloo , Gokul Rajaram
IPC分类号： G06F21/00
CPC分类号： G06F21/6209 , G06F2221/2149 , G06Q30/0251
摘要： A system and method for verifying content on a network site is provided. A document such as a website is identified. The document is accessed over a network from a content provider system connected to the network to obtain information about the document. Through an automated process, using the information about the document to determine whether the document conforms to one or more predetermined rules associated with the content provider system governing the usage of content in the document.
摘要翻译：提供了一种用于验证网站上的内容的系统和方法。识别诸如网站的文档。该文档通过网络从连接到网络的内容提供商系统访问以获得关于文档的信息。通过自动化过程，使用关于文档的信息来确定文档是否符合与管理文档中的内容的使用的内容提供者系统相关联的一个或多个预定规则。

33. 发明授权

US06925537B2 Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants 有权
标题翻译：多处理器高速缓存一致性系统和方法，其中处理器节点和输入/输出节点是相等的参与者
公开(公告)号：US06925537B2
公开(公告)日：2005-08-02
申请号：US10698130
申请日：2003-10-31
申请人： Luiz A. Barroso , Kourosh Gharachorloo , Andreas Nowatzyk , Mosur K. Ravishankar , Robert J. Stets, Jr.
发明人： Luiz A. Barroso , Kourosh Gharachorloo , Andreas Nowatzyk , Mosur K. Ravishankar , Robert J. Stets, Jr.
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0817 , G06F2212/621
摘要： A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol. Each processor core has an associated memory cache for caching memory lines of information. Each input/output node includes no processor cores, an input/output interface for interfacing to an input/output bus or input/output device, a memory cache for caching memory lines of information and an interface to a local memory subsystem. The local memory subsystem of each processor node and input/output node stores a multiplicity of memory lines of information. The protocol engine of each processor node and input/output node implements the same predefined cache coherence protocol.
摘要翻译：计算机系统具有多个处理器节点和多个输入/输出节点。每个处理器节点包括多个处理器核心，到本地存储器系统的接口和实现预定义高速缓存一致性协议的协议引擎。每个处理器核心具有用于缓存存储器信息线的相关联的存储器缓存。每个输入/输出节点不包括处理器内核，用于与输入/输出总线或输入/输出设备进行接口的输入/输出接口，用于缓存存储器信息线的存储器缓存和到本地存储器子系统的接口。每个处理器节点和输入/输出节点的本地存储器子系统存储多个存储器信息线。每个处理器节点和输入/输出节点的协议引擎实现相同的预定义缓存一致性协议。

34. 发明授权

US06751720B2 Method and system for detecting and resolving virtual address synonyms in a two-level cache hierarchy 失效
标题翻译：用于检测和解析两级缓存层次结构中的虚拟地址同义词的方法和系统
公开(公告)号：US06751720B2
公开(公告)日：2004-06-15
申请号：US10042054
申请日：2002-01-07
申请人： Luiz André Barroso , Kourosh Gharachorloo , Andreas Nowatzyk , Robert J. Stets, Jr. , Mosur Kumaraswamy Ravishankar
发明人： Luiz André Barroso , Kourosh Gharachorloo , Andreas Nowatzyk , Robert J. Stets, Jr. , Mosur Kumaraswamy Ravishankar
IPC分类号： G06F1200
CPC分类号： G06F12/0826 , G06F12/0828 , G06F2212/621
摘要： L1 cache synonyms in a two-level cache system are detected and resolved by logic in the L2 cache. Duplicate copies of the L1 cache tags and state (“Dtags”) are maintained in the L2 cache. After a miss occurs in the L1 cache, the Dtags in the second-level cache that correspond to all possible synonym locations in the L1 cache are searched for synonyms. If a synonym is found, the L2 cache notifies the L1 cache where the requested cache line can be found in the L1 cache. The L1 cache then copies the cache line from the location where the synonym was found to the location where the miss occurred, and it invalidates the cache line at the original location. The Dtags in the second-level cache are updated to reflect the changes made in the L1 cache.
摘要翻译：二级缓存系统中的L1缓存同义词通过L2缓存中的逻辑进行检测和解析。 L1缓存标签和状态（“Dtags”）的重复副本被保留在L2高速缓存中。在L1高速缓存中出现未命中之后，搜索对应于L1高速缓存中所有可能的同义词位置的二级高速缓存中的Dtags同义词。如果发现同义词，则L2缓存通知L1缓存，其中可以在L1缓存中找到所请求的高速缓存行。然后，L1高速缓存从发现同义词的位置复制缓存行到发生未命中的位置，并且使原始位置的高速缓存行无效。更新二级缓存中的Dtags以反映L1缓存中所做的更改。

35. 发明授权

US06725343B2 System and method for generating cache coherence directory entries and error correction codes in a multiprocessor system 有权
标题翻译：用于在多处理器系统中生成高速缓存一致目录条目和纠错码的系统和方法
公开(公告)号：US06725343B2
公开(公告)日：2004-04-20
申请号：US09972477
申请日：2001-10-05
申请人： Luiz A. Barroso , Kourosh Gharachorloo , Andreas Nowatzyk
发明人： Luiz A. Barroso , Kourosh Gharachorloo , Andreas Nowatzyk
IPC分类号： G06F1208
CPC分类号： G06F12/0817 , G06F11/1064 , G06F11/1666 , G06F2212/2542
摘要： Each node of a multiprocessor computer system includes a main memory, a cache memory system and logic. The main memory stores memory lines of data. A directory entry for each memory line indicates whether a copy of the corresponding memory line is stored in the cache memory system in another node. The cache memory system stores copies of memory lines and cache state information indicating whether the cached copy of each memory line is an exclusive copy. The logic of each respective node is configured to respond to a transaction request for a particular memory line and its corresponding directory entry, where the respective node is the home node of the particular memory. When the cache memory system of the home node stores an exclusive copy of the particular memory line, the logic responds to the request by sending the copy of the particular memory line retrieved from the cache memory system and a predefined null directory entry value, and thus does not retrieve the memory line and its directory entry from the main memory of the home node.
摘要翻译：多处理器计算机系统的每个节点包括主存储器，高速缓冲存储器系统和逻辑。主存储器存储数据的存储线。每个存储器线的目录条目指示对应的存储器行的副本是否存储在另一个节点的高速缓存存储器系统中。高速缓冲存储器系统存储指示每个存储器线的高速缓存副本是否是专用副本的存储器行的副本和高速缓存状态信息。每个相应节点的逻辑被配置为响应特定存储器线及其对应的目录条目的事务请求，其中相应节点是特定存储器的归属节点。当家庭节点的高速缓冲存储器系统存储特定存储器线的专用副本时，逻辑通过发送从高速缓冲存储器系统检索的特定存储器线的副本和预定义的空目录条目值来响应该请求，因此不从主节点的主存储器检索内存条及其目录条目。

36. 发明授权

US06668308B2 Scalable architecture based on single-chip multiprocessing 有权
公开(公告)号：US06668308B2
公开(公告)日：2003-12-23
申请号：US09877793
申请日：2001-06-08
申请人： Luiz Andre Barroso , Kourosh Gharachorloo , Andreas Nowatzyk
发明人： Luiz Andre Barroso , Kourosh Gharachorloo , Andreas Nowatzyk
IPC分类号： G06F1200
CPC分类号： G06F12/0811 , G06F12/0826 , G06F2212/621
摘要： A chip-multiprocessing system with scalable architecture, including on a single chip: a plurality of processor cores; a two-level cache hierarchy; an intra-chip switch; one or more memory controllers; a cache coherence protocol; one or more coherence protocol engines; and an interconnect subsystem. The two-level cache hierarchy includes first level and second level caches. In particular, the first level caches include a pair of instruction and data caches for, and private to, each processor core. The second level cache has a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores. Each of the plurality of processor cores is capable of executing an instruction set of the ALPHA™ processing core. The scalable architecture of the chip-multiprocessing system is targeted at parallel commercial workloads. A showcase example of the chip-multiprocessing system, called the PIRANHA™ system, is a highly integrated processing node with eight simpler ALPHA™ processor cores. A method for scalable chip-multiprocessing is also provided.

37. 发明授权

US6101420A Method and apparatus for disambiguating change-to-dirty commands in a switch based multi-processing system with coarse directories 失效
标题翻译：在具有粗略目录的基于交换机的多处理系统中消除歧义指令的方法和装置
公开(公告)号：US6101420A
公开(公告)日：2000-08-08
申请号：US957543
申请日：1997-10-24
申请人： Stephen R. VanDoren , Simon C. Steely , Madhumitra Sharma , Kourosh Gharachorloo
发明人： Stephen R. VanDoren , Simon C. Steely , Madhumitra Sharma , Kourosh Gharachorloo
IPC分类号： G05B19/18
CPC分类号： G05B19/0421 , G05B2219/2213 , G05B2219/2227
摘要： An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory. Memory performance is additionally improved by including, at each memory, a delayed write buffer which is used in conjunction with the directory to identify victims that are to be written to memory. An arb bus coupled to the output of the directory of each node provides a central ordering point for all messages that are transferred through the SMP. The messages comprise a number of transactions, and each transaction is assigned to a number of different virtual channels, depending upon the processing stage of the message. The use of virtual channels thus helps to maintain data coherency by providing a straightforward method for maintaining system order. Using the virtual channels and the directory structure, cache coherency problems that would previously result in deadlock may be avoided.
摘要翻译：用于大SMP计算机系统的架构和一致性协议包括分层交换结构，其允许多个多处理器节点耦合到交换机以以最佳性能进行操作。在每个多处理器节点内，提供同时缓冲系统，其允许多处理器节点的所有处理器以最高性能运行。存储器在节点之间共享，存储器的一部分驻留在每个多处理器节点处。每个多处理器节点包括用于维持存储器一致性的多个元件，包括受害缓存，目录和事务跟踪表。受害者缓存允许选择性地更新目的地存储在远程多处理节点处的存储器的受害者数据，从而提高存储器的整体性能。通过在每个存储器处包括延迟的写入缓冲器来进一步改善存储器性能，该缓冲器与目录一起使用以识别要写入存储器的受害者。耦合到每个节点的目录的输出的arb总线为通过SMP传输的所有消息提供了中心排序点。消息包括多个事务，并且根据消息的处理阶段，将每个事务分配给多个不同的虚拟通道。因此，通过提供用于维护系统顺序的简单方法，使用虚拟通道有助于维持数据一致性。使用虚拟通道和目录结构，可以避免先前导致死锁的高速缓存一致性问题。

38. 发明授权

US6085263A Method and apparatus for employing commit-signals and prefetching to maintain inter-reference ordering in a high-performance I/O processor 失效
标题翻译：用于采用提交信号和预取以在高性能I / O处理器中维持参考间排序的方法和装置
公开(公告)号：US6085263A
公开(公告)日：2000-07-04
申请号：US956861
申请日：1997-10-24
申请人： Madhumitra Sharma , Chester Pawlowski , Kourosh Gharachorloo , Stephen R. Van Doren , Simon C. Steely, Jr.
发明人： Madhumitra Sharma , Chester Pawlowski , Kourosh Gharachorloo , Stephen R. Van Doren , Simon C. Steely, Jr.
IPC分类号： G06F12/08 , G06F13/12 , G06F13/14
CPC分类号： G06F12/082 , G06F13/124 , G06F12/0862 , G06F2212/621
摘要： An improved I/O processor (IOP) delivers high I/O performance while maintaining inter-reference ordering among memory reference operations issued by an I/O device as specified by a consistency model in a shared memory multiprocessor system. The IOP comprises a retire controller which imposes inter-reference ordering among the operations based on receipt of a commit signal for each operation, wherein the commit signal for a memory reference operation indicates the apparent completion of the operation rather than actual completion of the operation. In addition, the IOP comprises a prefetch controller coupled to an I/O cache for prefetching data into cache without any ordering constraints (or out-of-order). The ordered retirement functions of the IOP are separated from its prefetching operations, which enables the latter operations to be performed in an arbitrary manner so as to improve the overall performance of the system.
摘要翻译：改进的I / O处理器（IOP）提供高I / O性能，同时在由共享存储器多处理器系统中的一致性模型指定的I / O设备发出的存储器参考操作之间保持参考间排序。 IOP包括退出控制器，其基于对每个操作的提交信号的接收，在操作之间施加参考间排序，其中用于存储器参考操作的提交信号指示操作的明显完成，而不是实际完成操作。此外，IOP包括耦合到I / O缓存的预取控制器，用于将数据预取到高速缓存中，而没有任何排序限制（或无序）。 IOP的有序退休功能与其预取操作分离，这使得后面的操作能够以任意方式执行，从而提高系统的整体性能。

39. 发明授权

US5787480A Lock-up free data sharing 失效
标题翻译：锁定免费数据共享
公开(公告)号：US5787480A
公开(公告)日：1998-07-28
申请号：US684281
申请日：1996-07-17
申请人： Daniel J. Scales , Kourosh Gharachorloo
发明人： Daniel J. Scales , Kourosh Gharachorloo
IPC分类号： G06F9/46 , G06F12/00
CPC分类号： G06F9/52
摘要： A software implemented method for lock-up free data sharing operates in a networked computer system including a plurality of workstations. Each workstation including a processor, a memory having addresses, and an input/output interface connected to each other by a bus. A set of addresses of the memories are designated as virtual shared addresses to store shared data. A portion of the virtual shared addresses is allocated to store the shared data as a plurality of blocks accessible by programs executing in any of the processors, each block including an integer number of lines. A program is instrumented to request an exclusive copy of the block if the program includes a store instruction which attempts to access data stored in a non-exclusive copy of the block. Additional instructions of the program are executed while the request for the exclusive copy of the block is pending. Addresses of data of the block modified by the additional instructions are recorded. In response to receiving the exclusive copy of the block, the modified data stored at the recorded addresses are merged with the data of the exclusive copy of the block.
摘要翻译：用于锁定免费数据共享的软件实现方法在包括多个工作站的联网计算机系统中运行。每个工作站包括处理器，具有地址的存储器以及通过总线彼此连接的输入/输出接口。存储器的一组地址被指定为虚拟共享地址以存储共享数据。分配虚拟共享地址的一部分以将共享数据存储为可由在任何处理器中执行的程序访问的多个块，每个块包括整数行。如果程序包括尝试访问存储在块的非排他性副本中的数据的存储指令，则程序被用来请求块的排他副本。当程序的独占副本的请求待决时，执行程序的附加指令。记录由附加指令修改的块的数据地址。响应于接收到块的独占副本，存储在记录地址处的修改数据与块的专用副本的数据合并。

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