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31. 发明授权

US5113390A Data transfer network suitable for use in a parallel computer 失效
标题翻译：数据传输网络适用于并行计算机
公开(公告)号：US5113390A
公开(公告)日：1992-05-12
申请号：US508065
申请日：1990-04-10
申请人： Takehisa Hayashi , Koichiro Omoda , Teruo Tanaka , Naoki Hamanaka , Shigeo Nagashima
发明人： Takehisa Hayashi , Koichiro Omoda , Teruo Tanaka , Naoki Hamanaka , Shigeo Nagashima
IPC分类号： H04L12/935 , H04L12/937
CPC分类号： H04L49/3018 , H04L49/254 , H04L49/3027
摘要： A computer system having a plurality of processors assigned first and second address portions are connected to a plurality of switch circuits. A first group transfer networks are connected to a corresponding first group of the plurality of switch circuits. Each of the transfer networks concurrently transfer data among the switch circuits. The switch circuits are provided to processors of a first kind arranged in a plurality of processor groups. The processor groups of the first kind include processors with different values for first address portions and the same value for second address portions. Additional transfer networks, processors and switches functioning in a similar manner are provided to expand the above system. In another embodiment of the present invention a data transfer network is provided having a plurality of processors for data transfer. The network includes a plurality of multistage switches each belonging to one of plural stages and connected to the switches of a preceding stage and to switches of the succeeding stage. Each of the switches are arranged to receive packets from a preceding switch. A packet includes a target process address and data to be transferred. A path select device is connected to receive packets and is also connected to plural switches belonging to a next stage for the transfer of the received partial addresses and partial data. A control device is connected to receive the partial addresses and partial data and is responsive to a predetermined bit within the received partial addresses. The control means is responsive to the arrival of the first partial address of the packet.

32. 发明授权

US06970912B2 Computer system having a plurality of computers each providing a shared storage access processing mechanism for controlling local/remote access to shared storage devices 失效
标题翻译：计算机系统具有多个计算机，每个计算机提供用于控制对共享存储设备的本地/远程访问的共享存储访问处理机制
公开(公告)号：US06970912B2
公开(公告)日：2005-11-29
申请号：US09311952
申请日：1999-05-18
申请人： Hideki Murayama , Hiroshi Yashiro , Satoshi Yoshizawa , Kazuo Horikawa , Takehisa Hayashi , Hiroshi Iwamoto , Kimitoshi Yamada
发明人： Hideki Murayama , Hiroshi Yashiro , Satoshi Yoshizawa , Kazuo Horikawa , Takehisa Hayashi , Hiroshi Iwamoto , Kimitoshi Yamada
IPC分类号： G06F13/14 , G06F1/00 , G06F3/06 , G06F12/14 , G06F13/00 , G06F15/17 , G06F21/00 , G06F21/24 , G06F15/167
CPC分类号： G06F3/062 , G06F3/0622 , G06F3/0637 , G06F3/067 , G06F21/80
摘要： A computer system having a plurality of computers connected to each other by a computer coupling mechanism. Each computer includes a processor, memory, I/O device, disk control mechanism, computer coupling network adapter, disk requirement processing section connected to a system bus, and a disk connected to a disk control mechanism. The disk requirement processing section controls the disk, in response to a processing requirement for the disk from one of the processors of the other computers, based on structural definition information. The structural definition information describes a structure of the computer system. The computer system may be a loosely-coupled computer system.
摘要翻译：一种具有通过计算机连接机构彼此连接的多个计算机的计算机系统。每个计算机包括处理器，存储器，I / O设备，磁盘控制机构，计算机耦合网络适配器，连接到系统总线的磁盘需求处理部分以及连接到磁盘控制机构的磁盘。磁盘需求处理部分基于结构定义信息响应于来自其他计算机的其中一个处理器的磁盘的处理要求来控制磁盘。结构定义信息描述了计算机系统的结构。计算机系统可以是松散耦合的计算机系统。

33. 发明授权

US06728258B1 Multi-processor system and its network 失效
标题翻译：多处理器系统及其网络
公开(公告)号：US06728258B1
公开(公告)日：2004-04-27
申请号：US09456383
申请日：1999-12-08
申请人： Tetsuhiko Okada , Naoki Hamanaka , Naohiko Irie , Takehisa Hayashi , Tetsuya Mochida , Masabumi Shibata , Youichi Tanaka , Yasuhiro Ishii
发明人： Tetsuhiko Okada , Naoki Hamanaka , Naohiko Irie , Takehisa Hayashi , Tetsuya Mochida , Masabumi Shibata , Youichi Tanaka , Yasuhiro Ishii
IPC分类号： H04L1266
CPC分类号： G06F15/17375 , G06F12/0833 , G06F2212/1016 , G06F2212/206
摘要： In a multi-processor system interconnecting processor units, memory units, and input/output units connected to input/output devices via a crossbar switch having a plurality of ports, the transmitter of each processor unit has a circuit for determining a destination of an access request in the following manner. For an access request to a main memory, the access request is transferred to all processor units and one memory unit storing the data to be accessed. For an access request to a memory mapped register of the input/output device, the access request is broadcast to all input/output units. For an access request to a memory mapped register belonging to any one of the processor units, memory units, and input/output units, the access request is broadcast to all units via the crossbar switch.
摘要翻译：在通过具有多个端口的交叉开关连接到处理器单元，存储器单元和连接到输入/输出设备的输入/输出单元的多处理器系统中，每个处理器单元的发射器具有用于确定接入的目的地的电路请求以下列方式。对于对主存储器的访问请求，访问请求被传送到存储要访问的数据的所有处理器单元和一个存储单元。对于对输入/输出设备的存储器映射寄存器的访问请求，将访问请求广播到所有输入/输出单元。对于属于处理器单元，存储器单元和输入/输出单元中的任何一个的存储器映射寄存器的访问请求，访问请求经由交叉开关广播到所有单元。

34. 发明授权

US06519667B2 Bus control system 失效
公开(公告)号：US06519667B2
公开(公告)日：2003-02-11
申请号：US09991925
申请日：2001-11-26
申请人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
发明人： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
IPC分类号： G06F1300
CPC分类号： G06F13/4027 , G06F13/36
摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

35. 发明授权

US06477560B1 Method and apparatus for controlling resource 失效
标题翻译：控制资源的方法和装置
公开(公告)号：US06477560B1
公开(公告)日：2002-11-05
申请号：US09192218
申请日：1998-11-16
申请人： Hideki Murayama , Hiroshi Yashiro , Takehisa Hayashi , Masahiro Kitano
发明人： Hideki Murayama , Hiroshi Yashiro , Takehisa Hayashi , Masahiro Kitano
IPC分类号： G06F900
CPC分类号： G06F9/5016
摘要： A control method of controlling a computer for controlling a resource connected to the computer and shared by a plurality of programs included in the computer includes the steps of storing a control information ID indicating a storage area in the main memory storing control information concerning access between a certain program and the resource in an OS space of a main memory, storing the control information ID in an adaptor connected to the main memory via a bus, and taking out the control information from the storage area included in the OS space, by using the control information ID stored in the adapter. In the case where the adapter runs short of a storage area, information that the adapter runs short of a storage area in the main memory is conveyed via the bus. By using the control information thus taken out, the resource is controlled.
摘要翻译：控制计算机的控制方法，用于控制连接到计算机并由包括在计算机中的多个程序共享的资源的计算机包括以下步骤：将指示存储区域的控制信息ID存储在主存储器中，该主存储器存储关于在特定程序和主存储器的OS空间中的资源，经由总线将控制信息ID存储在连接到主存储器的适配器中，并且通过使用该存储区域中的包含在OS空间中的存储区域中取出控制信息存储在适配器中的控制信息ID。在适配器运行时间短于存储区域的情况下，适配器在主存储器中的存储区域的运行时间短的信息经由总线传送。通过使用由此取出的控制信息，控制资源。

36. 发明授权

US6108694A Memory disk sharing method and its implementing apparatus 有权
标题翻译：内存磁盘共享方法及其实现装置
公开(公告)号：US6108694A
公开(公告)日：2000-08-22
申请号：US193852
申请日：1998-11-18
申请人： Hiroshi Yashiro , Hideki Murayama , Hirofumi Fujita , Takehisa Hayashi , Masahiro Kitano
发明人： Hiroshi Yashiro , Hideki Murayama , Hirofumi Fujita , Takehisa Hayashi , Masahiro Kitano
IPC分类号： G06F3/06 , G06F21/00 , G06F13/38 , G06F15/17
CPC分类号： G06F3/0613 , G06F21/80 , G06F3/0659 , G06F3/067
摘要： A memory disc sharing method in which a plurality of computers share a memory disc through a network, wherein a command in accordance with which the memory disc is accessed is received by a network interface apparatus, and when a requested computer to which a request of the command has been made is any of other computers, the command is transmitted to the any of other computers, and when the requested computer is a computer concerned, the command is stored in a memory disc command queue. The network interface apparatus retrieves the command from the memory disc command queue, and executes the processing of reading out/writing data from/to the memory disc in the computer concerned when a requesting computer from which a request of the command has been made is the computer concerned, and carries out the data transfer between the memory disc in the computer concerned and the requesting computer when the requesting computer is any of other computers.
摘要翻译：一种存储器盘共享方法，其中多个计算机通过网络共享存储盘，其中，由网络接口装置接收存储盘访问的命令，并且当请求的计算机命令是任何其他计算机，命令被发送到任何其他计算机，并且当所请求的计算机是有关的计算机时，该命令被存储在存储器盘命令队列中。网络接口装置从存储器盘命令队列检索命令，并且当已经从其发出了命令的请求的请求计算机时，执行从相关计算机中向存储盘读/写数据的处理并且当请求计算机是任何其他计算机时，执行有关计算机中的存储盘和请求计算机之间的数据传输。

37. 发明授权

US6011791A Multi-processor system and its network 失效
标题翻译：多处理器系统及其网络
公开(公告)号：US6011791A
公开(公告)日：2000-01-04
申请号：US747344
申请日：1996-11-12
申请人： Tetsuhiko Okada , Naoki Hamanaka , Naohiko Irie , Takehisa Hayashi , Tetsuya Mochida , Masabumi Shibata , Youichi Tanaka , Yasuhiro Ishii
发明人： Tetsuhiko Okada , Naoki Hamanaka , Naohiko Irie , Takehisa Hayashi , Tetsuya Mochida , Masabumi Shibata , Youichi Tanaka , Yasuhiro Ishii
IPC分类号： G06F15/173 , G06F13/38 , H04L12/56
CPC分类号： G06F15/17375
摘要： In a multi-processor system interconnecting processor units, memory units, and input/output units connected to input/output devices via a crossbar switch having a plurality of ports, the transmitter of each processor unit has a circuit for determining a destination of an access request in the following manner. For an access request to a main memory, the access request is transferred to all processor units and one memory unit storing the data to be accessed. For an access request to a memory mapped register of the input/output device, the access request is broadcast to all input/output units. For an access request to a memory mapped register belonging to any one of the processor units, memory units, and input/output units, the access request is broadcast to all units via the crossbar switch.
摘要翻译：在通过具有多个端口的交叉开关连接到处理器单元，存储器单元和连接到输入/输出设备的输入/输出单元的多处理器系统中，每个处理器单元的发射器具有用于确定接入的目的地的电路请求以下列方式。对于对主存储器的访问请求，访问请求被传送到存储要访问的数据的所有处理器单元和一个存储单元。对于对输入/输出设备的存储器映射寄存器的访问请求，将访问请求广播到所有输入/输出单元。对于属于处理器单元，存储器单元和输入/输出单元中的任何一个的存储器映射寄存器的访问请求，访问请求经由交叉开关广播到所有单元。

38. 发明授权

US5617424A Method of communication between network computers by dividing packet data into parts for transfer to respective regions 失效
标题翻译：网络计算机之间通过将分组数据分割成各个区域进行传送的方法
公开(公告)号：US5617424A
公开(公告)日：1997-04-01
申请号：US642666
申请日：1996-05-03
申请人： Hideki Murayama , Satoshi Yoshizawa , Hidenori Inouchi , Takeshi Aimoto , Takehisa Hayashi , Hiroshi Iwamoto
发明人： Hideki Murayama , Satoshi Yoshizawa , Hidenori Inouchi , Takeshi Aimoto , Takehisa Hayashi , Hiroshi Iwamoto
IPC分类号： G06F13/00 , G06F15/173 , H04L12/02 , H04L12/951 , H04L29/02 , H04L29/06 , H04L29/14 , H04J3/24
CPC分类号： H04L49/9042 , H04L29/06 , H04L47/10 , H04L47/32 , H04L49/3009 , H04L49/557 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9057 , H04L49/9063 , H04L63/0236 , H04L69/22 , H04L69/40
摘要： The present invention relates to a network communication method and a network system that enables received data to be transferred directly to the user data region, thereby eliminating the need to perform data copy operations. In the present invention, packets are each provided with received region assignment information (port ID) for showing the region in which the packet is to be received and/or division information for dividing the packet. The region which is to receive data contained in the packet is determined from a port table and conversion tables, and the packet data is transferred to the region directly.
摘要翻译：网络通信方法和网络系统技术领域本发明涉及一种网络通信方法和网络系统，其能够将接收的数据直接传送到用户数据区域，从而不需要进行数据复制操作。在本发明中，分组具有用于表示要接收分组的区域的接收区域分配信息（端口ID）和/或划分分组的划分信息。从端口表和转换表确定要接收包中包含的数据的区域，并且分组数据直接传送到该区域。

39. 发明授权

US5132752A Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US5132752A
公开(公告)日：1992-07-21
申请号：US658463
申请日：1991-02-22
申请人： Yasunari Umemoto , Nobuo Kotera , Kiichi Ueyanagi , Norikazu Hashimoto , Nobutoshi Matsunaga , Yasuo Wada , Shoji Shukuri , Noboru Masuda , Takehisa Hayashi , Hirotoshi Tanaka
发明人： Yasunari Umemoto , Nobuo Kotera , Kiichi Ueyanagi , Norikazu Hashimoto , Nobutoshi Matsunaga , Yasuo Wada , Shoji Shukuri , Noboru Masuda , Takehisa Hayashi , Hirotoshi Tanaka
IPC分类号： H01L29/10 , H01L29/812
CPC分类号： H01L29/1075 , H01L29/812 , Y10S257/903
摘要： A field effect transistor formed on a semi-insulator or compound semiconductor substrate comprises a first semiconductor layer forming a source region, a drain region and a channel layer, and a second semiconductor layer having a reverse conduction type to that of the first semiconductor layer. The second semiconductor layer is doped so that it will be totally depleted. Therefore, a portion of the second semiconductor layer adjacent to the substrate will remain conductive. The field effect transistor with this structure prevents the short channel effect and the soft error due to .alpha.-particles. A threshold voltage control arrangement is also provided using the feature of a control electrode coupled to the second semiconductor layer and a feedback arrangement.
摘要翻译：形成在半绝缘体或化合物半导体衬底上的场效应晶体管包括形成源极区，漏极区和沟道层的第一半导体层以及具有与第一半导体层相反的导通型的第二半导体层。第二半导体层被掺杂以使其完全耗尽。因此，与衬底相邻的第二半导体层的一部分将保持导电。具有这种结构的场效应晶体管防止短沟道效应和由于α-粒子引起的软误差。还使用耦合到第二半导体层的控制电极的特征和反馈装置来提供阈值电压控制装置。

40. 发明授权

US4803527A Semiconductor integrated circuit device having semi-insulator substrate 失效
标题翻译：具有半绝缘体衬底的半导体集成电路器件
公开(公告)号：US4803527A
公开(公告)日：1989-02-07
申请号：US876466
申请日：1986-06-20
申请人： Yasushi Hatta , Kazumichi Mitsusada , Hirotoshi Tanaka , Takehisa Hayashi
发明人： Yasushi Hatta , Kazumichi Mitsusada , Hirotoshi Tanaka , Takehisa Hayashi
IPC分类号： H01L29/812 , H01L21/338 , H01L21/8232 , H01L27/02 , H01L27/06 , H01L29/90 , H01L29/78
CPC分类号： H01L27/0605 , H01L27/0251
摘要： Disclosed is a semiconductor integrated circuit device forming MESFETs by use of a semi-insulator GaAs substrate which prevents destruction of an electrostatic destruction protect circuit and a Schottky junction of an internal circuit by causing a part of electrostatic energy, which is applied to external terminals, to flow from a semiconductor region connected to the external terminals into another semiconductor region which is formed in the vicinity of the semiconductor region described above and to which a predetermined fixed potential is applied.
摘要翻译：公开了一种通过使用半绝缘体GaAs衬底形成MESFET的半导体集成电路器件，其通过施加施加到外部端子的一部分静电能来防止静电破坏保护电路和内部电路的肖特基结的破坏，从连接到外部端子的半导体区域流到形成在上述半导体区域附近并且施加预定固定电位的另一个半导体区域。

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