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31. 发明授权

US07078781B2 High-breakdown-voltage semiconductor device 失效
标题翻译：高击穿电压半导体器件
公开(公告)号：US07078781B2
公开(公告)日：2006-07-18
申请号：US10942000
申请日：2004-09-16
申请人： Tetsuo Hatakeyama , Takashi Shinohe
发明人： Tetsuo Hatakeyama , Takashi Shinohe
IPC分类号： H01L27/095 , H01L29/861 , H01L29/00
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0661 , H01L29/0692 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/7392 , H01L29/7395 , H01L29/7722 , H01L29/7802 , H01L29/872
摘要： A high-breakdown-voltage semiconductor device includes a high-resistance semiconductor layer, first trenches formed on the surface thereof in a longitudinal plane shape and in parallel, a Schottky electrode formed thereon and sandwiched between adjacent first trenches, a first region having an opposite conductivity type to the semiconductor layer continuously disposed in a sidewall and a bottom of each of the first trenches, a sidewall insulating film disposed on the sidewall, a second region of the opposite conductivity type disposed in the bottom of each of the first trenches, a third region disposed on the opposite surface of the semiconductor layer, a control electrode filling each of the first trenches in contact with the second region and connected to the Schottky electrode, a backside electrode formed on the third region, wherein second trenches communicate with the first trenches at both ends of longitudinal sides thereof, and the Schottky electrode is surrounded by the first and second trenches.
摘要翻译：高耐压半导体器件包括：高电阻半导体层，在其表面上形成纵向平面形状并且平行的第一沟槽，形成在其上并夹在相邻第一沟槽之间的肖特基电极，第一区域具有相反的导电类型连续地设置在每个第一沟槽的侧壁和底部中的半导体层，设置在侧壁上的侧壁绝缘膜，设置在每个第一沟槽的底部的相反导电类型的第二区域，第三区域，设置在所述半导体层的相对表面上;控制电极，填充与所述第二区域接触并连接到所述肖特基电极的每个所述第一沟槽;形成在所述第三区域上的背面电极，其中，所述第二沟槽与所述第一沟槽连通，沟槽在其纵向侧的两端，肖特基电极被第一个a包围第二个沟渠。

32. 发明申请

US20060011973A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060011973A1
公开(公告)日：2006-01-19
申请号：US11230492
申请日：2005-09-21
申请人： Makoto Mizukami , Takashi Shinohe
发明人： Makoto Mizukami , Takashi Shinohe
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0634 , H01L29/086 , H01L29/0878 , H01L29/66666 , H01L29/7397 , H01L29/7811 , H01L29/7828 , H01L29/8083
摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, a lightly-doped semiconductor layer of the first conductivity type formed on the first major surface of the substrate, a first semiconductor region of the first conductivity type formed on an island-shaped region on the lightly-doped semiconductor layer, a first electrode surrounding the first semiconductor region and buried at a deeper position than the first semiconductor region, a second semiconductor region formed on the second major surface of the substrate, a buried field relaxation layer formed in the lightly-doped semiconductor layer between a bottom surface of the first electrode and the second semiconductor region, including a first field relaxation layer of the first conductivity type and second field relaxation layers of the second conductivity type formed at two ends of the first field relaxation layer, second and third electrodes formed on the first and second semiconductor regions, respectively.
摘要翻译：半导体器件包括第一导电类型的半导体衬底，形成在衬底的第一主表面上的第一导电类型的轻掺杂半导体层，形成在岛状区域上的第一导电类型的第一半导体区域在所述轻掺杂半导体层上，包围所述第一半导体区并且埋藏在比所述第一半导体区更深的位置的第一电极，形成在所述衬底的所述第二主表面上的第二半导体区，在第一电极的底表面和第二半导体区域之间的轻掺杂半导体层，包括第一导电类型的第一场弛豫层和形成在第一场弛豫层两端的第二导电类型的第二场弛豫层，形成在第一和第二半导体区域上的第二和第三电极，分别。

33. 发明授权

US06969887B2 Semiconductor device 失效
公开(公告)号：US06969887B2
公开(公告)日：2005-11-29
申请号：US11038043
申请日：2005-01-21
申请人： Makoto Mizukami , Takashi Shinohe
发明人： Makoto Mizukami , Takashi Shinohe
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06 , H01L29/08 , H01L29/24 , H01L29/739 , H01L29/808 , H01L29/94 , H01L31/062
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0634 , H01L29/086 , H01L29/0878 , H01L29/66666 , H01L29/7397 , H01L29/7811 , H01L29/7828 , H01L29/8083
摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, a lightly-doped semiconductor layer of the first conductivity type formed on the first major surface of the substrate, a first semiconductor region of the first conductivity type formed on an island-shaped region on the lightly-doped semiconductor layer, a first electrode surrounding the first semiconductor region and buried at a deeper position than the first semiconductor region, a second semiconductor region formed on the second major surface of the substrate, a buried field relaxation layer formed in the lightly-doped semiconductor layer between a bottom surface of the first electrode and the second semiconductor region, including a first field relaxation layer of the first conductivity type and second field relaxation layers of the second conductivity type formed at two ends of the first field relaxation layer, second and third electrodes formed on the first and second semiconductor regions, respectively.

34. 发明申请

US20050161732A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20050161732A1
公开(公告)日：2005-07-28
申请号：US11038043
申请日：2005-01-21
申请人： Makoto Mizukami , Takashi Shinohe
发明人： Makoto Mizukami , Takashi Shinohe
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06 , H01L29/08 , H01L29/24 , H01L29/739 , H01L29/808 , H01L29/94 , H01L31/062
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0634 , H01L29/086 , H01L29/0878 , H01L29/66666 , H01L29/7397 , H01L29/7811 , H01L29/7828 , H01L29/8083
摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, a lightly-doped semiconductor layer of the first conductivity type formed on the first major surface of the substrate, a first semiconductor region of the first conductivity type formed on an island-shaped region on the lightly-doped semiconductor layer, a first electrode surrounding the first semiconductor region and buried at a deeper position than the first semiconductor region, a second semiconductor region formed on the second major surface of the substrate, a buried field relaxation layer formed in the lightly-doped semiconductor layer between a bottom surface of the first electrode and the second semiconductor region, including a first field relaxation layer of the first conductivity type and second field relaxation layers of the second conductivity type formed at two ends of the first field relaxation layer, second and third electrodes formed on the first and second semiconductor regions, respectively.
摘要翻译：半导体器件包括第一导电类型的半导体衬底，形成在衬底的第一主表面上的第一导电类型的轻掺杂半导体层，形成在岛状区域上的第一导电类型的第一半导体区域在所述轻掺杂半导体层上，包围所述第一半导体区并且埋藏在比所述第一半导体区更深的位置的第一电极，形成在所述衬底的所述第二主表面上的第二半导体区，在第一电极的底表面和第二半导体区域之间的轻掺杂半导体层，包括第一导电类型的第一场弛豫层和形成在第一场弛豫层两端的第二导电类型的第二场弛豫层，形成在第一和第二半导体区域上的第二和第三电极，分别。

35. 发明授权

US06855970B2 High-breakdown-voltage semiconductor device 失效
公开(公告)号：US06855970B2
公开(公告)日：2005-02-15
申请号：US10393914
申请日：2003-03-24
申请人： Tetsuo Hatakeyama , Takashi Shinohe
发明人： Tetsuo Hatakeyama , Takashi Shinohe
IPC分类号： H01L29/06 , H01L29/10 , H01L29/24 , H01L29/739 , H01L29/772 , H01L29/78 , H01L29/80 , H01L31/112 , H01L29/94 , H01L31/0312
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0661 , H01L29/0692 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/7392 , H01L29/7395 , H01L29/7722 , H01L29/7802 , H01L29/872
摘要： A high-breakdown-voltage semiconductor device comprises a high-resistance semiconductor layer, trenches formed on the surface thereof in a longitudinal plane shape and in parallel, first regions formed on the semiconductor layer to be sandwiched between adjacent ones of the trenches and having an impurity concentration higher than that of the semiconductor layer, a second region having opposite conductivity to the first regions and continuously disposed in a trench sidewall and bottom portion, a sidewall insulating film disposed on the second region of the trench sidewall, a third region disposed on the second region of the trench bottom portion and having the same conductivity as and the higher impurity concentration than the second region, a fourth region disposed on the back surface of the semiconductor layer, a first electrode formed on each first region, a second electrode connected to the third region, and a third electrode formed on the fourth region.

36. 发明授权

US06236069B1 Insulated-gate thyristor 失效
标题翻译：绝缘栅晶闸管
公开(公告)号：US06236069B1
公开(公告)日：2001-05-22
申请号：US09102360
申请日：1998-06-23
申请人： Takashi Shinohe , Kazuya Nakayama , Minami Takeuchi , Masakazu Yamaguchi , Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa
发明人： Takashi Shinohe , Kazuya Nakayama , Minami Takeuchi , Masakazu Yamaguchi , Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa
IPC分类号： H01L2974
CPC分类号： H01L29/7455 , H01L29/42308 , H01L29/749
摘要： Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.
摘要翻译：本文公开了一种绝缘栅极晶闸管，其包括第一导电类型的基极层，具有第一和第二主表面，形成在基底层的第一主表面中的第一导电类型的第一主电极区域，第二导电类型的第二主表面形成在基底层的第二主表面的第二导电类型的主电极区域，至少一对从第一主电极区域延伸到基底层中并且彼此相对并间隔开预定的凹槽距离，形成在沟槽内的绝缘栅电极，以及用于从基层释放第二导电类型的载流子的关断绝缘栅晶体管结构。

37. 发明授权

US5464994A Insulated-gate thyristor 失效
标题翻译：绝缘栅晶闸管
公开(公告)号：US5464994A
公开(公告)日：1995-11-07
申请号：US291754
申请日：1994-08-16
申请人： Takashi Shinohe , Kazuya Nakayama , Minami Takeuchi , Masakazu Yamaguchi , Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa
发明人： Takashi Shinohe , Kazuya Nakayama , Minami Takeuchi , Masakazu Yamaguchi , Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa
IPC分类号： H01L29/423 , H01L29/745 , H01L29/749 , H01L29/74
CPC分类号： H01L29/7455 , H01L29/42308 , H01L29/749
摘要： Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.
摘要翻译：本文公开了一种绝缘栅极晶闸管，其包括第一导电类型的基极层，具有第一和第二主表面，形成在基底层的第一主表面中的第一导电类型的第一主电极区域，第二导电类型的第二主表面形成在基底层的第二主表面的第二导电类型的主电极区域，至少一对从第一主电极区域延伸到基底层中并且彼此相对并间隔开预定的凹槽距离，形成在沟槽内的绝缘栅电极，以及用于从基层释放第二导电类型的载流子的关断绝缘栅晶体管结构。

38. 发明授权

US4717940A MIS controlled gate turn-off thyristor 失效
标题翻译： MIS控制栅极关断晶闸管
公开(公告)号：US4717940A
公开(公告)日：1988-01-05
申请号：US14608
申请日：1987-02-13
申请人： Takashi Shinohe , Katsuhiko Takigami , Hiromichi Ohashi , Akio Nakagawa
发明人： Takashi Shinohe , Katsuhiko Takigami , Hiromichi Ohashi , Akio Nakagawa
IPC分类号： H01L29/08 , H01L29/10 , H01L29/745 , H01L29/74
CPC分类号： H01L29/0839 , H01L29/102 , H01L29/7455
摘要： An MIS controlled gate turn-off thyristor includes a pnpn structure comprised of a first emitter layer, a first base layer, a second base layer and a second emitter layer, and a turn-off MIS transistor for short-circuiting the second base layer to the second emitter layer. A low impurity concentration layer is formed on the second base layer and the second emitter layer is so formed that it extends, through the low impurity concentration layer, into the second base layer. The MIS transistor is formed on the surface portion of said low impurity concentration layer.
摘要翻译： MIS控制栅极截止晶闸管包括由第一发射极层，第一基极层，第二基极层和第二发射极层构成的pnpn结构，以及用于将第二基极层短路的关断MIS晶体管第二发射极层。在第二基极层上形成低杂质浓度层，第二发射极层形成为通过低杂质浓度层延伸到第二基极层。 MIS晶体管形成在所述低杂质浓度层的表面部分上。

39. 发明授权

US09041008B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09041008B2
公开(公告)日：2015-05-26
申请号：US13411789
申请日：2012-03-05
申请人： Yukio Nakabayashi , Takashi Shinohe , Atsuko Yamashita
发明人： Yukio Nakabayashi , Takashi Shinohe , Atsuko Yamashita
IPC分类号： H01L29/78 , H01L29/66 , H01L21/04
CPC分类号： H01L29/66068 , H01L21/046 , H01L21/0475 , H01L29/7827
摘要： A semiconductor device of an embodiment includes a first conductive type silicon carbide substrate having first and second main surfaces, a first conductive type silicon carbide layer formed on the first main surface, a second conductive type first silicon carbide region formed in the silicon carbide layer, and a first conductive type second silicon carbide region formed in the first silicon carbide region. The device includes a trench penetrating through the first and second silicon carbide regions, and a second conductive type third silicon carbide region formed on a bottom and a side surface of the trench. The third silicon carbide region is in contact with the first silicon carbide region, and is formed between the trench and the silicon carbide layer. In addition, the device includes a gate insulating film formed in the trench, a gate electrode, a first electrode, and a second electrode.
摘要翻译：实施例的半导体器件包括具有第一和第二主表面的第一导电型碳化硅衬底，形成在第一主表面上的第一导电型碳化硅层，形成在碳化硅层中的第二导电型第一碳化硅区，以及形成在第一碳化硅区域中的第一导电类型的第二碳化硅区域。该器件包括穿过第一和第二碳化硅区域的沟槽以及形成在沟槽的底部和侧表面上的第二导电类型的第三碳化硅区域。第三碳化硅区域与第一碳化硅区域接触，并且形成在沟槽和碳化硅层之间。此外，该器件包括形成在沟槽中的栅极绝缘膜，栅电极，第一电极和第二电极。

40. 发明授权

US08841741B2 High breakdown voltage semiconductor rectifier 有权
标题翻译：高耐压半导体整流器
公开(公告)号：US08841741B2
公开(公告)日：2014-09-23
申请号：US13226883
申请日：2011-09-07
申请人： Masamu Kamaga , Makoto Mizukami , Takashi Shinohe
发明人： Masamu Kamaga , Makoto Mizukami , Takashi Shinohe
IPC分类号： H01L31/102 , H01L29/66 , H01L29/861 , H01L29/06
CPC分类号： H01L29/0615 , H01L29/0692 , H01L29/6609 , H01L29/8613
摘要： A high breakdown voltage diode of the present embodiment includes a first conductive semiconductor substrate, a drift layer formed on the first conductive semiconductor substrate and formed of a first conductive semiconductor, a buffer layer formed on the drift layer and formed of a second conductive semiconductor, a second conductive high concentration semiconductor region formed at an upper portion of the buffer layer, a mesa termination unit formed on an end region of a semiconductor apparatus to relax an electric field of the end region when reverse bias is applied between the semiconductor substrate and the buffer layer, and an electric field relaxation region formed at the mesa termination unit and formed of a second conductive semiconductor.A breakdown voltage of a high breakdown voltage diode, in which a pn junction is provided to a semiconductor layer, is increased, and a process yield is improved.
摘要翻译：本实施例的高击穿电压二极管包括第一导电半导体衬底，形成在第一导电半导体衬底上并由第一导电半导体形成的漂移层，形成在漂移层上并由第二导电半导体形成的缓冲层，形成在缓冲层的上部的第二导电性高浓度半导体区域，形成在半导体装置的端部区域上的台面终端单元，用于在半导体基板与半导体基板之间施加反向偏压时使末端区域的电场松弛缓冲层和形成在台面终端单元处并由第二导电半导体形成的电场弛豫区域。提供了将pn结提供给半导体层的高击穿电压二极管的击穿电压，并且提高了工艺成品率。

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