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31. 发明授权

US07667682B2 Display 有权
标题翻译：显示
公开(公告)号：US07667682B2
公开(公告)日：2010-02-23
申请号：US11285212
申请日：2005-11-23
申请人： Michiru Senda , Hiroyuki Horibata
发明人： Michiru Senda , Hiroyuki Horibata
IPC分类号： G09G3/34 , G11C19/00
CPC分类号： G09G3/3688 , G09G3/3208 , G09G3/3266 , G09G3/3275 , G09G3/3677 , G09G2330/021 , G11C19/184 , G11C19/28
摘要： A display having a shift register circuit capable of suppressing increase of power consumption is provided. This display comprises a shift register circuit including a shift register circuit portion including a first circuit portion having a second transistor turned on in response to a first signal and a second circuit portion having a sixth transistor turned on in response to a second signal providing an ON-state period not overlapping with an ON-state period of the second transistor and an input signal switching circuit portion for switching the first and second signals supplied to the second and sixth transistors respectively.
摘要翻译：提供了具有能够抑制功耗增加的移位寄存器电路的显示器。该显示器包括移位寄存器电路，该移位寄存器电路包括移位寄存器电路部分，该移位寄存器电路部分包括响应于第一信号而导通的第二晶体管的第一电路部分和响应于第二信号提供ON的第六晶体管导通的第二电路部分 - 与第二晶体管的导通状态周期不重叠的状态周期，以及用于分别切换提供给第二和第六晶体管的第一和第二信号的输入信号切换电路部分。

32. 发明申请

US20090243678A1 Delay locked-loop circuit and display apparatus 有权
标题翻译：延迟锁定环电路和显示设备
公开(公告)号：US20090243678A1
公开(公告)日：2009-10-01
申请号：US12379727
申请日：2009-02-27
申请人： Hiroshi Mizuhashi , Michiru Senda , Gen Koide
发明人： Hiroshi Mizuhashi , Michiru Senda , Gen Koide
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0818 , H03L7/093
摘要： A delay locked-loop circuit includes: a phase comparator detecting a phase difference between an external clock and an internal clock; an up/down counter controlling a delay time in accordance with an output signal from the phase comparator; and a delay line including plural unit delay circuits corresponding to plural bits of a signal output from the up/down counter in order to control the delay of the external clock to conform the external clock to the internal clock, and in which the unit delay circuits controlled by the output from a same bit in the output from the up/down counter are not connected adjacently to each other in the connection of the plural unit delay circuits in series.
摘要翻译：延迟锁定环电路包括：检测外部时钟和内部时钟之间的相位差的相位比较器; 上/下计数器根据来自相位比较器的输出信号控制延迟时间; 以及延迟线，包括对应于从上/下计数器输出的信号的多个比特的多个单位延迟电路，以便控制外部时钟的延迟以使外部时钟符合内部时钟，并且其中单位延迟电路在多个单元延迟电路的串联连接中，由来自递增/递减计数器的输出中相同位的输出控制不相互连接。

33. 发明申请

US20090096906A1 CLOCK SIGNAL GENERATION CIRCUIT, DISPLAY PANEL MODULE, IMAGE SENSOR APPARATUS, AND ELECTRONIC APPARATUS 有权
标题翻译：时钟信号发生电路，显示面板模块，图像传感器装置和电子设备
公开(公告)号：US20090096906A1
公开(公告)日：2009-04-16
申请号：US12248992
申请日：2008-10-10
申请人： Michiru Senda , Hiroshi Mizuhashi , Gen Koide
发明人： Michiru Senda , Hiroshi Mizuhashi , Gen Koide
IPC分类号： H04N5/335 , G09G5/00 , H03L7/06
CPC分类号： H04N5/335 , G09G3/20 , G09G5/008 , G09G2300/0408 , G09G2310/08 , H03L7/0812 , H03L7/0814 , H04N5/3765
摘要： A clock signal generation circuit of a delay locked loop type includes a delay line configured to delay a first clock signal to generate a second clock signal; a delay amount controller configured to change the amount of delay in the delay line in such a manner that a phase of the second clock signal is in synchronization with a phase of the first clock signal; a pseudo-lock detection section configured to detect a pseudo-locked state of the first clock signal and the second clock signal; and a pseudo-locked state release section configured to change the amount of delay in the delay line in a case that the pseudo-locked state is detected.
摘要翻译：延迟锁定环路的时钟信号产生电路包括：延迟线，被配置为延迟第一时钟信号以产生第二时钟信号; 延迟量控制器，被配置为以所述第二时钟信号的相位与所述第一时钟信号的相位同步的方式改变所述延迟线中的延迟量; 伪锁定检测部，被配置为检测第一时钟信号和第二时钟信号的伪锁定状态; 以及伪锁定状态释放部，被配置为在检测到伪锁定状态的情况下改变延迟线的延迟量。

34. 发明授权

US07221351B2 Display device 有权
标题翻译：显示设备
公开(公告)号：US07221351B2
公开(公告)日：2007-05-22
申请号：US10444068
申请日：2003-05-23
申请人： Michiru Senda
发明人： Michiru Senda
IPC分类号： G09G3/30 , G09G3/36
CPC分类号： G09G3/3233 , G09G3/3283 , G09G3/3291 , G09G2300/0828 , G09G2300/0852 , G09G2300/0861
摘要： A current generating circuit, which generates a driving current weighed corresponding to a digital image signal, is disposed for each pixel in the display device of this invention. The driving current is supplied to an organic El element. The current generating circuit has D/A conversion function, which is capable of converting the digital image signal into the weighed driving current, enabling the gradation display corresponding to the digital image signal.
摘要翻译：为本发明的显示装置中的每个像素设置产生对应于数字图像信号加权的驱动电流的电流产生电路。驱动电流被提供给有机EL元件。电流产生电路具有D / A转换功能，其能够将数字图像信号转换成称重的驱动电流，使得能够对应于数字图像信号的灰度显示。

35. 发明申请

US20070040821A1 Amplifier circuit and display device 有权
标题翻译：放大器电路和显示装置
公开(公告)号：US20070040821A1
公开(公告)日：2007-02-22
申请号：US11504142
申请日：2006-08-15
申请人： Michiru Senda , Hiroyuki Horibata
发明人： Michiru Senda , Hiroyuki Horibata
IPC分类号： G09G5/00
CPC分类号： G09G3/3685 , G09G3/3614 , G09G3/3696 , G09G2310/0251 , G09G2310/0256 , G09G2310/027 , G09G2310/0291
摘要： In a buffer amplifier which receives an input signal on a positive input terminal, has an output terminal connected to a negative input terminal, and outputs a stabilized output signal, a switch for connecting the positive input terminal and the output terminal is provided. By switching the switch ON, the output of the buffer amplifier is set close to the input.
摘要翻译：在接收正输入端子上的输入信号的缓冲放大器中，具有连接到负输入端子的输出端子，并且输出稳定的输出信号，提供用于连接正输入端子和输出端子的开关。通过将开关切换到ON，缓冲放大器的输出设置为接近输入。

36. 发明申请

US20060221043A1 Display 有权
标题翻译：显示
公开(公告)号：US20060221043A1
公开(公告)日：2006-10-05
申请号：US11387792
申请日：2006-03-24
申请人： Hiroyuki Horibata , Michiru Senda
发明人： Hiroyuki Horibata , Michiru Senda
IPC分类号： G09G3/36
CPC分类号： G11C19/184 , G11C19/00 , G11C19/28
摘要： A display capable of inhibiting a logic composition circuit from outputting a signal to a gate line or a drain line at unintentional timing is obtained. This display comprises a shift register circuit including a logic composition circuit portion constituted of a plurality of first conductive type transistors turned on with a first voltage supply source for receiving a first shift signal and a second shift signal and outputting a shift output signal by logically compositing the first shift signal and the second shift signal with each other. At least either a first shift register circuit portion or a second shift register circuit portion includes a reset transistor for resetting the voltage supply source of a node outputting the first shift signal or the second shift signal to a second voltage supply source not turning on the transistors of the logic composition circuit portion in response to a prescribed drive signal.
摘要翻译：获得能够禁止逻辑合成电路在无意定时将信号输出到栅极线或漏极线的显示器。该显示器包括移位寄存器电路，该移位寄存器电路包括由多个第一导电型晶体管构成的逻辑合成电路部分，该多个第一导电型晶体管用于接收第一移位信号的第一电压源和第二移位信号，并通过逻辑合成输出移位输出信号第一移位信号和第二移位信号。至少第一移位寄存器电路部分或第二移位寄存器电路部分至少包括复位晶体管，用于将输出第一移位信号或第二移位信号的节点的电压源转换为不导通晶体管的第二电压源逻辑合成电路部分响应规定的驱动信号。

37. 发明申请

US20050140414A1 Delay circuit and display including the same 审中-公开
标题翻译：延迟电路和显示包括相同
公开(公告)号：US20050140414A1
公开(公告)日：2005-06-30
申请号：US11016800
申请日：2004-12-21
申请人： Michiru Senda
发明人： Michiru Senda
IPC分类号： G09G3/20 , G09G3/36 , H03K5/00 , H03K5/13 , H03K5/153 , H03K17/28 , H03K17/687 , H03K19/096
CPC分类号： G09G3/3688 , G09G2310/0294 , H03K5/133 , H03K2005/00156
摘要： A delay circuit capable of suppressing reduction of the yield in manufacturing is provided. This delay circuit comprises an inverter circuit having a prescribed logical threshold voltage and a first transistor connected in parallel to the inverter circuit. The first transistor is turned on when an input signal in and an output signal from the inverter circuit are at a first voltage and a second voltage respectively and further turned on for at least a partial period in a period when the input signal in the inverter circuit reaches a voltage corresponding to the logical threshold voltage of the inverter circuit from the first voltage for changing from the first voltage to the second voltage thereby functioning substantially as a capacitor.
摘要翻译：提供一种能够抑制制造成品率降低的延迟电路。该延迟电路包括具有规定的逻辑阈值电压的反相器电路和与反相器电路并联连接的第一晶体管。当反相器电路中的输入信号和来自反相器电路的输出信号分别处于第一电压和第二电压时，第一晶体管导通，并且在逆变器电路中的输入信号的周期内进一步导通至少部分周期从用于从第一电压变为第二电压的第一电压达到与逆变器电路的逻辑阈值电压相对应的电压，从而基本上作为电容器起作用。

38. 发明授权

US08618492B2 Radiation image pickup device 有权
标题翻译：辐射摄像装置
公开(公告)号：US08618492B2
公开(公告)日：2013-12-31
申请号：US13137209
申请日：2011-07-28
申请人： Michiru Senda , Tsutomu Tanaka , Tsutomu Harada
发明人： Michiru Senda , Tsutomu Tanaka , Tsutomu Harada
IPC分类号： G01T1/24
CPC分类号： G01T1/247 , G01T1/208 , H04N5/32 , H04N5/3651
摘要： A radiation image pickup device includes: an image pickup section having a plurality of pixels and generating an electric signal according to incident radiation, the plurality of pixels each including a photoelectric conversion element and one or a plurality of transistors of a predetermined amplifier circuit; and a correction section subjecting signal data of the electric signal obtained in the image pickup section to predetermined correction process. The correction section makes a comparison between measurement data obtained by measuring an input-output characteristic of the amplifier circuit in each of the plurality of pixels and initial data on the input-output characteristic, and performs the correction process by the pixel individually, by using a result of the comparison.
摘要翻译：一种放射线图像拾取装置，包括：具有多个像素并根据入射辐射产生电信号的图像拾取部分，所述多个像素分别包括光电转换元件和预定放大器电路的一个或多个晶体管; 以及校正部，对在图像拾取部中获得的电信号的信号数据进行预定的校正处理。校正部分比较通过测量多个像素中的每一个中的放大器电路的输入 - 输出特性和关于输入 - 输出特性的初始数据而获得的测量数据，并且通过使用单独的像素执行校正处理比较的结果。

39. 发明授权

US08593442B2 Sensor device, method of driving sensor element, display device with input function and electronic apparatus 有权
标题翻译：传感器装置，驱动传感器元件的方法，具有输入功能的显示装置和电子设备
公开(公告)号：US08593442B2
公开(公告)日：2013-11-26
申请号：US12941276
申请日：2010-11-08
申请人： Michiru Senda , Makoto Takatoku , Tsutomu Harada
发明人： Michiru Senda , Makoto Takatoku , Tsutomu Harada
IPC分类号： G09G5/00
CPC分类号： G06F3/0412 , G06F3/0418 , G06F3/042
摘要： Techniques are described for detecting and compensating for characteristic changes of a photoelectric conversion element, such as changes related to the temperature of the photoelectric conversion element. A display device that includes an I/O display panel and a light-receiving drive circuit is disclosed. The I/O display panel includes a plurality of display pixels; and a plurality of photoelectric conversion elements including a first photoelectric conversion element that substantially is shielded from light and a second photoelectric conversion element that is exposed to light. The light-receiving drive circuit receives a first detection signal from the first photoelectric conversion element and resets the second photoelectric conversion element based on the first detection signal.
摘要翻译：描述了用于检测和补偿光电转换元件的特性变化的技术，例如与光电转换元件的温度相关的变化。公开了一种包括I / O显示面板和光接收驱动电路的显示装置。 I / O显示面板包括多个显示像素; 以及多个光电转换元件，包括基本上被遮光的第一光电转换元件和暴露于光的第二光电转换元件。光接收驱动电路接收来自第一光电转换元件的第一检测信号，并且基于第一检测信号复位第二光电转换元件。

40. 发明授权

US08471802B2 Liquid crystal display 有权
标题翻译：液晶显示器
公开(公告)号：US08471802B2
公开(公告)日：2013-06-25
申请号：US11929346
申请日：2007-10-30
申请人： Michiru Senda , Ryoichi Yokoyama
发明人： Michiru Senda , Ryoichi Yokoyama
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G09G3/3614 , G09G2300/0876 , G09G2310/061 , G09G2310/08 , G09G2320/0261 , G09G2330/021
摘要： A small or middle-sized liquid crystal display employing a black insertion driving method overcomes the after-image or blurring of a moving picture by shifting the level of a voltage applied to a storage capacitor line within a predetermined period corresponding to about 20% to about 80% that lasts after image signals are applied to pixels until the next image signals are applied to the pixels by using two types of voltages that shift pixel voltages into a black display potential.
摘要翻译：采用黑色插入驱动方法的小型或中型液晶显示器通过将施加到辅助电容线的电压的电平移动到对应于大约20％的预定时间段内，克服了运动图像的后图像或模糊将图像信号施加到像素后持续80％，直到通过使用将像素电压移位成黑色显示电位的两种类型的电压将下一个图像信号施加到像素。

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