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31. 发明授权

US07817457B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US07817457B2
公开(公告)日：2010-10-19
申请号：US12132972
申请日：2008-06-04
申请人： Naoya Tokiwa , Kazushige Kanda , Toshiaki Edahiro , Koji Hosono , Takuya Futatsuyama , Shigeo Ohshima
发明人： Naoya Tokiwa , Kazushige Kanda , Toshiaki Edahiro , Koji Hosono , Takuya Futatsuyama , Shigeo Ohshima
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0097 , G11C2013/0092 , G11C2213/32 , G11C2213/72
摘要： According to one embodiment, a nonvolatile memory device includes: a memory cell array including memory cells each having a variable resistance element for nonvolatilely storing data identified by an electrically rewritable resistance value; a first data latch storing write and erase data to be written on a given group of memory cells of the memory cell array for a write and erase operation; and a second data latch storing reference data for performing a compensation operation of the given group to compensate write and erase disturbance accompanied by the write or erase operation.
摘要翻译：根据一个实施例，非易失性存储器件包括：存储单元阵列，其包括各自具有用于非易失性地存储由电可重写电阻值识别的数据的可变电阻元件的存储单元; 存储要写入存储单元阵列的给定组的存储单元的用于写入和擦除操作的写入和擦除数据的第一数据锁存器; 以及第二数据锁存器，存储用于执行给定组的补偿操作以补偿伴随着写入或擦除操作的写入和擦除干扰的参考数据。

32. 发明申请

US20090052227A1 NON-VOLATILE MEMORY DEVICE AND METHOD FOR WRITING DATA THERETO 有权
标题翻译：非易失性存储器件及其数据写入方法
公开(公告)号：US20090052227A1
公开(公告)日：2009-02-26
申请号：US12118064
申请日：2008-05-09
申请人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
发明人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
IPC分类号： G11C11/00 , G11C7/00 , G11C7/06
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/32 , G11C2213/72
摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.
摘要翻译：本发明提供一种将数据写入非易失性存储器件的方法，该非易失性存储器件具有彼此相交的第一布线和第二布线以及布置在其间的每个交叉处的存储单元，每个存储单元具有可变电阻元件和整流元件系列。根据该方法，在所选择的第一布线中升高之前，将第二布线充电至不小于整流元件阈值的一定电压。然后，将所选择的第一布线充电到写入或擦除所需的电压，之后放电所选择的第二布线。

33. 发明授权

US07209388B2 Semiconductor memory device with MOS transistors each having floating gate and control gate 失效
标题翻译：具有MOS晶体管的半导体存储器件分别具有浮动栅极和控制栅极
公开(公告)号：US07209388B2
公开(公告)日：2007-04-24
申请号：US11169633
申请日：2005-06-30
申请人： Kazushige Kanda
发明人： Kazushige Kanda
IPC分类号： G11C5/14
CPC分类号： G11C29/846 , G11C8/18 , G11C16/0433 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C29/808
摘要： A semiconductor memory device includes a row address transition detector. The semiconductor memory device remedies a fault by replacing a column in a memory cell array with a redundancy bit line. The row address transition detector detects a change in a row address signal for selecting the row direction of the memory cell array. Only when a change in the row address signal is detected by the row address transition detector, the redundancy bit line is sensed.
摘要翻译：半导体存储器件包括行地址转换检测器。半导体存储器件通过用冗余位线替换存储单元阵列中的列来补救故障。行地址转换检测器检测用于选择存储单元阵列的行方向的行地址信号的变化。只有当行地址转换检测器检测到行地址信号的变化时，才检测冗余位线。

34. 发明申请

US20120235218A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120235218A1
公开(公告)日：2012-09-20
申请号：US13235397
申请日：2011-09-18
申请人： Hiroyuki KUTSUKAKE , Noboru Shibata , Kazushige Kanda , Masayuki Ichige
发明人： Hiroyuki KUTSUKAKE , Noboru Shibata , Kazushige Kanda , Masayuki Ichige
IPC分类号： H01L27/115 , H01L21/8239
CPC分类号： H01L27/11529 , G11C11/5621 , G11C16/0483 , H01L21/823807 , H01L21/823892 , H01L27/11546
摘要： According to one embodiment, a device includes a semiconductor substrate, a first region including a first well which is formed in substrate, a second well which is formed in substrate and on first well, and a memory cell which is formed on second well, and a second region including a third well which is formed in substrate, and a first transistor which is formed on third well. The device includes a third region including a second transistor which is formed on semiconductor substrate, and a fourth region including a fourth well which is formed in semiconductor substrate, a fifth well which is formed in substrate and on fourth well, and a third transistor which is formed on fifth well. Bottoms of first well and fourth well are lower than a bottom of third well, and bottom of third well is lower than bottoms of second well and fifth well.
摘要翻译：根据一个实施例，一种器件包括半导体衬底，第一区域，包括形成在衬底中的第一阱，形成在衬底中的第二阱和第一阱，以及形成在第二阱上的存储单元，以及包括形成在衬底中的第三阱的第二区域和形成在第三阱上的第一晶体管。该器件包括第三区域，该第三区域包括形成在半导体衬底上的第二晶体管，以及第四区域，包括形成在半导体衬底中的第四阱，形成在衬底中的第五阱和第四阱，以及第三晶体管，形成在第五井。第一井和第四井的底部低于第三井的底部，第三井的底部低于第二井和第五井的底部。

35. 发明申请

US20120079330A1 TEST DEVICE AND TEST METHOD FOR RESISTIVE RANDOM ACCESS MEMORY AND RESISTIVE RANDOM ACCESS MEMORY DEVICE 有权
标题翻译：电阻随机访问存储器和电阻随机访问存储器件的测试装置和测试方法
公开(公告)号：US20120079330A1
公开(公告)日：2012-03-29
申请号：US13238479
申请日：2011-09-21
申请人： Kazuaki KAWAGUCHI , Kazushige Kanda
发明人： Kazuaki KAWAGUCHI , Kazushige Kanda
IPC分类号： G11C29/08 , G06F11/273
CPC分类号： G11C29/56 , G11C11/16 , G11C13/00 , G11C29/50012 , G11C29/56012
摘要： According to the embodiments, a first write enable signal that changes with a constant period and a second write enable signal that changes at a time portion in which a limit time between activation/deactivation control of word lines and activation/deactivation control of bit lines is checked are input, a plurality of core control signals in which a time interval with which the core control signals change is locally shorter than a period of the first write enable signal based on the first write enable signal and the second write enable signal that are input is generated, and an operation verification of the resistive random access memory is performed by using the generated core control signals, whereby a cycle time in an arbitrary test cycle is locally and arbitrary adjusted.
摘要翻译：根据实施例，在恒定周期改变的第一写入使能信号和在字线的激活/停止控制和位线的激活/去激活控制之间的限制时间的时间部分发生变化的第二写使能信号是多个核心控制信号，其中核心控制信号改变的时间间隔基于输入的第一写入使能信号和第二写入使能信号而局部地短于第一写入使能信号的周期并且通过使用所生成的核心控制信号来执行电阻性随机存取存储器的操作验证，从而局部地和任意地调整任意测试周期中的周期时间。

36. 发明授权

US07889537B2 Non-volatile memory device and method for writing data thereto 有权
标题翻译：用于向其写入数据的非易失性存储器件和方法
公开(公告)号：US07889537B2
公开(公告)日：2011-02-15
申请号：US12118064
申请日：2008-05-09
申请人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
发明人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
IPC分类号： G11C11/00 , G11C17/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/32 , G11C2213/72
摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.
摘要翻译：本发明提供一种将数据写入非易失性存储器件的方法，该非易失性存储器件具有彼此相交的第一布线和第二布线以及布置在其间的每个交叉处的存储单元，每个存储单元具有可变电阻元件和整流元件系列。根据该方法，在所选择的第一布线中升高之前，将第二布线充电至不小于整流元件阈值的一定电压。然后，将所选择的第一布线充电到写入或擦除所需的电压，之后放电所选择的第二布线。

37. 发明申请

US20090265591A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20090265591A1
公开(公告)日：2009-10-22
申请号：US12415448
申请日：2009-03-31
申请人： Yuki Okukawa , Kazushige Kanda
发明人： Yuki Okukawa , Kazushige Kanda
IPC分类号： G11C29/04 , G06F11/22
CPC分类号： G01R31/3183 , G01R31/31919 , G11C16/04 , G11C29/028 , G11C29/48 , G11C29/50 , G11C29/56
摘要： A semiconductor integrated circuit device related to an embodiment of the present invention includes an address register which includes an internal selection circuit connected with a control circuit, a signal generation instruction circuit which instructs the control circuit so that a predetermined internal control signal is generated, a latch circuit, a plurality of which are arranged corresponding to a number of bits of test parameter data, the latch circuit latching test result data which is provided from the data program/read circuit and outputting the test result data to the selection circuit and externally, the control circuit generating an internal control signal which activates the selection circuit at a timing at which a fixed value data of the test parameter data is changed, and the selection circuit controlling a test so that a fixed value data of the test parameter data is changed.
摘要翻译：与本发明的实施例有关的半导体集成电路装置包括地址寄存器，其包括与控制电路连接的内部选择电路，指示控制电路以产生预定的内部控制信号的信号生成指令电路，锁存电路，其中多个对应于测试参数数据的位数排列，锁存电路锁存从数据程序/读取电路提供的测试结果数据，并将测试结果数据输出到选择电路和外部，所述控制电路产生内部控制信号，所述内部控制信号在所述测试参数数据的固定值数据被改变的定时激活所述选择电路，并且所述选择电路控制测试，使得所述测试参数数据的固定值数据被改变。

38. 发明授权

US07539053B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07539053B2
公开(公告)日：2009-05-26
申请号：US11849752
申请日：2007-09-04
申请人： Kazushige Kanda
发明人： Kazushige Kanda
IPC分类号： G11C16/04
CPC分类号： G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C2211/5641
摘要： A non-volatile semiconductor memory device includes plurality of word lines and a plurality of bit lines comprising even numbered bit lines and odd numbered bit lines and a memory cell array including a plurality of memory cells having two or more storage states, one of the plurality of memory cells being connected to a corresponding word line of the plurality of word lines, the number of storage states between adjacent memory cells is different in a word line direction and a bit line direction.
摘要翻译：非易失性半导体存储器件包括多个字线和包括偶数位线和奇数位线的多个位线，以及包括具有两个或多个存储状态的多个存储单元的存储单元阵列，多个存储器单元中的一个的存储单元连接到多个字线的对应字线，相邻存储单元之间的存储状态数在字线方向和位线方向上不同。

39. 发明授权

US07382675B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07382675B2
公开(公告)日：2008-06-03
申请号：US11472360
申请日：2006-06-22
申请人： Kazushige Kanda
发明人： Kazushige Kanda
IPC分类号： G11C5/14 , G11C7/00 , G11C11/34
CPC分类号： G11C17/18 , G11C2029/4402
摘要： According to an aspect of the invention, there is provided a semiconductor memory device including a first power source which generates a first power supply voltage, a second power source which generates a second power supply voltage, a generation circuit which generates a third power supply voltage from the first power supply voltage, a switching circuit which selects one of the second power supply voltage and the third power supply voltage, and a fuse circuit connected to the switching circuit and equipped with a fuse element to carry out a fuse reading operation, wherein the third power supply voltage is supplied from the switching circuit to the fuse circuit during the fuse reading operation.
摘要翻译：根据本发明的一个方面，提供了一种半导体存储器件，包括产生第一电源电压的第一电源，产生第二电源电压的第二电源，产生第三电源电压的发生电路从所述第一电源电压开始，选择所述第二电源电压和所述第三电源电压中的一个的开关电路，以及连接到所述开关电路并配备有熔丝元件以进行熔丝读取操作的熔丝电路，其中在保险丝读取操作期间，第三电源电压从开关电路提供给熔丝电路。

40. 发明申请

US20060291124A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060291124A1
公开(公告)日：2006-12-28
申请号：US11472360
申请日：2006-06-22
申请人： Kazushige Kanda
发明人： Kazushige Kanda
IPC分类号： H02H5/04
CPC分类号： G11C17/18 , G11C2029/4402
摘要： According to an aspect of the invention, there is provided a semiconductor memory device including a first power source which generates a first power supply voltage, a second power source which generates a second power supply voltage, a generation circuit which generates a third power supply voltage from the first power supply voltage, a switching circuit which selects one of the second power supply voltage and the third power supply voltage, and a fuse circuit connected to the switching circuit and equipped with a fuse element to carry out a fuse reading operation, wherein the third power supply voltage is supplied from the switching circuit to the fuse circuit during the fuse reading operation.
摘要翻译：根据本发明的一个方面，提供了一种半导体存储器件，包括产生第一电源电压的第一电源，产生第二电源电压的第二电源，产生第三电源电压的发生电路从所述第一电源电压开始，选择所述第二电源电压和所述第三电源电压中的一个的开关电路，以及连接到所述开关电路并配备有熔丝元件以进行熔丝读取操作的熔丝电路，其中在保险丝读取操作期间，第三电源电压从开关电路提供给熔丝电路。

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