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31. 发明授权

US07890903B2 Method and system for formal verification of an electronic circuit design 有权
标题翻译：电子电路设计形式验证的方法和系统
公开(公告)号：US07890903B2
公开(公告)日：2011-02-15
申请号：US12129127
申请日：2008-05-29
申请人： Kai Weber , Matthias Pflanz , Christian Jacobi , Udo Krautz
发明人： Kai Weber , Matthias Pflanz , Christian Jacobi , Udo Krautz
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A new and convenient methodology for proving the correctness of multiplier and multiply-accumulate circuit designs in a full custom design flow. Such an approach utilizes a basic description of the implemented algorithm, which is created in early phases of the design flow and requires only little extra work for the designer who spends most of the time in full-custom optimizations. Such an approach also defines arithmetic circuit at the arithmetic bit level and allows for the generation of a gate level netlist. Given a structural similarity between the specification and design under verification, a large amount of structural similarity between the generated netlists is obtained so that a standard equivalence checker can be utilized to verify the design against the specification.
摘要翻译：一种新的便捷的方法，用于在完整的定制设计流程中证明乘法器的正确性和乘法积累电路设计。这种方法利用了实现的算法的基本描述，该算法是在设计流程的早期阶段创建的，并且只需要花费大部分时间进行全自定义优化的设计人员的额外工作。这种方法还在算术位电平处定义运算电路，并允许生成门级网表。给定了在规范和验证设计之间的结构相似性，获得了生成的网表之间大量的结构相似性，从而可以利用标准的等价检验器来验证与规范相关的设计。

32. 发明申请

US20090300560A1 METHOD AND SYSTEM FOR FORMAL VERIFICATION OF AN ELECTRONIC CIRCUIT DESIGN 有权
标题翻译：用于电子电路设计的正式验证的方法和系统
公开(公告)号：US20090300560A1
公开(公告)日：2009-12-03
申请号：US12129127
申请日：2008-05-29
申请人： Kai Weber , Matthias Pflanz , Christian Jacobi , Udo Krautz
发明人： Kai Weber , Matthias Pflanz , Christian Jacobi , Udo Krautz
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A new and convenient methodology for proving the correctness of multiplier and multiply-accumulate circuit designs in a full custom design flow. Such an approach utilizes a basic description of the implemented algorithm, which is created in early phases of the design flow and requires only little extra work for the designer who spends most of the time in full-custom optimizations. Such an approach also defines arithmetic circuit at the arithmetic bit level and allows for the generation of a gate level netlist. Given a structural similarity between the specification and design under verification, a large amount of structural similarity between the generated netlists is obtained so that a standard equivalence checker can be utilized to verify the design against the specification.
摘要翻译：一种新的便捷的方法，用于在完整的定制设计流程中证明乘法器的正确性和乘法积累电路设计。这种方法利用了实现的算法的基本描述，该算法是在设计流程的早期阶段创建的，并且只需要花费大部分时间进行全自定义优化的设计人员的额外工作。这种方法还在算术位电平处定义运算电路，并允许生成门级网表。给定了在规范和验证设计之间的结构相似性，获得了生成的网表之间大量的结构相似性，从而可以利用标准的等价检验器来验证与规范相关的设计。

33. 发明申请

US20070050435A1 Leading-Zero Counter and Method to Count Leading Zeros 审中-公开
标题翻译：领先的零计数器和计算领先零的方法
公开(公告)号：US20070050435A1
公开(公告)日：2007-03-01
申请号：US11459663
申请日：2006-07-25
申请人： Christian Jacobi , Silvia Mueller , Jochen Preiss , Kai Weber
发明人： Christian Jacobi , Silvia Mueller , Jochen Preiss , Kai Weber
IPC分类号： G06F15/00
CPC分类号： G06F7/74
摘要： The present invention relates to a circuit comprising a Leading Zero Counter (LZC) sub-circuit driving a second sub-circuit, like a shifter or arbiter. Shifter circuits or arbiter circuits operating with fewer stages than before have a smaller delay since every stage can select between more than two inputs. This reduces the overall delay of the shifter, arbiter, etc. But for state-of-the art binary LZC circuits this requires a complex recoding between LZC and shifter circuit. In order to provide an improved leading zero circuit having an output which allows a simpler control of a post-connected sub-circuit having two or more stages and having at least one stage with three or more inputs, it is proposed to provide a LZC circuitry providing an output consisting of two or more unary encoded substrings. This removes the requirement for a recoder between LZC and shifter.
摘要翻译：本发明涉及一种包括驱动第二子电路的前导零计数器（LZC）子电路的电路，如移相器或仲裁器。移动器电路或仲裁器电路的运行次数比以前更少，延迟较小，因为每个阶段都可以在两个以上的输入之间进行选择。这减少了移位器，仲裁器等的总体延迟。但是对于最先进的二进制LZC电路，这需要LZC和移位器电路之间的复杂重新编码。为了提供具有输出的改进的前导零电路，其允许更简单地控制具有两个或更多个级的后连接子电路并且具有至少一个具有三个或更多个输入的级，所以建议提供一种LZC电路提供由两个或更多个一元编码的子串组成的输出。这消除了对LZC和移位器之间的重新编码器的要求。

34. 发明授权

US10437602B2 Program interruption filtering in transactional execution 有权
公开(公告)号：US10437602B2
公开(公告)日：2019-10-08
申请号：US13524839
申请日：2012-06-15
申请人： Dan F. Greiner , Christian Jacobi , Marcel Mitran , Timothy J. Slegel
发明人： Dan F. Greiner , Christian Jacobi , Marcel Mitran , Timothy J. Slegel
IPC分类号： G06F9/30 , G06F9/38 , G06F9/46 , G06F9/48
摘要： Program exception conditions cause a transaction to abort and typically result in an interruption in which the operating system obtains control. A program interruption filtering control is provided to selectively present the interrupt. That is, the interrupt from the program exception condition may or may not be presented depending at least on the program interruption filtering control and a transaction class associated with the program exception condition. The program interruption filtering control is provided by a TRANSACTION BEGIN instruction.

35. 发明授权

US09740549B2 Facilitating transaction completion subsequent to repeated aborts of the transaction 有权
公开(公告)号：US09740549B2
公开(公告)日：2017-08-22
申请号：US13524857
申请日：2012-06-15
申请人： Brenton F. Belmar , Christian Jacobi , Randall W. Philley , Timothy J. Slegel
发明人： Brenton F. Belmar , Christian Jacobi , Randall W. Philley , Timothy J. Slegel
IPC分类号： G06F7/00 , G06F17/00 , G06F11/07 , G06F17/30 , G06F9/46 , G06F13/24
CPC分类号： G06F11/076 , G06F9/466 , G06F11/0721 , G06F13/24 , G06F17/30371
摘要： Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.

36. 发明授权

US09710266B2 Instruction to compute the distance to a specified memory boundary 有权
公开(公告)号：US09710266B2
公开(公告)日：2017-07-18
申请号：US13421451
申请日：2012-03-15
申请人： Jonathan D. Bradbury , Michael K. Gschwind , Christian Jacobi , Eric M. Schwarz , Timothy J. Slegel
发明人： Jonathan D. Bradbury , Michael K. Gschwind , Christian Jacobi , Eric M. Schwarz , Timothy J. Slegel
IPC分类号： G06F9/38 , G06F9/30 , G06F9/355
CPC分类号： G06F9/30043 , G06F9/3001 , G06F9/3004 , G06F9/30076 , G06F9/355 , G06F9/3824 , G06F9/3861
摘要： A Load Count to Block Boundary instruction is provided that provides a distance from a specified memory address to a specified memory boundary. The memory boundary is a boundary that is not to be crossed in loading data. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary; or it may be dynamically determined.

37. 发明授权

US09459867B2 Instruction to load data up to a specified memory boundary indicated by the instruction 有权
标题翻译：将数据加载到指令指定的指定内存边界的指令
公开(公告)号：US09459867B2
公开(公告)日：2016-10-04
申请号：US13421456
申请日：2012-03-15
申请人： Jonathan D. Bradbury , Michael K. Gschwind , Christian Jacobi , Eric M. Schwarz , Timothy J. Slegel
发明人： Jonathan D. Bradbury , Michael K. Gschwind , Christian Jacobi , Eric M. Schwarz , Timothy J. Slegel
IPC分类号： G06F9/30 , G06F9/38 , G06F9/455
CPC分类号： G06F9/30043 , G06F9/30007 , G06F9/30036 , G06F9/3004 , G06F9/30047 , G06F9/30098 , G06F9/3013 , G06F9/30145 , G06F9/3824 , G06F9/3861 , G06F9/45516
摘要： A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary.
摘要翻译：加载到块提供了将可变数量的字节数据加载到寄存器中，同时确保指定的存储器边界未被越过。边界可以指定多种方式，包括但不限于指令文本中的可变值，编码在操作码中的固定指令文本值或基于寄存器的边界。

38. 发明授权

US09336046B2 Transaction abort processing 有权
标题翻译：事务中止处理
公开(公告)号：US09336046B2
公开(公告)日：2016-05-10
申请号：US13524877
申请日：2012-06-15
申请人： Dan F. Greiner , Christian Jacobi , Timothy J. Slegel
发明人： Dan F. Greiner , Christian Jacobi , Timothy J. Slegel
IPC分类号： G06F9/46 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30098 , G06F9/3004 , G06F9/30087 , G06F9/30145 , G06F9/3834 , G06F9/3842 , G06F9/3857 , G06F9/3861 , G06F9/466
摘要： A transaction executing within a computing environment ends prior to completion; i.e., execution is aborted. Pursuant to aborting execution, a hardware transactional execution CPU mode is exited, and one or more of the following is performed: restoring selected registers; committing nontransactional stores on abort; branching to a transaction abort program status word specified location; setting a condition code and/or abort code; and/or preserving diagnostic information.
摘要翻译：在计算环境中执行的事务在完成之前结束; 即执行中止。根据中止执行，退出硬件事务执行CPU模式，执行以下一个或多个操作：恢复所选择的寄存器; 在中止时承诺非事务性商店; 分支到事务中止程序状态字指定位置; 设置条件代码和/或中止代码; 和/或保存诊断信息。

39. 发明授权

US09262320B2 Tracking transactional execution footprint 有权
标题翻译：跟踪事务执行占用
公开(公告)号：US09262320B2
公开(公告)日：2016-02-16
申请号：US13524355
申请日：2012-06-15
申请人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi , Patrick M. West
发明人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi , Patrick M. West
IPC分类号： G06F12/08 , G06F9/46 , G06F9/30 , G06F9/38
CPC分类号： G06F12/08 , G06F9/30 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3013 , G06F9/3834 , G06F9/3859 , G06F9/466 , G06F9/467 , G06F12/0815 , G06F12/084
摘要： Embodiments relate to tracking a transactional execution footprint. An aspect includes receiving a store instruction which includes store data. It is determined if the store instruction is executing within a transaction that effectively delays committing stores to a shared cache until the transaction has completed. The store data is stored to a cache line in a local cache. The cache line is marked as dirty if the transaction is active. The stored data that was marked as dirty in the local cache is invalidated if the transaction has terminated abnormally. The stored data is un-marked if it is determined that the transaction has successfully ended.
摘要翻译：实施例涉及跟踪事务执行足迹。一方面包括接收包括存储数据的存储指令。确定存储指令是否在事务内执行，以有效地将提交存储延迟到共享高速缓存，直到事务完成。存储数据被存储到本地高速缓存中的高速缓存行。如果事务处于活动状态，则缓存行被标记为脏。如果事务异常终止，则在本地缓存中标记为脏的存储数据将无效。如果确定交易已成功结束，则存储的数据将被取消标记。

40. 发明申请

US20130339675A1 RANDOMIZED TESTING WITHIN TRANSACTIONAL EXECUTION 有权
标题翻译：在实际执行过程中进行随机测试
公开(公告)号：US20130339675A1
公开(公告)日：2013-12-19
申请号：US13524796
申请日：2012-06-15
申请人： Dan F. Greiner , Christian Jacobi , Timothy J. Slegel
发明人： Dan F. Greiner , Christian Jacobi , Timothy J. Slegel
IPC分类号： G06F9/00
CPC分类号： G06F11/1474 , G06F9/3861 , G06F9/466 , G06F9/467 , G06F11/3636 , G06F11/366 , G06F11/3688 , G06F13/4068 , G06F2201/87
摘要： Task specific diagnostic controls are provided to facilitate the debugging of certain types of abort conditions. The diagnostic controls may be set to cause transactions to be selectively aborted, allowing a transaction to drive its abort handler routine for testing purposes. The controls include, for instance, a transaction diagnostic scope and a transaction diagnostic control. The transaction diagnostic scope indicates when the transaction diagnostic control is to be applied, and the transaction diagnostic control indicates whether transactions are to selectively aborted.
摘要翻译：提供任务特定的诊断控制，以便于某些类型的中止条件的调试。可以设置诊断控件以导致事务被选择性地中止，从而允许事务驱动其中止处理程序用于测试目的。控件包括例如事务诊断范围和事务诊断控件。事务诊断范围指示何时应用事务诊断控件，并且事务诊断控件指示是否选择性地中止事务。

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