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31. 发明授权

US06327244B1 Packet handler 有权
标题翻译：数据包处理程序
公开(公告)号：US06327244B1
公开(公告)日：2001-12-04
申请号：US09210849
申请日：1998-12-15
申请人： Ken'ichi Sakamoto , Yasunari Shinohara , Takahiko Kozaki
发明人： Ken'ichi Sakamoto , Yasunari Shinohara , Takahiko Kozaki
IPC分类号： G01R3108
CPC分类号： H04Q11/0478 , H04L49/10 , H04L49/103 , H04L49/201 , H04L49/25 , H04L49/254 , H04L49/30 , H04L49/3009 , H04L49/552
摘要： A packet handler includes an interface circuit of an ATM handler corresponding in one-to-one relation to each input/output port of an ATM switch. A switch interface including a disconnection circuit and a distribution circuit controls the cell flow from each interface circuit to a corresponding input port and the cell from the output ports of the ATM switch to each interface circuit. In a set of the interface circuits, one redundant transmission path can be replaced arbitrarily with two nonredundant independant transmission paths. The ATM communication system can thus accomodate redundant transmission paths and nonredundant transmission paths in an arbitrary ratio.
摘要翻译：分组处理器包括与ATM交换机的每个输入/输出端口一对一关系的ATM处理器的接口电路。包括断开电路和分配电路的开关接口控制从每个接口电路到相应输入端口的单元流以及从ATM交换机的输出端口到每个接口电路的单元流。在一组接口电路中，可以用两个非冗余独立传输路径任意替换一个冗余传输路径。因此，ATM通信系统可以以任意比例容纳冗余传输路径和非冗余传输路径。

32. 发明授权

US06021130A ATM switching system and cell control method 失效
标题翻译： ATM交换系统和电池控制方法
公开(公告)号：US06021130A
公开(公告)日：2000-02-01
申请号：US94675
申请日：1998-06-15
申请人： Takahiko Kozaki , Morihito Miyagi , Manabu Okamoto
发明人： Takahiko Kozaki , Morihito Miyagi , Manabu Okamoto
IPC分类号： H04Q3/00 , H04L12/801 , H04L12/851 , H04L12/911 , H04L12/927 , H04L12/931 , H04L12/937 , H04Q11/04 , H04J3/14
CPC分类号： H04L12/5601 , H04L49/103 , H04L49/108 , H04L49/255 , H04L49/3009 , H04L49/3027 , H04L49/3081 , H04L49/309 , H04L49/505 , H04L2012/563 , H04L2012/5647 , H04L2012/5648 , H04L2012/5658 , H04L2012/5681
摘要： An ATM switching system which includes PVC allocation circuits corresponding to output queues. At the time of arrival of the leading cell of each burst data, if the output line has room, the PVC of the burst data is stored as information for admission and identification. The subsequently-arriving cells having the same PVC identification information as the stored identification information are input to an output buffer, and the cells of the remaining burst data are all discarded. Even when a plurality of burst data compete for the same output line, the fact that all the cells other than the first-arriving admitted burst data are discarded prevents the cells from being input other than within a predetermined bandwidth and localizes the burst data affected by the cell discarding due to output queue overflow.
摘要翻译：一种ATM交换系统，包括对应于输出队列的PVC分配电路。在每个突发数据的前导单元到达时，如果输出线有空间，则突发数据的PVC被存储为用于准入和识别的信息。具有与存储的标识信息相同的PVC识别信息的随后到达的小区被输入到输出缓冲器，并且剩余突发数据的单元全部被丢弃。即使当多个突发数据竞争相同的输出线时，除了首次到达的入站突发数据之外的所有小区被丢弃的事实也防止了小区在预定带宽之外的输入，并且定位了受到由于输出队列溢出而导致的单元丢弃。

33. 发明授权

US5530698A ATM switching system and cell control method 失效
公开(公告)号：US5530698A
公开(公告)日：1996-06-25
申请号：US294496
申请日：1994-08-23
申请人： Takahiko Kozaki , Morihito Miyagi , Manabu Okamoto
发明人： Takahiko Kozaki , Morihito Miyagi , Manabu Okamoto
IPC分类号： H04Q3/00 , H04L12/801 , H04L12/851 , H04L12/911 , H04L12/927 , H04L12/931 , H04L12/937 , H04Q11/04 , H04J3/14
CPC分类号： H04L12/5601 , H04L49/103 , H04L49/108 , H04L49/255 , H04L49/3009 , H04L49/3027 , H04L49/3081 , H04L49/309 , H04L49/505 , H04L2012/563 , H04L2012/5647 , H04L2012/5648 , H04L2012/5658 , H04L2012/5681
摘要： An ATM switching system which includes PVC allocation circuits corresponding to output queues. At the time of arrival of the leading cell of each burst data, if the output line has room, the PVC of the burst data is stored as information for admission and identification. The subsequently-arriving cells having the same PVC identification information as the stored identification information are input to an output buffer, and the cells of the remaining burst data are all discarded. Even when a plurality of burst data compete for the same output line, the fact that all the cells other than the first-arriving admitted burst data are discarded prevents the cells from being input other than within a predetermined bandwidth and localizes the burst data affected by the cell discarding due to output queue overflow.

34. 发明授权

US5124977A Switching system for switching cells having error detection apparatus 失效
标题翻译：用于切换具有错误检测装置的电池的开关系统
公开(公告)号：US5124977A
公开(公告)日：1992-06-23
申请号：US482090
申请日：1990-02-20
申请人： Takahiko Kozaki , Yoshito Sakurai
发明人： Takahiko Kozaki , Yoshito Sakurai
IPC分类号： H04L12/883 , H04L12/933 , H04Q11/04
CPC分类号： H04Q11/0478 , H04L12/5601 , H04L12/5602 , H04L49/108 , H04L2012/5627 , H04L2012/5651 , H04L2012/5674 , H04L2012/5681
摘要： A switching system for handling a plurality of cells, each cell including a header section and a data section, and for exchanging a communication message contained in the data section of the cell between a plurality of incoming highways and a plurality of outgoing highways according to the data contained in the header section of the cell. The switching system includes a unit for multiplexing the incoming highways in time division, a first memory having addressable storage locations for storing cells received from the multiplexing unit, a unit for demultiplexing and distributing data output from the first memory among a plurality of outgoing highways, a second memory for storing an empty address of an empty storage location of the first memory, a unit for controlling the write and read operations of the first memory in accordance with an empty address stored in the second memory used as write and read addresses, and a unit for detecting an error in at least one of the write address and read address.

35. 发明授权

US07502380B2 Packet handler 失效
标题翻译：数据包处理程序
公开(公告)号：US07502380B2
公开(公告)日：2009-03-10
申请号：US11006636
申请日：2004-12-08
申请人： Ken'ichi Sakamoto , Yasunari Shinohara , Takahiko Kozaki
发明人： Ken'ichi Sakamoto , Yasunari Shinohara , Takahiko Kozaki
IPC分类号： H04L12/28
CPC分类号： H04Q11/0478 , H04L49/10 , H04L49/103 , H04L49/201 , H04L49/25 , H04L49/254 , H04L49/30 , H04L49/3009 , H04L49/552
摘要： A packet handler includes an interface circuit corresponding in one-to-one relation to each input/output port of a switch. A switch interface including a disconnection circuit and a distribution circuit controls the packet from each interface circuit to a corresponding input port and the packet from the output ports of the switch to each interface circuit. In a set of interface circuits, one redundant transmission path can be replaced arbitrarily with two non-redundant independent transmission paths. The packet communication system can thus accommodate redundant transmission paths and non-redundant transmission paths in an arbitrary ratio.
摘要翻译：分组处理器包括与交换机的每个输入/输出端口一对一关系对应的接口电路。包括断开电路和分配电路的开关接口将来自每个接口电路的分组控制到相应的输入端口，并将分组从交换机的输出端口控制到每个接口电路。在一组接口电路中，可以用两个非冗余独立传输路径任意替换一个冗余传输路径。分组通信系统因此可以以任意比例容纳冗余传输路径和非冗余传输路径。

36. 发明授权

US06850485B2 Packet handler 失效
标题翻译：数据包处理程序
公开(公告)号：US06850485B2
公开(公告)日：2005-02-01
申请号：US09955159
申请日：2001-09-19
申请人： Ken'ichi Sakamoto , Yasunari Shinohara , Takahiko Kozaki
发明人： Ken'ichi Sakamoto , Yasunari Shinohara , Takahiko Kozaki
IPC分类号： H04L1/22 , H04L12/70 , H04L12/935 , H04Q3/00 , H04Q11/04 , G01R31/08
CPC分类号： H04Q11/0478 , H04L49/10 , H04L49/103 , H04L49/201 , H04L49/25 , H04L49/254 , H04L49/30 , H04L49/3009 , H04L49/552
摘要： A packet handler includes an interface circuit of an ATM handler corresponding in one-to-one relation to each input/output port of an ATM switch. A switch interface including a disconnection circuit and a distribution circuit controls the cell flow from each interface circuit to a corresponding input port and the cell from the output ports of the ATM switch to each interface circuit. In a pet of interface circuits, one redundant transmission path can be replaced arbitrarily with two nonredundant independent transmission paths. The ATM communication system can thus accommodate redundant transmission paths and nonredundant transmission paths in an arbitrary ratio.
摘要翻译：分组处理器包括与ATM交换机的每个输入/输出端口一对一关系的ATM处理器的接口电路。包括断开电路和分配电路的开关接口控制从每个接口电路到相应输入端口的单元流以及从ATM交换机的输出端口到每个接口电路的单元流。在接口电路的宠物中，一个冗余传输路径可以用两个非冗余独立传输路径任意替换。因此，ATM通信系统可以以任意比例容纳冗余传输路径和非冗余传输路径。

37. 发明授权

US06611527B1 Packet switching apparatus with a common buffer 失效
标题翻译：具有公共缓冲区的分组交换设备
公开(公告)号：US06611527B1
公开(公告)日：2003-08-26
申请号：US09497210
申请日：2000-02-03
申请人： Norihiko Moriwaki , Mitsuhiro Wada , Takahiko Kozaki , Hiroaki Kasahara
发明人： Norihiko Moriwaki , Mitsuhiro Wada , Takahiko Kozaki , Hiroaki Kasahara
IPC分类号： H04L1228
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/608 , H04L2012/5651 , H04L2012/5679 , H04L2012/5681 , H04L2012/5684
摘要： A plurality of address chains are assigned to each of such flows as output lines, priority control, etc. in the address management carried out in a switch with a shared buffer. Each of the address chains has a write address register 20 and a read address register 30. The switch is also provided with a distributive pointer 22 for distributing cells in a flow to a plurality of address chains and a write address register selector 21, as well as a read pointer 32 for reading packets from a plurality of the address chains and a read address register selector 31 so as to read the packets through a pipeline with use of those plural address chains.
摘要翻译：在具有共享缓冲器的交换机中执行的地址管理中，将多个地址链分配给每个这样的流作为输出线，优先级控制等。每个地址链具有写入地址寄存器20和读取地址寄存器30.开关还具有分配指示器22，用于将流中的单元分配到多个地址链和写入地址寄存器选择器21 作为用于从多个地址链读取分组的读指针32和读地址寄存器选择器31，以便通过使用这些多个地址链的流水线读取分组。

38. 发明授权

US06507584B1 ATM switch 失效
标题翻译： ATM交换机
公开(公告)号：US06507584B1
公开(公告)日：2003-01-14
申请号：US09193414
申请日：1998-11-18
申请人： Norihiko Moriwaki , Takahiko Kozaki , Takaaki Toyama , Mitsuhiro Wada , Yozo Oguri
发明人： Norihiko Moriwaki , Takahiko Kozaki , Takaaki Toyama , Mitsuhiro Wada , Yozo Oguri
IPC分类号： H04L1228
CPC分类号： H04L12/5601 , H04L49/153 , H04L49/1538 , H04L49/1576 , H04L49/255 , H04L49/3081 , H04L49/455 , H04L2012/565 , H04L2012/5681 , H04Q11/0478
摘要： An ATM switch that can be expanded to form a large scale ATM switch with minimal hardware additions. The ATM switch includes a plurality of ATM switch units arranged in parallel, a plurality of cell distributors arranged on the input side of the ATM switch units, and a plurality of cell assemblers arranged on the output side of the ATM switch units. Each of the cell distributors distributes ATM cells received from a plurality of incoming highways to a buffer memory having a plurality of queues corresponding to the output ports of the ATM switch units, namely destinations of the ATM cells, and stores the ATM cells to the queues in the buffer memory. Each cell distributor reads ATM cells having the same destination information, and outputs such ATM cells to respective ones of the ATM switch units in parallel. Each of the ATM switch units independently exchanges the received ATM cell in parallel with the other ATM switch units. Each of the cell assemblers multiplexes ATM cells received from the ATM switch units in a manner to preserve the time sequential order of the ATM cells, and outputs the ATM cells to one of a plurality of outgoing highways. A desired increase in the capacity of the ATM switch is implemented by adding an ATM switch unit between the cell distributors and the cell assemblers, thereby allowing for an increase in hardware in proportion to the desired increase in capacity.
摘要翻译：一个ATM交换机，可以扩展，形成一个大型ATM交换机，最少的硬件添加。 ATM交换机包括并行布置的多个ATM交换单元，布置在ATM交换单元的输入侧的多个单元分配器，以及布置在ATM交换单元的输出侧的多个单元汇编器。每个小区分配器将从多个入站高速公路接收的ATM信元分配到具有对应于ATM交换单元的输出端口的多个队列的缓冲存储器，即ATM信元的目的地，并将ATM信元存储到队列在缓冲存储器中。每个单元分配器读取具有相同目的地信息的ATM信元，并且将这些ATM信元并行地输出到相应的ATM交换单元。每个ATM交换单元与其他ATM交换单元并行地独立地交换所接收的ATM信元。每个小区装配器以保持ATM信元的时间顺序的方式复用从ATM交换机单元接收的ATM信元，并将ATM信元输出到多个输出高速公路中的一个。通过在单元分配器和单元组装器之间添加ATM交换单元来实现ATM交换机的容量的期望的增加，从而允许与期望的容量增加成比例地增加硬件。

39. 发明授权

US5923657A ATM switching system and cell control method 失效
公开(公告)号：US5923657A
公开(公告)日：1999-07-13
申请号：US31776
申请日：1998-02-27
申请人： Takahiko Kozaki , Morihito Miyagi , Manabu Okamoto
发明人： Takahiko Kozaki , Morihito Miyagi , Manabu Okamoto
IPC分类号： H04L12/56 , H04J3/14
CPC分类号： H04L12/5601 , H04L49/255 , H04L49/3081 , H04L2012/5647 , H04L2012/5658 , H04L2012/5681
摘要： An ATM switching system which includes PVC allocation circuits corresponding to output queues. At the time of arrival of the leading cell of each burst data, if the output line has room, the PVC of the burst data is stored as information for admission and identification. The subsequently-arriving cells having the same PVC identification information as the stored identification information are input to an output buffer, and the cells of the remaining burst data are all discarded. Even when a plurality of burst data compete for the same output line, the fact that all the cells other than the first-arriving admitted burst data are discarded prevents the cells from being input other than within a predetermined bandwidth and localizes the burst data affected by the cell discarding due to output queue overflow.

40. 发明授权

US4964119A Method and system for packet exchange 失效
标题翻译：分组交换的方法和系统
公开(公告)号：US4964119A
公开(公告)日：1990-10-16
申请号：US334211
申请日：1989-04-06
申请人： Noboru Endo , Takahiko Kozaki , Hiroshi Kuwahara , Kenichi Ohtsuki , Shinobu Gohara
发明人： Noboru Endo , Takahiko Kozaki , Hiroshi Kuwahara , Kenichi Ohtsuki , Shinobu Gohara
IPC分类号： H04L12/801 , H04L12/931
CPC分类号： H04L49/103 , H04L49/25 , H04L49/254 , H04L49/30 , H04L49/3009
摘要： In a packet exchange system for preforming packet exchange by setting logical channels, individual input packets are assigned with information indicative of input sequence of the individual input packets counted in each call and the input sequence information is stored. Each time each packet is delivered, the input sequence information assigned to an input packet is stored as an output sequence information in a call to which the delivered packet belongs, and the status of congestion of packets of the call which are present in the exchange is decided on the basis of the stored input sequence information and output sequence information. This system further includes a rerouting circuit having buffer function and a control device for changing the contents of a conversion table when it detects by looking up the conversion table that the number of packets remaining in the exchange which are destined for a specified output line exceeds a predetermined threshold, whereby input packets scheduled to be destined for the specified output line are temporarily stored in the rerouting circuit.

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