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31. 发明授权

US5410267A 3.3 V to 5 V supply interface buffer 失效
标题翻译： 3.3 V至5 V电源接口缓冲器
公开(公告)号：US5410267A
公开(公告)日：1995-04-25
申请号：US126334
申请日：1993-09-24
申请人： Matthew B. Haycock , Stephen R. Mooney
发明人： Matthew B. Haycock , Stephen R. Mooney
IPC分类号： H03K19/0175 , H03K19/0185 , H03K19/094
CPC分类号： H03K3/356113 , H03K19/017518 , H03K19/018521
摘要： An improved 3.3 V to 5 V interface buffer comprising a solid state BiCMOS device implemented on a reduced voltage process designed to operate from 3.3 V and 5 V supplies and capable of receiving a 0-3.3 V input signal while providing a external swing signal from 0-5 V. Specifically, cross coupled PMOS and NMOS devices manufactured by a 3.3 V process are utilized with level shifting diodes for achieving a device which operates on higher voltages than conventional circuit design techniques allow for a given process technique, while providing a 0-5 V output at the sending device.
摘要翻译：一种改进的3.3 V至5 V接口缓冲器，包括一个固态BiCMOS器件，该器件采用设计用于3.3 V和5 V电源工作的降压工艺，并能够接收0-3.3 V输入信号，同时提供0的外部摆幅信号具体来说，采用3.3V工艺制造的交叉耦合PMOS和NMOS器件用于电平移位二极管，用于实现与常规电路设计技术相比更高的电压工作的器件，允许给定的工艺技术，同时提供0- 发送设备输出5 V输出。

32. 发明授权

US07222208B1 Simultaneous bidirectional port with synchronization circuit to synchronize the port with another port 失效
标题翻译：具有同步电路的双向口同步端口与另一端口同步
公开(公告)号：US07222208B1
公开(公告)日：2007-05-22
申请号：US09644463
申请日：2000-08-23
申请人： Matthew B. Haycock , Amaresh Pangal
发明人： Matthew B. Haycock , Amaresh Pangal
IPC分类号： G06F1/00 , H03K19/175
CPC分类号： G06F13/4077
摘要： A simultaneous bidirectional port coupled to a bus includes a synchronization circuit that synchronizes the port with another simultaneous data port coupled to the same bus. The synchronization circuit includes an output driver having an imbalanced output impedance, and includes a receiver with input hysteresis. The input hysteresis of the receiver is not satisfied unless both drivers with imbalanced output impedance coupled to the bus assert an output signal. Each driver asserts a signal on the bus when initialization of the corresponding simultaneous bidirectional port is complete. When both simultaneous bidirectional ports are initialized, the hysteresis of the receivers is satisfied, and each port is notified that both have been initialized.
摘要翻译：耦合到总线的同时双向端口包括同步电路，该同步电路使端口与耦合到同一总线的另一同时数据端口同步。同步电路包括具有不平衡输出阻抗的输出驱动器，并且包括具有输入滞后的接收器。接收器的输入滞后不能满足，除非与总线耦合的不平衡输出阻抗的驱动器都断言输出信号。当对应的同时双向端口的初始化完成时，每个驱动器在总线上断言信号。当两个同时双向端口被初始化时，接收器的滞后被满足，并且通知两个端口都被初始化。

33. 发明授权

US06901526B1 Digital bus synchronizer for generating read reset signal 失效
公开(公告)号：US06901526B1
公开(公告)日：2005-05-31
申请号：US09709001
申请日：2000-11-08
申请人： Matthew B. Haycock , Amaresh Pangal
发明人： Matthew B. Haycock , Amaresh Pangal
IPC分类号： G06F1/04 , G06F1/12 , H03K19/00
CPC分类号： G06F1/12
摘要： A digital bus includes a transmitter unit, a receiver unit, and a transmission medium to couple the transmitter unit to the receiver unit and to provide a path for exchanging information between the transmitter unit and the receiver unit. The receiver unit includes a first-in-first-out (FIFO) unit and a synchronizer unit for receiving information from the transmitter unit. The synchronizer unit receives a plurality of write clock signals and a reset signal and generates a read reset signal positioned with respect to the plurality write clock signals and a sample clock signal. The read reset signal has a latency with respect to each of the plurality of write reset signals of between 0 and 1 clock cycles.

34. 发明授权

US06718416B1 Method and apparatus for removing and installing a computer system bus agent without powering down the computer system 有权
标题翻译：用于移除和安装计算机系统总线代理而不关闭计算机系统的方法和装置
公开(公告)号：US06718416B1
公开(公告)日：2004-04-06
申请号：US09643379
申请日：2000-08-21
申请人： Keith M. Self , Matthew B. Haycock
发明人： Keith M. Self , Matthew B. Haycock
IPC分类号： G06F1300
CPC分类号： G06F13/4081
摘要： An example embodiment of a computer system that includes a removable agent that can be removed or installed without powering down the system includes a fixed bus agent and the replaceable bus agent. The fixed bus agent and the replaceable bus agent are electrically coupled together by a presence detect signal, a synchronization signal, and a data bus. A deassertion of the presence detect signal indicates to the fixed bus agent that the removable bus agent has been disconnected and is no longer electrically coupled to the fixed bus agent. The fixed bus agent then tri-states its outputs and also prevents potentially invalid data from being delivered to the core circuitry of the fixed bus agent. An assertion of the presence detect signal indicates to the fixed bus agent that the replaceable bus agent is electrically connected to the fixed bus agent. In response to the assertion of the presence detect signal, the fixed bus agent and the replaceable bus agent enter reset periods. Following the reset periods and when each bus agent is ready to communicate to the other agent, the fixed bus agent and the replaceable bus agent signal to each other over the synchronization signal that each is ready to begin communication over the data bus.
摘要翻译：包括可以在不关闭系统的情况下被移除或安装的可移除代理的计算机系统的示例性实施例包括固定总线代理和可更换总线代理。固定总线代理和可更换总线代理通过存在检测信号，同步信号和数据总线电耦合在一起。存在检测信号的取消表示向固定总线代理指示可移除总线代理已经断开并且不再电耦合到固定总线代理。然后，固定总线代理器对其输出进行三态，并且还防止潜在的无效数据被传递到固定总线代理的核心电路。存在检测信号的断言向固定总线代理指示可更换总线代理电连接到固定总线代理。响应于存在检测信号的确认，固定总线代理和可更换总线代理进入复位周期。在复位周期之后，当每个总线代理准备好与其他代理通信时，固定总线代理和可更换总线代理器通过同步信号相互信号，每个同步信号准备好通过数据总线开始通信。

35. 发明授权

US07328361B2 Digital bus synchronizer for generating read reset signal 有权
标题翻译：数字总线同步器，用于产生读取复位信号
公开(公告)号：US07328361B2
公开(公告)日：2008-02-05
申请号：US11141262
申请日：2005-05-31
申请人： Matthew B. Haycock , Amaresh Pangal
发明人： Matthew B. Haycock , Amaresh Pangal
IPC分类号： G06F1/04 , G06F1/12
CPC分类号： G06F1/12
摘要： A digital bus includes a transmitter unit, a receiver unit, and a transmission medium to couple the transmitter unit to the receiver unit and to provide a path for exchanging information between the transmitter unit and the receiver unit. The receiver unit includes a first-in-first-out (FIFO) unit and a synchronizer unit for receiving information from the transmitter unit. The synchronizer unit receives a plurality of write clock signals and a reset signal and generates a read reset signal positioned with respect to the plurality write clock signals and a sample clock signal. The read reset signal has a latency with respect to each of the plurality of write reset signals of between 0 and 1 clock cycles.
摘要翻译：数字总线包括发射机单元，接收机单元和用于将发射机单元耦合到接收机单元并且提供用于在发射机单元和接收机单元之间交换信息的路径的传输介质。接收机单元包括先进先出（FIFO）单元和用于从发射机单元接收信息的同步器单元。同步器单元接收多个写时钟信号和复位信号，并产生相对于多个写入时钟信号定位的读取复位信号和采样时钟信号。读取复位信号相对于多个写入复位信号中的每一个在0和1个时钟周期之间具有等待时间。

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