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31. 发明授权

US08041897B2 Cache management within a data processing apparatus 有权
标题翻译：数据处理设备内的缓存管理
公开(公告)号：US08041897B2
公开(公告)日：2011-10-18
申请号：US12223173
申请日：2006-09-18
申请人： Stuart David Biles , Richard Roy Grisenthwaite , David Hennah Mansell
发明人： Stuart David Biles , Richard Roy Grisenthwaite , David Hennah Mansell
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/127 , G06F12/0862
摘要： A data processing apparatus, and method of managing at least one cache within such an apparatus, are provided. The data processing apparatus has at least one processing unit for executing a sequence of instructions, with each such processing unit having a cache associated therewith, each cache having a plurality of cache lines for storing data values for access by the associated processing unit when executing the sequence of instructions. Identification logic is provided which, for each cache, monitors data traffic within the data processing apparatus and based thereon generates a preferred for eviction identification identifying one or more of the data values as preferred for eviction. Cache maintenance logic is then arranged, for each cache, to implement a cache maintenance operation during which selection of one or more data values for eviction from that cache is performed having regard to any preferred for eviction identification generated by the identification logic for data values stored in that cache. It has been found that such an approach provides a very flexible technique for seeking to improve cache storage utilisation.
摘要翻译：提供了一种数据处理装置以及管理这种装置中的至少一个高速缓存的方法。数据处理装置具有用于执行指令序列的至少一个处理单元，每个这样的处理单元具有与其相关联的高速缓存，每个高速缓冲存储器具有多个高速缓存行，用于存储由相关处理单元执行访问时的数据值指令序列提供了识别逻辑，对于每个高速缓存来说，监视数据处理装置内的数据业务，并且基于此，生成用于驱逐的标识的优选，以便识别为驱逐优选的一个或多个数据值。然后，对于每个高速缓存，缓存维护逻辑被布置以实现高速缓存维护操作，在该高速缓存维护操作期间，考虑到存储的数据值的识别逻辑生成的用于逐出识别的任何优选的执行，从该缓存中选择一个或多个用于逐出的数据值在那个缓存中。已经发现，这种方法为寻求提高缓存存储利用率提供了非常灵活的技术。

32. 发明申请

US20100094613A1 Device emulation support within a host data processing apparatus 有权
标题翻译：主机数据处理设备内的设备仿真支持
公开(公告)号：US20100094613A1
公开(公告)日：2010-04-15
申请号：US12453806
申请日：2009-05-22
申请人： Stewart David Biles , David Hennah Mansell , Richard Roy Grisenthwaite
发明人： Stewart David Biles , David Hennah Mansell , Richard Roy Grisenthwaite
IPC分类号： G06F9/455 , G06F12/00
CPC分类号： G06F9/45558 , G06F2009/45583
摘要： A data processing apparatus 12 is provided with a memory management unit 24 which triggers memory aborts. When a memory abort occurs, data characterising the memory abort is written to a fault status register 28 (memory-abort register). The data characterising the memory abort includes data identifying a register number associated with the memory access which gave rise to the memory abort. This register identifying data is used to emulate the action of the memory access instruction without having to read the program instruction lead to the memory abort. This is useful in providing virtualisation support for a virtual data processing apparatus 2.
摘要翻译：数据处理装置12设置有触发存储器中止的存储器管理单元24。当发生存储器中止时，表征存储器中止的数据被写入故障状态寄存器28（存储器中止寄存器）。表征存储器中止的数据包括识别与存储器访问相关联的寄存器号的数据，这导致存储器中止。该寄存器识别数据用于模拟存储器访问指令的动作，而不必读取导致存储器中止的程序指令。这在为虚拟数据处理设备2提供虚拟化支持方面是有用的。

33. 发明授权

US07657694B2 Handling access requests in a data processing apparatus 有权
标题翻译：在数据处理设备中处理访问请求
公开(公告)号：US07657694B2
公开(公告)日：2010-02-02
申请号：US11641969
申请日：2006-12-20
申请人： David Hennah Mansell , Stuart David Biles , Stephen John Hill
发明人： David Hennah Mansell , Stuart David Biles , Stephen John Hill
IPC分类号： G06F21/00
CPC分类号： G06F13/24
摘要： A data processing apparatus is provided comprising processing logic for issuing access requests when access to data is required, with each access request specifying a memory address associated with the data the subject of the access request. Access control logic is used to perform an access control operation to check for each access request whether the specified memory address is accessible by the processing logic. Further, a table is provided having a plurality of entries, each entry identifying an address range and an associated action. On occurrence of one or more predetermined events, the access control logic references the table to determine whether the specified address is within the address range identified by an entry of the table. If so, the associated action specified in that entry is invoked, whereas otherwise the access control logic causes any action indicated by the access control operation to be performed. This provides a particularly efficient mechanism for handling access requests in a variety of situations, for example within a virtualization environment where the access requests are directed to virtual devices implemented by hypervisor software.
摘要翻译：提供了一种数据处理装置，包括当需要访问数据时发出访问请求的处理逻辑，每个访问请求指定与访问请求的对象的数据相关联的存储器地址。访问控制逻辑用于执行访问控制操作以检查每个访问请求是否由处理逻辑访问指定的存储器地址。此外，提供具有多个条目的表，每个条目标识地址范围和相关联的动作。在发生一个或多个预定事件时，访问控制逻辑引用该表以确定指定的地址是否在由表的条目标识的地址范围内。如果是，则调用在该条目中指定的相关联的动作，而否则访问控制逻辑将导致执行由访问控制操作指示的任何动作。这提供了用于在各种情况下处理访问请求的特别有效的机制，例如在其中访问请求被引导到由管理程序软件实现的虚拟设备的虚拟化环境中。

34. 发明申请

US20100005269A1 Translation of virtual to physical addresses 有权
标题翻译：虚拟到物理地址的翻译
公开(公告)号：US20100005269A1
公开(公告)日：2010-01-07
申请号：US12216253
申请日：2008-07-01
申请人： Jeremy Piers Davies , David Hennah Mansell , Richard Roy Grisenthwaite
发明人： Jeremy Piers Davies , David Hennah Mansell , Richard Roy Grisenthwaite
IPC分类号： G06F12/02
CPC分类号： G06F12/126 , G06F12/1036
摘要： Address translation circuitry for translating virtual addresses to physical addresses for a data processor in response to access requests from said data processor targeting virtual addresses is disclosed. The address translation circuitry comprises: a data store comprising a plurality of entries for storing a plurality of mappings of ranges of virtual addresses to ranges of physical addresses for said data processor and additional data associated with each of said plurality of mappings within a table; updating circuitry for updating said table in response to an access request for a virtual address that is not mapped by said table, said updating circuitry being responsive to receipt of a mapping for said virtual address to: select a plurality of entries in said table suitable for storing said received mapping; and determine one of said plurality of selected entries to be overwritten by said received mapping in dependence upon at least a portion of said additional data stored in said one of said plurality of selected entries.
摘要翻译：公开了用于将数据处理器的虚拟地址转换为物理地址的地址转换电路，以响应来自所述数据处理器的虚拟地址的访问请求。地址转换电路包括：数据存储器，包括多个条目，用于存储虚拟地址范围的多个映射到所述数据处理器的物理地址范围和与表内的所述多个映射中的每一个相关联的附加数据; 更新电路，用于响应于未被所述表映射的虚拟地址的访问请求来更新所述表，所述更新电路响应于接收到所述虚拟地址的映射，以选择在所述表中适合的多个条目存储所述接收的映射; 并且根据存储在所述多个选择的条目中的所述一个中的所述附加数据的至少一部分，确定要被所述接收的映射覆盖的所述多个所选择的条目中的一个。

35. 发明申请

US20080155167A1 Handling access requests in a data processing apparatus 有权
标题翻译：在数据处理设备中处理访问请求
公开(公告)号：US20080155167A1
公开(公告)日：2008-06-26
申请号：US11641969
申请日：2006-12-20
申请人： David Hennah Mansell , Stuart David Biles , Stephen John Hill
发明人： David Hennah Mansell , Stuart David Biles , Stephen John Hill
IPC分类号： G06F12/08
CPC分类号： G06F13/24
摘要： A data processing apparatus is provided comprising processing logic for issuing access requests when access to data is required, with each access request specifying a memory address associated with the data the subject of the access request. Access control logic is used to perform an access control operation to check for each access request whether the specified memory address is accessible by the processing logic. Further, a table is provided having a plurality of entries, each entry identifying an address range and an associated action. On occurrence of one or more predetermined events, the access control logic references the table to determine whether the specified address is within the address range identified by an entry of the table. If so, the associated action specified in that entry is invoked, whereas otherwise the access control logic causes any action indicated by the access control operation to be performed. This provides a particularly efficient mechanism for handling access requests in a variety of situations, for example within a virtualisation environment where the access requests are directed to virtual devices implemented by hypervisor software.
摘要翻译：提供了一种数据处理装置，包括当需要访问数据时发出访问请求的处理逻辑，每个访问请求指定与访问请求的对象的数据相关联的存储器地址。访问控制逻辑用于执行访问控制操作以检查每个访问请求是否由处理逻辑访问指定的存储器地址。此外，提供具有多个条目的表，每个条目标识地址范围和相关联的动作。在发生一个或多个预定事件时，访问控制逻辑引用该表以确定指定的地址是否在由表的条目标识的地址范围内。如果是，则调用在该条目中指定的相关联的动作，而否则访问控制逻辑将导致执行由访问控制操作指示的任何操作。这提供了用于在各种情况下处理访问请求的特别有效的机制，例如在其中访问请求被定向到由管理程序软件实现的虚拟设备的虚拟化环境中。

36. 发明授权

US07305534B2 Control of access to a memory by a device 有权
标题翻译：控制设备对存储器的访问
公开(公告)号：US07305534B2
公开(公告)日：2007-12-04
申请号：US10714561
申请日：2003-11-17
申请人： Simon Charles Watt , Lionel Belnet , David Hennah Mansell , Nicolas Chaussade , Peter Guy Middleton
发明人： Simon Charles Watt , Lionel Belnet , David Hennah Mansell , Nicolas Chaussade , Peter Guy Middleton
IPC分类号： G06F12/00
CPC分类号： G06F12/1491 , G06F21/6218 , G06F21/71 , G06F21/74 , G06F21/79 , G06F21/85 , G06F2221/2105 , G06F2221/2141 , G06F2221/2149
摘要： The present invention provides a data processing apparatus and method for controlling access to a memory. The data processing apparatus has a secure domain and a non-secure domain, in the secure domain the data processing apparatus having access to secure data which is not accessible in the non-secure domain. The data processing apparatus comprises a device coupled to a memory via a device bus, and operable, when an item of data in the memory is required by the device, to issue onto the device bus a memory access request pertaining to either the secure domain or the non-secure domain. The memory is operable to store data required by the device, and contains secure memory for storing secure data and non-secure memory for storing non-secure data. In accordance with the present invention, the data processing apparatus further comprises partition checking logic coupled to the device bus and operable whenever the memory access request as issued by the device pertains to the non-secure domain, to detect if the memory access request is seeking to access the secure memory and upon such detection to prevent the access specified by that memory request. This approach significantly improves the security of data contained within a secure portion of memory.
摘要翻译：本发明提供一种用于控制对存储器的访问的数据处理装置和方法。数据处理装置具有安全域和非安全域，在安全域中，数据处理装置具有对非安全域中不可访问的安全数据的访问。数据处理装置包括经由设备总线耦合到存储器的设备，并且当设备需要存储器中的数据项时，可以向设备总线发出存储器访问请求，该存储器访问请求涉及安全域或非安全域。存储器可操作以存储设备所需的数据，并且包含用于存储安全数据的安全存储器和用于存储非安全数据的非安全存储器。根据本发明，数据处理装置还包括耦合到设备总线的分区检查逻辑，每当由设备发布的存储器访问请求与非安全域相关时，可操作，以检测存储器访问请求是否正在寻找以访问安全存储器并且在这种检测时防止由该存储器请求指定的访问。这种方法显着提高了包含在存储器安全部分内的数据的安全性。

37. 发明授权

US07149862B2 Access control in a data processing apparatus 有权
标题翻译：数据处理装置中的访问控制
公开(公告)号：US07149862B2
公开(公告)日：2006-12-12
申请号：US10933478
申请日：2004-09-03
申请人： Andrew David Tune , Peter James Aldworth , Simon Charles Watt , Lionel Belnet , David Hennah Mansell
发明人： Andrew David Tune , Peter James Aldworth , Simon Charles Watt , Lionel Belnet , David Hennah Mansell
IPC分类号： G06F12/00
CPC分类号： G06F12/1441
摘要： A data processing apparatus and method are provided for controlling access to a slave device, the slave device having an address range associated therewith. The apparatus comprises control storage programmable to define a partition identifying a secure region and a non-secure region in the address range, with the data processing apparatus supporting a plurality of modes of operation including a secure mode, and the control storage being programmable only by software executing in the secure mode. A master device is arranged to issue an access request onto a bus, the access request identifying a sequence of addresses within the address range and including a control signal indicating whether the access request is a secure access request or a non-secure access request. The secure region is only accessible by a secure access request. Further, access control logic is provided which is associated with the slave device, the access control logic being operable to receive the access request from the bus and an indication of the partition from the control storage and, if the access request is a non-secure access request, to prevent access to the secure region.
摘要翻译：提供了一种用于控制对从设备的访问的数据处理设备和方法，该从设备具有与之相关联的地址范围。该装置包括可编程的控制存储器，用于定义识别地址范围中的安全区域和非安全区域的分区，数据处理设备支持包括安全模式的多种操作模式，并且控制存储器仅可由软件在安全模式下执行。主设备被布置为在总线上发出访问请求，该访问请求标识地址范围内的一系列地址，并且包括指示该访问请求是安全访问请求还是非安全访问请求的控制信号。安全区域只能通过安全访问请求访问。此外，提供与从设备相关联的访问控制逻辑，访问控制逻辑可操作以从总线接收访问请求以及来自控制存储器的分区的指示，以及如果访问请求是非安全的访问请求，以防止访问安全区域。

38. 发明授权

US07124274B2 Virtual to physical memory address mapping within a system having a secure domain and a non-secure domain 有权
标题翻译：具有安全域和非安全域的系统内的虚拟到物理内存地址映射
公开(公告)号：US07124274B2
公开(公告)日：2006-10-17
申请号：US10714560
申请日：2003-11-17
申请人： Simon Charles Watt , Christopher Bentley Dornan , Luc Orion , Nicolas Chaussade , Lionel Belnet , Stephane Eric Sebastien Brochier , David Hennah Mansell , Michael Robert Nonweiler
发明人： Simon Charles Watt , Christopher Bentley Dornan , Luc Orion , Nicolas Chaussade , Lionel Belnet , Stephane Eric Sebastien Brochier , David Hennah Mansell , Michael Robert Nonweiler
IPC分类号： G06F12/00
CPC分类号： G06F12/145 , G06F9/4812 , G06F12/1009 , G06F12/1027 , G06F21/74 , G06F2209/481
摘要： An apparatus for processing data, the apparatus comprising: a processor operable in a plurality of modes and either a secure domain or a non-secure domain including at least one secure mode being a mode in the secure domain; and at least one non-secure mode being a mode in the non-secure domain. When the processor is executing a program in a secure mode, the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor further includes a non-secure translation table base address register and a secure translation table base address register operable in the non-secure and secure domain, respectively, to indicate a region of memory storing either non-secure or secure domain memory mapping data defining how virtual addresses are translated to physical addresses within either the non-secure or secure domain.
摘要翻译：一种用于处理数据的装置，所述装置包括：可以多种模式操作的处理器和安全域或非安全域，所述安全域或非安全域包括作为安全域中的模式的至少一个安全模式; 并且至少一个非安全模式是非安全域中的模式。当处理器以安全模式执行程序时，程序可以访问当处理器以非安全模式运行时无法访问的安全数据。处理器还包括分别在非安全和安全域中操作的非安全转换表基地址寄存器和安全转换表基地址寄存器，以指示存储非安全或安全域存储器映射数据的存储器区域定义如何将虚拟地址转换为非安全或安全域中的物理地址。

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