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31. 发明授权

US4059887A Tantalum chip capacitor and method of manufacture 失效
标题翻译：钽片电容器及其制造方法
公开(公告)号：US4059887A
公开(公告)日：1977-11-29
申请号：US791511
申请日：1977-04-27
申请人： John L. Galvagni
发明人： John L. Galvagni
IPC分类号： H01G9/08 , B01J17/00
CPC分类号： H01G9/08 , Y10T29/417
摘要： The present invention is directed to a method of making a tantalum chip capacitor and the resultant capacitor device. The invention is characterized by encapsulating an essentially conventional tantalum capacitor subassembly including a body portion, the outer surface of which comprises a cathode, an anode, and an anode lead extending therefrom, within a metallic tubular case, preferably rectangular in transverse section. The subassembly is inserted within the casing and electrical connection is effected between the cathode and the case adjacent one end. An electrical connection is effected between the anode and the other end of the case. The case is thereafter filled with a polymeric insulating material in liquid form, which is thereafter caused to harden. After the polymeric material has hardened, a band, section or groove of the case is cut away to interrupt a direct current path between the ends of the case, which function as the terminals of the capacitor, the ends being maintained in structural integrity by the hardened polymeric material.
摘要翻译：本发明涉及一种制造钽片式电容器和所得电容器器件的方法。本发明的特征在于封装基本上常规的钽电容器子组件，其包括主体部分，其主体部分的外表面包括阴极，阳极和从其延伸的阳极引线，在金属管状壳体内，优选地在横截面为矩形。子组件插入壳体内，并且在阴极和邻近一端的壳体之间进行电连接。在壳体的阳极和另一端之间进行电连接。然后，该情况用液体形式的聚合物绝缘材料填充，然后使其硬化。在聚合物材料硬化之后，壳体的带状部分或凹槽被切除，以中断壳体的端部之间的直流路径，其作为电容器的端子，端部通过硬化聚合材料。

32. 发明授权

US07889020B2 Asymmetrical filter 有权
标题翻译：不对称滤波器
公开(公告)号：US07889020B2
公开(公告)日：2011-02-15
申请号：US11583361
申请日：2006-10-18
申请人： Joseph M. Hock , John L. Galvagni
发明人： Joseph M. Hock , John L. Galvagni
IPC分类号： H04B3/30 , H03H7/00
CPC分类号： H01G4/35 , H03H1/0007 , H03H7/1758 , H03H2001/0042
摘要： Disclosed is methodology and apparatus for producing an asymmetrical filter for use with implantable medical devices, and in other input filtering environments. Differing forward and reverse characteristic responses are provided by inserting a low value resistor in series with heart connecting leads so that EMI input protection may be provided without significantly reducing energy transfer from the protected device. Improved protection against voltage transients is provided with present arrangements of differentiated series impedance. Higher frequency energy is allowed out of a subject device than is allowed into such device, which allows for attenuation of undesired frequency ranges entering the filter while allowing output pulses to exit without distortion.
摘要翻译：公开了用于生产用于可植入医疗装置的非对称过滤器以及其它输入过滤环境的方法和装置。通过插入与心脏连接引线串联的低值电阻器来提供不同的正向和反向特性响应，从而可以提供EMI输入保护，而不会显着减少受保护器件的能量传输。提供了针对电压瞬态的改进的保护，具有差分串联阻抗的当前布置。比被允许进入这种装置的受检器件更高的频率能量允许衰减进入滤波器的不期望的频率范围，同时允许输出脉冲退出而不失真。

33. 发明授权

US07576968B2 Plated terminations and method of forming using electrolytic plating 有权
标题翻译：电镀终端和成型方法
公开(公告)号：US07576968B2
公开(公告)日：2009-08-18
申请号：US11503402
申请日：2006-08-10
申请人： Andrew P. Ritter , Robert Heistand, II , John L. Galvagni , John M. Hulik , Raymond T. Galasco
发明人： Andrew P. Ritter , Robert Heistand, II , John L. Galvagni , John M. Hulik , Raymond T. Galasco
IPC分类号： H01G4/228
CPC分类号： H01G4/232 , H01C1/14 , H01G4/2325 , H01G4/30
摘要： A multilayer electronic component includes a plurality of dielectric layers interleaved with a plurality of internal electrodes. Internal and/or external anchor tabs may also be selectively interleaved with the dielectric layers. Portions of the internal electrodes and anchor tabs are exposed along the periphery of the electronic component in respective groups. Each exposed portion is within a predetermined distance from other exposed portions in a given group such that termination structures may be formed by deposition and controlled bridging of a thin-film plated material among selected of the exposed internal conductive elements. Electrolytic plating may be employed in conjunction with optional cleaning and annealing steps to form directly plated portions of copper, nickel or other conductive material. Once an initial thin-film metal is directly plated to a component periphery, additional portions of different materials may be plated thereon.
摘要翻译：多层电子部件包括与多个内部电极交错的多个电介质层。内部和/或外部锚固片也可以选择性地与电介质层交错。内部电极和锚固片的部分沿着电子部件的周边分别暴露在各自的组中。每个暴露部分在给定组中与其它暴露部分在预定距离内，使得端接结构可以通过在选定的暴露的内部导电元件中的薄膜电镀材料的沉积和受控桥接形成。电解电镀可以与可选的清洁和退火步骤一起使用，以形成铜，镍或其它导电材料的直接镀覆部分。一旦将初始薄膜金属直接电镀到部件周边，则可以在其上镀上不同材料的附加部分。

34. 发明授权

US07573698B2 Window via capacitors 有权
标题翻译：通过电容窗
公开(公告)号：US07573698B2
公开(公告)日：2009-08-11
申请号：US11517536
申请日：2006-09-07
申请人： Carl L. Eggerding , Jason MacNeal , John L. Galvagni , Andrew P. Ritter
发明人： Carl L. Eggerding , Jason MacNeal , John L. Galvagni , Andrew P. Ritter
IPC分类号： H01G4/228 , H01G4/06
CPC分类号： H01G4/30 , H01G4/12 , H01G4/232
摘要： A method of forming a window via capacitor comprises a first step of providing a plurality of interleaved dielectric layers and paired electrode layers to create a multilayered arrangement characterized by top and bottom surfaces and a plurality pf side surfaces. First and second transition layer electrode portions are provided on a top surface of the multilayered arrangement on top of which a cover layer formed to define openings, or windows, therein is provided. The cover layer may be provided before device firing or may be printed on after firing using polymer or glass. Peripheral terminations are subsequently formed on the device periphery to connect selected electrode layers to respective transition layer electrode portions. Via terminations are formed in the cover layer openings, on top of which solder balls may be applied. Some of the terminations may be formed in accordance with various plating techniques as disclosed.
摘要翻译：一种通过电容器形成窗户的方法包括提供多个交错电介质层和成对电极层的第一步骤，以产生以顶表面和底表面以及多个侧表面为特征的多层布置。第一过渡层电极部分和第二过渡层电极部分设置在多层结构的顶表面上，其上形成有限定开口或其中的窗口的覆盖层。覆盖层可以在器件烧制之前提供，或者可以在使用聚合物或玻璃烧制后印刷。随后在器件外围形成外围端子，以将所选择的电极层连接到各自的过渡层电极部分。通孔端子形成在覆盖层开口中，其上可以施加焊球。一些终端可以根据所公开的各种电镀技术形成。

35. 发明授权

US07463474B2 System and method of plating ball grid array and isolation features for electronic components 有权
标题翻译：电镀球栅阵列和隔离特性的系统和方法
公开(公告)号：US07463474B2
公开(公告)日：2008-12-09
申请号：US11641546
申请日：2006-12-19
申请人： Andrew P. Ritter , John L. Galvagni , Raymond T. Galasco
发明人： Andrew P. Ritter , John L. Galvagni , Raymond T. Galasco
IPC分类号： H01G4/228
CPC分类号： H01G4/232 , H01G4/30
摘要： A multilayer electronic component includes a plurality of dielectric layers interleaved with a plurality of first and second polarity electrode layers. Internal and/or external anchor tabs may also be selectively interleaved with the dielectric layers. Portions of the electrodes and anchor tabs are exposed along the periphery of the electronic component in respective groups and thin-film plated deposition is formed thereon by electroless and/or electrolytic plating techniques. A solder dam layer is provided over a given component surface and formed to expose predetermined areas where solder barrier and flash materials may be deposited before attaching solder preforms. Some embodiments include plated terminations substantially covering selected component surfaces to facilitate with heat dissipation and signal isolation for the electronic components.
摘要翻译：多层电子部件包括与多个第一和第二极性电极层交错的多个电介质层。内部和/或外部锚固片也可以选择性地与电介质层交错。电极和锚定片的部分沿着各组的电子部件的周边露出，并且通过无电解和/或电解电镀技术在其上形成薄膜电镀沉积。在给定的组件表面上提供焊接层，并形成以暴露在附着焊料预制件之前可以沉积阻焊层和闪光材料的预定区域。一些实施例包括基本上覆盖所选择的部件表面的电镀端接件，以促进电子部件的散热和信号隔离。

36. 发明申请

US20080165468A1 VERY LOW PROFILE MULTILAYER COMPONENTS 审中-公开
标题翻译：非常低的配置文件多层组件
公开(公告)号：US20080165468A1
公开(公告)日：2008-07-10
申请号：US11958700
申请日：2007-12-18
申请人： Marianne Berolini , John L. Galvagni , Andrew P. Ritter
发明人： Marianne Berolini , John L. Galvagni , Andrew P. Ritter
IPC分类号： H01G4/005 , H05K1/16
CPC分类号： H01G4/30 , H01C7/1006 , H01C7/18 , H01C17/065 , H01G4/005 , Y10T29/49155
摘要： Methodologies are disclosed for producing multilayer electronic devices using a single screen printing mask. Plural layer devices are constructed by placing a common mask in alternating positions among alternating layers of support material such that, upon stacking of the plural layers, complimentary electrode structure is produced in alternating layers. Support material may be varied to produce different devices, including capacitors, resistors, and varistors. Multilayer electronic devices include multiple layers providing adjacent printed complimentary electrode layers having an upper surface, a lower surface, a front edge, and a back edge, and with lateral end portions of combined first and second layers trimmed so as to expose selected conductive patterns. Termination material is applied to at least such trimmed lateral end portions. A low inductance controlled equivalent series resistance (ESR) multilayer capacitor, includes at least two different pairs of electrodes, some of which have interdigitated respective side tabs. Termination material may be associated with such electrodes. In some instances, some electrodes may have dummy or anchor tabs associated with them but not electrically connected with them, to facilitate the formation of termination material at designated locations.
摘要翻译：公开了使用单一丝网印刷掩模制造多层电子器件的方法。多层装置是通过将共同的掩模放置在支撑材料的交替层之间的交替位置而构成的，使得在堆叠多层时，以交替的层产生互补的电极结构。可以改变支撑材料以产生不同的装置，包括电容器，电阻器和变阻器。多层电子器件包括提供相邻印刷互补电极层的多个层，其具有上表面，下表面，前边缘和后边缘，并且组合的第一和第二层的横向端部部分被修整以暴露所选择的导电图案。终端材料至少应用于这种修剪的侧端部。低电感控制的等效串联电阻（ESR）层叠电容器包括至少两个不同的电极对，其中一些电极具有相互指向的相应的侧片。端接材料可以与这样的电极相关联。在一些情况下，一些电极可以具有与其相关联的虚拟或锚定片，但不与它们电连接，以便于在指定位置形成终端材料。

37. 发明授权

US07161794B2 Component formation via plating technology 有权
标题翻译：通过电镀技术形成组件
公开(公告)号：US07161794B2
公开(公告)日：2007-01-09
申请号：US10900787
申请日：2004-07-28
申请人： John L. Galvagni , Jason MacNeal , Andrew P. Ritter , Robert Heistand, II , Sriram Dattaguru
发明人： John L. Galvagni , Jason MacNeal , Andrew P. Ritter , Robert Heistand, II , Sriram Dattaguru
IPC分类号： H01G4/228 , H01G2/20
CPC分类号： H01G4/232 , Y10T29/43 , Y10T29/435
摘要： Improved terminations, interconnection techniques, and inductive element features for multilayer electronic components are formed in accordance with disclosed plating techniques. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such plated termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed varying width internal electrode tabs and additional anchor tab portions. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. The combination of electrode tabs and anchor tabs may be exposed in respective arrangements to form generally discoidal portions of plated material. Such plated material may ultimately form generally round portions of ball limiting metallurgy (BLM) to which solder balls may be reflowed. The disclosed technology may be utilized with a plurality of monolithic multilayer components, including interdigitated capacitors, multilayer capacitor arrays, and integrated passive components. A variety of different plating techniques and materials may be employed in the formation of the subject self-determining plated terminations and inductive components.
摘要翻译：根据公开的电镀技术形成改进的端接，互连技术和用于多层电子部件的电感元件特征。单片组件设置有电镀端接，从而消除或大大简化了对典型厚膜端接条的需要。这种电镀终端技术消除了许多典型的终端问题，并且能够以更细的间距实现更高数量的终端，这对于较小的电子部件可能是特别有益的。受电镀的终端由暴露的变化宽度的内部电极片和附加的锚定片部分引导和锚定。这种锚定片可以相对于芯片结构位于内部或外部，以使附加的金属化电镀材料成核。电极片和锚定片的组合可以以各自的布置暴露以形成电镀材料的大致盘形部分。这种电镀材料最终可以形成通常圆球形限制冶金（BLM）的圆形部分，焊球可以回流到该部分。所公开的技术可以与多个单片多层组件一起使用，包括交错电容器，多层电容器阵列和集成无源组件。各种不同的电镀技术和材料可用于形成受试者自确定的电镀终端和电感组分。

38. 发明授权

US07054136B2 Controlled ESR low inductance multilayer ceramic capacitor 有权
标题翻译：受控ESR低电感多层陶瓷电容器
公开(公告)号：US07054136B2
公开(公告)日：2006-05-30
申请号：US10446464
申请日：2003-05-28
申请人： Andrew P. Ritter , John L. Galvagni
发明人： Andrew P. Ritter , John L. Galvagni
IPC分类号： H01G4/228 , H01G4/20
CPC分类号： H01G4/30 , H01G4/2325
摘要： A multilayer ceramic capacitor assembly capable of exhibiting low high-frequency inductance and a controlled equivalent series resistance (ESR) while maintaining a useful capacitance value includes respective pluralities of first and second electrode elements interleaved to form a stack. Controlled ESR is achieved either through inclusion of specific types of materials or through alteration of the shape of various component parts. A resistive material may be used in typical end terminations, via terminations, electrode elements or connective tab structures. Additionally, the dielectric may be made lossy so as to enhance resistivity without overly affecting device capacitance. Still further, an additional layer of resistive material may be added to an outer device surface to connect filled-via terminations to end terminations or radial resistive prints may be used to only partially fill the vias. Finally, various electrode element configurations, such as flat plate, serpentine, mesh, L-, O- or U-shaped patterns, may be employed.
摘要翻译：能够表现出低的高频电感和受控的等效串联电阻（ESR）同时保持有用的电容值的多层陶瓷电容器组件包括相互交织以形成叠层的多个第一和第二电极元件。通过包含特定类型的材料或通过改变各种组分部件的形状来实现受控ESR。电阻材料可用于典型的端接端子，通过端子，电极元件或连接片结构。此外，电介质可以是有损的，以便增强电阻率而不会过度影响器件电容。此外，可以将附加的电阻材料层添加到外部器件表面以将填充通孔端子连接到端部端子，或者径向电阻印刷可用于仅部分填充通孔。最后，可以采用诸如平板，蛇形，网状，L-，O-或U形图案的各种电极元件结构。

39. 发明授权

US06982863B2 Component formation via plating technology 有权
公开(公告)号：US06982863B2
公开(公告)日：2006-01-03
申请号：US10409036
申请日：2003-04-08
申请人： John L. Galvagni , Jason MacNeal , Andrew P. Ritter , Robert Heistand, II , Sriram Dattaguru
发明人： John L. Galvagni , Jason MacNeal , Andrew P. Ritter , Robert Heistand, II , Sriram Dattaguru
IPC分类号： H01G4/228 , H01G4/32
CPC分类号： H01G4/232 , Y10T29/43 , Y10T29/435
摘要： Improved terminations, interconnection techniques, and inductive element features for multilayer electronic components are formed in accordance with disclosed plating techniques. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such plated termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed varying width internal electrode tabs and additional anchor tab portions. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. The combination of electrode tabs and anchor tabs may be exposed in respective arrangements to form generally discoidal portions of plated material. Such plated material may ultimately form generally round portions of ball limiting metallurgy (BLM) to which solder balls may be reflowed. The disclosed technology may be utilized with a plurality of monolithic multilayer components, including interdigitated capacitors, multilayer capacitor arrays, and integrated passive components. A variety of different plating techniques and materials may be employed in the formation of the subject self-determining plated terminations and inductive components.

40. 发明授权

US06757152B2 Cascade capacitor 失效
标题翻译：级联电容
公开(公告)号：US06757152B2
公开(公告)日：2004-06-29
申请号：US10234972
申请日：2002-09-04
申请人： John L. Galvagni , Robert Heistand, II , Georghe Korony
发明人： John L. Galvagni , Robert Heistand, II , Georghe Korony
IPC分类号： H01G4228
CPC分类号： H01G4/228 , H01G2/00 , H01G4/30 , H01G4/385 , H01L23/642 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , Y10T29/43 , Y10T29/435 , Y10T29/49082 , Y10T29/49124 , Y10T29/49128 , Y10T29/4913 , H01L2924/00
摘要： Multi-layer and cascade capacitors for use in high frequency applications and other environments are disclosed. The subject capacitor may have multiple capacitor components or aspects thereof in an integrated package. Such components may include, for example, thin film BGA components, interdigitated capacitor (IDC) configurations, double-layer electrochemical capacitors, surface mount tantalum products, multilayer capacitors, single layer capacitors, and others. Exemplary embodiments of the present subject matter preferably encompass at least certain aspects of thin film BGA techniques and/or IDC-style configurations. Features for attachment and interconnection are provided that facilitate low ESL while maintaining a given capacitance value. Additional advantages include low ESR and decoupling performance over a broad band of operational frequencies. More particularly, the presently disclosed technology provides for exemplary capacitors that may function over a frequency range from kilohertz up to several gigahertz, and that may also be characterized by a wide range of capacitance values. An additionally disclosed feature of the present subject matter is to incorporate dielectric layers of varied thicknesses to broaden the resonancy curve associated with a particular configuration.
摘要翻译：公开了用于高频应用和其他环境的多层和级联电容器。本集电容器可以在集成封装中具有多个电容器组件或其方面。这样的部件可以包括例如薄膜BGA部件，叉指电容器（IDC）配置，双层电化学电容器，表面贴装钽产品，多层电容器，单层电容器等。本主题的示例性实施例优选地包括薄膜BGA技术和/或IDC式配置的至少某些方面。提供用于附接和互连的特征，其在保持给定的电容值的同时促进低ESL。另外的优点包括在宽频带工作频率下的低ESR和去耦性能。更具体地，本公开的技术提供了可以在从千赫兹到几千兆赫兹的频率范围内起作用的示例性电容器，并且还可以通过宽范围的电容值来表征。本主题的另外公开的特征是结合不同厚度的电介质层以扩大与特定配置相关联的共振曲线。

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