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31. 发明申请

US20140239498A1 SILICIDED TRENCH CONTACT TO BURIED CONDUCTIVE LAYER 审中-公开
标题翻译：硅胶触点接触到导电层
公开(公告)号：US20140239498A1
公开(公告)日：2014-08-28
申请号：US13570737
申请日：2012-08-09
申请人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
发明人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L23/48 , H01L23/482
CPC分类号： H01L21/743 , H01L21/28518 , H01L21/76224 , H01L21/8249 , H01L27/0623 , H01L29/41 , H01L2924/0002 , H01L2924/00
摘要： A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.
摘要翻译：沟槽接触硅化物形成在接触沟槽的内壁上，该接触沟槽的内壁到达半导体衬底中的掩埋导电层，以减小通孔结构的寄生电阻。沟槽接触硅化物形成在底部，沟槽的侧壁上以及在半导体衬底的顶表面的一部分上。沟槽随后填充有中间线（MOL）电介质。可以在沟槽接触硅化物上形成接触通孔。沟槽接触硅化物可以通过与金属层的单一硅化反应或通过与多个金属层的多次硅化反应形成。

32. 发明申请

US20120074469A1 ASYMMETRIC WEDGE JFET, RELATED METHOD AND DESIGN STRUCTURE 有权
标题翻译：非对称楔形结构，相关方法和设计结构
公开(公告)号：US20120074469A1
公开(公告)日：2012-03-29
申请号：US12888828
申请日：2010-09-23
申请人： Xuefeng Liu , Richard A. Phelps , Robert M. Rassel , Xiaowei Tian
发明人： Xuefeng Liu , Richard A. Phelps , Robert M. Rassel , Xiaowei Tian
IPC分类号： H01L29/80 , G06F17/50 , H01L21/337
CPC分类号： H01L29/772 , G06F17/50 , H01L29/0649 , H01L29/0843 , H01L29/1066 , H01L29/66901 , H01L29/808
摘要： A junction gate field-effect transistor (JFET) for an integrated circuit (IC) chip is provided comprising a source region, a drain region, a lower gate, and a channel, with an insulating shallow trench isolation (STI) region extending from an inner edge of an upper surface of the source region to an inner edge of an upper surface of the drain region, without an intentionally doped region, e.g., an upper gate, coplanar with an upper surface of the IC chip between the source/drain regions. In addition, an asymmetrical quasi-buried upper gate can be included, disposed under a portion of the STI region, but not extending under a portion of the STI region proximate to the drain region. Embodiments of this invention also include providing an implantation layer, under the source region, to reduce Ron. A related method and design structure are also disclosed.
摘要翻译：提供了一种用于集成电路（IC）芯片的结栅场效应晶体管（JFET），其包括源极区，漏极区，下栅极和沟道，其中绝缘浅沟槽隔离（STI）区域从源区域的上表面的内边缘到漏极区域的上表面的内边缘，而没有有意掺杂的区域，例如上栅极，与源极/漏极区域之间的IC芯片的上表面共面。此外，可以包括设置在STI区域的一部分下方的不对称的准掩埋的上栅极，但不在靠近漏极区域的STI区域的一部分下方延伸。本发明的实施例还包括在源极区域下提供注入层以减少Ron。还公开了相关的方法和设计结构。

33. 发明授权

US08035190B2 Semiconductor devices 有权
标题翻译：半导体器件
公开(公告)号：US08035190B2
公开(公告)日：2011-10-11
申请号：US12725792
申请日：2010-03-17
申请人： Xuefeng Liu , Robert M. Rassel , Steven H. Voldman
发明人： Xuefeng Liu , Robert M. Rassel , Steven H. Voldman
IPC分类号： H01L29/00
CPC分类号： H01L29/7436 , H01L27/0262 , H01L29/7378
摘要： A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The device further comprises a reach-through structure connecting the first and second sub-collectors and an N-well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. The device further comprises N+ diffusion regions in contact with the N-well, a P+ diffusion region in contact with the N-well, and shallow trench isolation structures between the N+ and P+ diffusion regions.
摘要翻译：一种器件包括形成在衬底的上部中的第一子集电极和形成在第一外延层的上部中的第一外延层和第二子集电极的下部，以及第二外延层的下部。该装置还包括连接第一和第二子集电器的连通结构和形成在第二外延层的一部分中并与第二子集电器和达到通孔结构接触的N阱。该装置还包括与N阱接触的N +扩散区，与N阱接触的P +扩散区，以及N +和P +扩散区之间的浅沟槽隔离结构。

34. 发明授权

US07989306B2 Method of forming alternating regions of Si and SiGe or SiGeC on a buried oxide layer on a substrate 有权
标题翻译：在衬底上的掩埋氧化物层上形成Si和SiGe或SiGeC的交替区域的方法
公开(公告)号：US07989306B2
公开(公告)日：2011-08-02
申请号：US11770908
申请日：2007-06-29
申请人： Xuefeng Liu , Robert M. Rassel , Steven H. Voldman
发明人： Xuefeng Liu , Robert M. Rassel , Steven H. Voldman
IPC分类号： H01L21/76 , H01L21/322 , H01L21/20 , H01L21/36 , H01L23/58 , H01L21/02 , H01L29/30
CPC分类号： H01L21/84 , H01L21/76243 , H01L21/76264 , H01L21/823807 , H01L21/8249 , H01L27/0635 , H01L27/0652 , H01L27/092 , H01L27/1203 , H01L27/1207
摘要： Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions.
摘要翻译：半导体结构和形成半导体结构的方法，更具体地涉及用于形成用于SOI / SiGe器件的SiGe和/或SiGeC掩埋层的结构和方法。集成结构包括具有交替的Si和SiGe或SiGeC区域的不连续的掩埋层。该结构还包括在Si和SiGe或SiGeC区域之间的界面处的隔离结构，以减少交替区域之间的缺陷。器件与Si和SiGe或SiGeC区域相关联。

35. 发明申请

US20090001414A1 STRUCTURES AND METHODS OF FORMING SIGE AND SIGEC BURIED LAYER FOR SOI/SIGE TECHNOLOGY 有权
标题翻译：用于SOI / SIGE技术的形成信号和SIGEC覆层的结构和方法
公开(公告)号：US20090001414A1
公开(公告)日：2009-01-01
申请号：US11770908
申请日：2007-06-29
申请人： Xuefeng Liu , Robert M. Rassel , Steven H. Voldman
发明人： Xuefeng Liu , Robert M. Rassel , Steven H. Voldman
IPC分类号： H01L29/12 , H01L21/20
CPC分类号： H01L21/84 , H01L21/76243 , H01L21/76264 , H01L21/823807 , H01L21/8249 , H01L27/0635 , H01L27/0652 , H01L27/092 , H01L27/1203 , H01L27/1207
摘要： Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions.
摘要翻译：半导体结构和形成半导体结构的方法，更具体地涉及用于形成用于SOI / SiGe器件的SiGe和/或SiGeC掩埋层的结构和方法。集成结构包括具有交替的Si和SiGe或SiGeC区域的不连续的掩埋层。该结构还包括在Si和SiGe或SiGeC区域之间的界面处的隔离结构，以减少交替区域之间的缺陷。器件与Si和SiGe或SiGeC区域相关联。

36. 发明申请

US20080179703A1 SCHOTTKY BARRIER DIODES FOR MILLIMETER WAVE SiGe BICMOS APPLICATIONS 有权
标题翻译：肖特基二极管适用于千兆波SiGe BICMOS应用
公开(公告)号：US20080179703A1
公开(公告)日：2008-07-31
申请号：US11853973
申请日：2007-09-12
申请人： Jeffrey B. Johnson , Xuefeng Liu , Bradley A. Orner , Robert M. Rassel
发明人： Jeffrey B. Johnson , Xuefeng Liu , Bradley A. Orner , Robert M. Rassel
IPC分类号： H01L29/872 , H01L21/329
CPC分类号： H01L29/872 , H01L21/8249 , H01L27/0635 , H01L27/0814 , H01L29/161 , H01L29/47 , H01L29/66143
摘要： The structure for millimeter-wave frequency applications, includes a Schottky barrier diode (SBD) with a cutoff frequency (FC) above 1.0 THz formed on a SiGe BiCMOS wafer. A method is also contemplated for forming a Schottky barrier diode on a SiGe BiCMOS wafer, including forming a structure which provides a cutoff frequency (Fc) above about 1.0 THz. In embodiments, the structure which provides a cutoff frequency (Fc) above about 1.0 THz may include an anode having an anode area which provides a cutoff frequency (FC) above about 1.0 THz, an n-epitaxial layer having a thickness which provides a cutoff frequency (FC) above about 1.0 THz, a p-type guardring at an energy and dosage which provides a cutoff frequency (FC) above about 1.0 THz, the p-type guardring having a dimension which provides a cutoff frequency (FC) above about 1.0 THz, and a well tailor with an n-type dopant which provides a cutoff frequency (FC) above about 1.0 THz.
摘要翻译：毫米波频率应用的结构包括在SiGe BiCMOS晶片上形成的截止频率（F SUB）高于1.0THz的肖特基势垒二极管（SBD）。还考虑了在SiGe BiCMOS晶片上形成肖特基势垒二极管的方法，包括形成提供高于约1.0THz的截止频率（F SUB）的结构。在实施例中，提供约1.0THz以上的截止频率（F SUB）的结构可以包括具有提供上述截止频率（F SUB C）的阳极区域的阳极约1.0THz，具有提供高于约1.0THz的截止频率（F SUB）的厚度的n外延层，以能量和剂量提供截止频率（F）的p型防护在约1.0THz以上的p型防护装置，具有提供高于约1.0THz的截止频率（F SUB C）的尺寸，以及具有n 型掺杂剂，其在约1.0THz以上提供截止频率（F C C）。

37. 发明申请

US20080124883A1 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE 审中-公开
公开(公告)号：US20080124883A1
公开(公告)日：2008-05-29
申请号：US11941452
申请日：2007-11-16
申请人： Douglas D. COOLBAUGH , Alvin J. Joseph , Seong-dong Kim , Louis D. Laozerotti , Xuefeng Liu , Robert M. Rassel
发明人： Douglas D. COOLBAUGH , Alvin J. Joseph , Seong-dong Kim , Louis D. Laozerotti , Xuefeng Liu , Robert M. Rassel
IPC分类号： H01L21/8222
CPC分类号： H01L27/0814 , H01L27/0664 , H01L27/0823 , H01L29/0821 , H01L29/7371 , H01L29/868
摘要： A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.

38. 发明授权

US07329940B2 Semiconductor structure and method of manufacture 有权
标题翻译：半导体结构及制造方法
公开(公告)号：US07329940B2
公开(公告)日：2008-02-12
申请号：US11163882
申请日：2005-11-02
申请人： Douglas D. Coolbaugh , Alvin J. Joseph , Seong-dong Kim , Louis D. Lanzerotti , Xuefeng Liu , Robert M. Rassel
发明人： Douglas D. Coolbaugh , Alvin J. Joseph , Seong-dong Kim , Louis D. Lanzerotti , Xuefeng Liu , Robert M. Rassel
IPC分类号： H01L27/082
CPC分类号： H01L27/0814 , H01L27/0664 , H01L27/0823 , H01L29/0821 , H01L29/7371 , H01L29/868
摘要： A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.
摘要翻译：一种结构包括具有形成在具有第一厚度的第一区域中的第一子集电极的单晶片和形成在具有不同于第一厚度的第二厚度的第二区域中的第二子集电极。还可以设想一种方法，其包括提供包括第一层并在第一层中形成第一掺杂区的衬底。该方法还包括在第一层上形成第二层并在第二层中形成第二掺杂区域。第二掺杂区形成在与第一掺杂区不同的深度。该方法还包括在第一层中形成第一通道并在第二层中形成第二通道以将第一通道连接到表面。

39. 发明申请

US20070278618A1 METHOD AND STRUCTURE FOR SYMMETRIC CAPACITOR FORMATION 有权
标题翻译：对称电容器形成的方法和结构
公开(公告)号：US20070278618A1
公开(公告)日：2007-12-06
申请号：US11421774
申请日：2006-06-02
申请人： David S. Collins , Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Xuefeng Liu
发明人： David S. Collins , Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H01L29/00
CPC分类号： H01L27/0805
摘要： A structure and associated method for forming a structure. The structure comprises a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises a first dopant having a first polarity. The second doped region forms a first electrode of a capacitor. The third doped region forms a second electrode of the capacitor. Each of the second doped region and the third doped region comprises a second dopant having a second polarity. The first shallow trench isolation structure is formed between the second doped region and the third doped region. The capacitor comprises a main capacitance. The structure comprises a first parasitic capacitance and a second parasitic capacitance. The first parasitic capacitance is about equal to the second parasitic capacitance.
摘要翻译：用于形成结构的结构和相关联的方法。该结构包括形成在衬底内的第一掺杂区域，第二掺杂区域，第三掺杂区域和第一浅沟槽隔离结构。第一掺杂区域包括具有第一极性的第一掺杂剂。第二掺杂区域形成电容器的第一电极。第三掺杂区域形成电容器的第二电极。第二掺杂区域和第三掺杂区域中的每一个包括具有第二极性的第二掺杂剂。第一浅沟槽隔离结构形成在第二掺杂区和第三掺杂区之间。电容器包括主电容。该结构包括第一寄生电容和第二寄生电容。第一寄生电容约等于第二寄生电容。

40. 发明授权

US07402890B2 Method for symmetric capacitor formation 有权
标题翻译：对称电容器形成方法
公开(公告)号：US07402890B2
公开(公告)日：2008-07-22
申请号：US11421774
申请日：2006-06-02
申请人： David S. Collins , Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Xuefeng Liu
发明人： David S. Collins , Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H01L29/00
CPC分类号： H01L27/0805
摘要： A structure and associated method for forming a structure. The structure comprises a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises a first dopant having a first polarity. The second doped region forms a first electrode of a capacitor. The third doped region forms a second electrode of the capacitor. Each of the second doped region and the third doped region comprises a second dopant having a second polarity. The first shallow trench isolation structure is formed between the second doped region and the third doped region. The capacitor comprises a main capacitance. The structure comprises a first parasitic capacitance and a second parasitic capacitance. The first parasitic capacitance is about equal to the second parasitic capacitance.
摘要翻译：用于形成结构的结构和相关联的方法。该结构包括形成在衬底内的第一掺杂区域，第二掺杂区域，第三掺杂区域和第一浅沟槽隔离结构。第一掺杂区域包括具有第一极性的第一掺杂剂。第二掺杂区域形成电容器的第一电极。第三掺杂区域形成电容器的第二电极。第二掺杂区域和第三掺杂区域中的每一个包括具有第二极性的第二掺杂剂。第一浅沟槽隔离结构形成在第二掺杂区和第三掺杂区之间。电容器包括主电容。该结构包括第一寄生电容和第二寄生电容。第一寄生电容约等于第二寄生电容。

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