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31. 发明授权

US06288426B1 Thermal conductivity enhanced semiconductor structures and fabrication processes 有权
标题翻译：热导率增强的半导体结构和制造工艺
公开(公告)号：US06288426B1
公开(公告)日：2001-09-11
申请号：US09514106
申请日：2000-02-28
申请人： Robert J. Gauthier, Jr. , Dominic J. Schepis , William R. Tonti , Steven H. Voldman
发明人： Robert J. Gauthier, Jr. , Dominic J. Schepis , William R. Tonti , Steven H. Voldman
IPC分类号： H01L2900
CPC分类号： H01L29/78648 , H01L21/76264 , H01L21/76286 , H01L21/763 , H01L23/3677 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： Silicon is formed at selected locations on a substrate during fabrication of selected electronic components. A dielectric separation region is formed within the top silicon layer, and filled with a thermally conductive material. A liner material may be optionally deposited prior to depositing the thermally conductive material. In a second embodiment, a horizontal layer of thermally conductive material is also deposited in an oxide layer or bulk silicon layer below the top layer of silicon.
摘要翻译：在选择的电子部件的制造期间，在基板上的选定位置处形成硅。介电分离区形成在顶层硅层内，并填充有导热材料。衬里材料可以在沉积导热材料之前任选地沉积。在第二实施例中，水平导热材料层也沉积在硅顶层之下的氧化物层或体硅层中。

32. 发明授权

US06232163B1 Method of forming a semiconductor diode with depleted polysilicon gate structure 有权
标题翻译：形成具有耗尽的多晶硅栅结构的半导体二极管的方法
公开(公告)号：US06232163B1
公开(公告)日：2001-05-15
申请号：US09362549
申请日：1999-07-28
申请人： Steven H. Voldman , Robert J. Gauthier, Jr. , Jeffrey S. Brown
发明人： Steven H. Voldman , Robert J. Gauthier, Jr. , Jeffrey S. Brown
IPC分类号： H01L218238
CPC分类号： H01L27/0811 , H01L29/7391 , H01L2924/0002 , H01L2924/00
摘要： A high voltage tolerant diode structure for mixed-voltage, and mixed signal and analog/digital applications. The preferred silicon diode includes a polysilicon gate structure on at least one dielectric film layer on a semiconductor (silicon) layer or body. A well or an implanted area is formed in a bulk semiconductor substrate or in a surface silicon layer on an SOI wafer. Voltage applied to the polysilicon gate film, electrically depletes it, reducing voltage stress across the dielectric film. An intrinsic polysilicon film may be counter-doped, implanted with a low doped implantation, implanted with a low doped source/drain implant, or with a low doped MOSFET LDD or extension implant. Alternatively, a block mask may be formed over the gate structure when defining the depleted-polysilicon gate silicon diode to form low series resistance diode implants, preventing over-doping the film. Optionally, a hybrid photoresist method may be used to form higher doped edge implants in the silicon to reduce diode series resistance without a block mask.
摘要翻译：用于混合电压，混合信号和模拟/数字应用的高耐压二极管结构。优选的硅二极管包括在半导体（硅）层或主体上的至少一个电介质膜层上的多晶硅栅极结构。阱体或植入区域形成在SOI半导体衬底或SOI晶片的表面硅层中。施加到多晶硅栅极膜的电压，电耗电，降低电介质膜两端的电压。本征多晶硅膜可以是反掺杂的，注入低掺杂注入，注入低掺杂源/漏注入，或者与低掺杂的MOSFET LDD或延伸注入。或者，当限定耗尽多晶硅栅极硅二极管以形成低串联电阻二极管植入物时，可以在栅极结构上形成块掩模，防止膜过度掺杂。可选地，可以使用混合光致抗蚀剂方法在硅中形成更高掺杂的边缘注入，以减少二极管串联电阻而不使用块掩模。

33. 发明授权

US6097069A Method and structure for increasing the threshold voltage of a corner device 失效
标题翻译：提高拐角装置阈值电压的方法和结构
公开(公告)号：US6097069A
公开(公告)日：2000-08-01
申请号：US102196
申请日：1998-06-22
申请人： Jeffrey S. Brown , Robert J. Gauthier , Steven H. Voldman
发明人： Jeffrey S. Brown , Robert J. Gauthier , Steven H. Voldman
IPC分类号： H01L29/78 , H01L21/28 , H01L21/8238 , H01L29/423 , H01L29/76 , H01L29/00
CPC分类号： H01L21/28167 , H01L21/8238 , H01L29/42368
摘要： A structure for increasing the threshold voltage of a corner device, particularly for shallow trench isolation having narrow devices. An FET comprises a substrate having a channel formed therein under a gate between spaced source and drain regions. A trench isolation region is formed in the substrate around the transistor and on opposite sides of the channel to isolate the transistor from other devices formed in the substrate, with the trench isolation region forming first and second junction corner devices with opposite sides of the channel. A first dielectric layer is formed under the gate and over the channel of the field effect transistor to form a gate insulator for the transistor. A second corner edge dielectric layer is formed under the gate structure and over the first and second corner devices, such that the corner edge dielectric layer increases the thickness of dielectric over each corner device and thus increases the threshold voltage (Vt) and edge dielectric breakdown and decreases MOSFET corner gate-induced drain leakage.
摘要翻译：一种用于增加角装置的阈值电压的结构，特别是对于具有窄装置的浅沟槽隔离。 FET包括在间隔开的源极和漏极区之间的栅极下方形成有沟道的衬底。沟槽隔离区形成在晶体管周围的衬底和通道的相对侧上，以将晶体管与形成在衬底中的其它器件隔离，其中沟槽隔离区形成具有通道相对侧的第一和第二接合角器件。在场效应晶体管的栅极和沟道之下形成第一介电层，以形成晶体管的栅极绝缘体。在栅极结构之下和第一和第二角部器件之上形成第二角边缘电介质层，使得角部边缘电介质层增加每个拐角器件上的电介质厚度，从而增加阈值电压（Vt）和边缘电介质击穿并降低MOSFET栅极引起的漏极泄漏。

34. 发明授权

US6034397A Silicon-on-insulator body- and dual gate-coupled diode for electrostatic discharge (ESD) applications 失效
标题翻译：用于静电放电（ESD）应用的绝缘体上硅体和双栅极耦合二极管
公开(公告)号：US6034397A
公开(公告)日：2000-03-07
申请号：US2670
申请日：1998-01-05
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： H01L27/02 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/0255 , H01L27/0251 , H01L2924/0002
摘要： A body and dual gate coupled diode for silicon-on-insulator (SOI) technology is disclosed. The body and dual gate coupled diode is formed from a SOI field-effect transistor (FET) structure. The source of the SOI FET structure forms the first terminal of the diode. The drain of the SOI FET structure forms the second terminal of the diode. The SOI FET structure includes two gates, which are tied to the body of the SOI FET structure. An SOI circuit comprising at least one body and dual gate coupled diode formed from the SOI FET structure provides electrostatic discharge (ESD) protection.
摘要翻译：公开了一种用于绝缘体上硅（SOI）技术的主体和双栅耦合二极管。主体和双栅极耦合二极管由SOI场效应晶体管（FET）结构形成。 SOI FET结构的源极形成二极管的第一个端子。 SOI FET结构的漏极形成二极管的第二端子。 SOI FET结构包括两个栅极，其连接到SOI FET结构的主体。包括由SOI FET结构形成的至少一个主体和双栅极耦合二极管的SOI电路提供静电放电（ESD）保护。

35. 发明授权

US6034388A Depleted polysilicon circuit element and method for producing the same 失效
标题翻译：耗尽多晶硅电路元件及其制造方法
公开(公告)号：US6034388A
公开(公告)日：2000-03-07
申请号：US79846
申请日：1998-05-15
申请人： Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven H. Voldman
发明人： Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven H. Voldman
IPC分类号： H01L21/334 , H01L21/762 , H01L21/8238 , H01L27/06 , H01L27/12 , H01L29/94 , H01L29/76
CPC分类号： H01L29/66181 , H01L21/76237 , H01L21/76264 , H01L21/823842 , H01L21/82385 , H01L27/0629 , H01L27/1203 , H01L29/94 , H01L21/76283 , Y10S257/907
摘要： A circuit element comprising a semiconductor substrate. A well region of a first conductivity type is formed in a surface of the substrate. A dielectric film is formed on the substrate. A gate conductor of the first conductivity type is formed on the dielectric film over the well region of the substrate. The gate conductor is formed of a polycrystalline silicon film. The gate conductor has an impurity concentration substantially lower than a standard impurity concentration for the gate conductor of an MOS device. A polycrystalline silicon edge spacer is formed on each side of the gate conductor. A first pair of first conductivity type impurity diffusion regions are formed adjacent to the polycrystalline silicon edge spacers. The polycrystalline silicon film and edge spacers lie on a portion of the substrate between the first pair of first conductivity type impurity diffusion regions. The first pair of first conductivity type impurity diffusion regions have an impurity concentration substantially lower than the standard impurity concentration for the gate conductor of an MOS device. The gate conductor and the first pair of first conductivity type impurity diffusion regions may be formed by a single implantation step. Applications include ESD protection, analog applications, peripheral input/output circuitry, decoupling capacitors, and resistor ballasting.
摘要翻译：一种包括半导体衬底的电路元件。第一导电类型的阱区形成在衬底的表面中。在基板上形成电介质膜。在衬底的阱区上的电介质膜上形成第一导电类型的栅极导体。栅极导体由多晶硅膜形成。栅极导体的杂质浓度基本上低于MOS器件的栅极导体的标准杂质浓度。在栅极导体的每一侧上形成多晶硅边缘隔离物。第一对第一导电型杂质扩散区形成在与多晶硅边缘隔离物相邻的位置。多晶硅膜和边缘隔离物位于第一对第一导电型杂质扩散区之间的衬底的一部分上。第一对第一导电型杂质扩散区的杂质浓度基本上低于MOS器件的栅极导体的标准杂质浓度。可以通过单个注入步骤形成栅极导体和第一对第一导电型杂质扩散区。应用包括ESD保护，模拟应用，外围输入/输出电路，去耦电容和电阻镇流器。

36. 发明授权

US5872378A Dual thin oxide ESD network for nonvolatile memory applications 失效
标题翻译：用于非易失性存储器应用的双重薄氧化物ESD网络
公开(公告)号：US5872378A
公开(公告)日：1999-02-16
申请号：US834559
申请日：1997-04-07
申请人： Russell E. Rose , Robert C. Szafranski , Steven H. Voldman
发明人： Russell E. Rose , Robert C. Szafranski , Steven H. Voldman
IPC分类号： H01L21/8247 , H01L27/02 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/0248
摘要： An Electric Static Discharge (ESD) protection network for nonvolatile memory using a high voltage dual thin oxide MOSFET. In one aspect, there is a dual oxide electric static discharge (ESD) protective network for nonvolatile memory in which ESD protection is provided using a thick oxide PFET in a thick epitaxial layer with sequence independent circuitry. The dual oxide ESD network includes a high voltage PFET ESD network for 12 V to 5 V applications as well as a low voltage PFET network 5 V to 3 V applications taking advantage of dual oxides supported by the disclosed technology. The circuit saves space, is migratable, improves reliability, and it is voltage differential independent.
摘要翻译：使用高电压双薄氧化物MOSFET的非易失性存储器的静电放电（ESD）保护网络。在一个方面，存在用于非易失性存储器的双重氧化物静电放电（ESD）保护网络，其中使用具有序列独立电路的厚外延层中的厚氧化物PFET来提供ESD保护。双氧化物ESD网络包括用于12 V至5 V应用的高压PFET ESD网络，以及利用所公开技术支持的双重氧化物的低压PFET网络5 V至3 V应用。电路节省空间，可迁移，提高可靠性，是独立的电压差。

37. 发明授权

US09087925B2 Si and SiGeC on a buried oxide layer on a substrate 有权
标题翻译： Si和SiGeC在基底上的掩埋氧化物层上
公开(公告)号：US09087925B2
公开(公告)日：2015-07-21
申请号：US13150440
申请日：2011-06-01
申请人： Xuefeng Liu , Robert M. Rassel , Steven H. Voldman
发明人： Xuefeng Liu , Robert M. Rassel , Steven H. Voldman
IPC分类号： H01L21/84 , H01L21/762 , H01L27/12 , H01L21/8238 , H01L21/8249 , H01L27/06 , H01L27/092
CPC分类号： H01L21/84 , H01L21/76243 , H01L21/76264 , H01L21/823807 , H01L21/8249 , H01L27/0635 , H01L27/0652 , H01L27/092 , H01L27/1203 , H01L27/1207
摘要： Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions.
摘要翻译：半导体结构和形成半导体结构的方法，更具体地涉及用于形成用于SOI / SiGe器件的SiGe和/或SiGeC掩埋层的结构和方法。集成结构包括具有交替的Si和SiGe或SiGeC区域的不连续的掩埋层。该结构还包括在Si和SiGe或SiGeC区域之间的界面处的隔离结构，以减少交替区域之间的缺陷。器件与Si和SiGe或SiGeC区域相关联。

38. 发明授权

US08519402B2 Structure, structure and method of latch-up immunity for high and low voltage integrated circuits 有权
公开(公告)号：US08519402B2
公开(公告)日：2013-08-27
申请号：US12183462
申请日：2008-07-31
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： H01L27/108
CPC分类号： H01L27/092 , H01L21/823892 , H01L27/0921 , H01L29/0638 , H01L29/0653 , H01L29/0847 , H01L29/086 , H01L29/0878 , H01L29/1045 , H01L29/1079 , H01L29/1083 , H01L29/66833 , H01L29/7816 , H01L29/7835 , H01L29/7923
摘要： Design structures, structures and methods of manufacturing structures for providing latch-up immunity for mixed voltage integrated circuits. The structure includes a diffused N-Tub structure embedded in a P-wafer and provided below a retrograde N-well to a non-isolated CMOS logic.

39. 发明授权

US08301288B2 Optimized scheduling based on sensitivity data 有权
标题翻译：基于灵敏度数据优化调度
公开(公告)号：US08301288B2
公开(公告)日：2012-10-30
申请号：US10710065
申请日：2004-06-16
申请人： Brian T. Denton , Cuc K Huynh , Shreesh S. Tandel , Steven H. Voldman
发明人： Brian T. Denton , Cuc K Huynh , Shreesh S. Tandel , Steven H. Voldman
IPC分类号： G06F19/00 , G05B13/02 , H01L21/00 , H01L21/66
CPC分类号： G06Q10/06
摘要： A scheduling optimizer system, method and program product that analyzes a device for sensitivities, such as ESD sensitivities, and allows for modification of a floor schedule of the assembly unit of the device based on the sensitivity of the device while improving the overall performance of the assembly unit are disclosed. The scheduling optimizer analyzes sensitivity data for a device during operation of the assembly unit on the floor schedule. The floor schedule is then optimized based on the analyzed sensitivity data.
摘要翻译：调度优化器系统，方法和程序产品，用于分析设备的灵敏度，如ESD灵敏度，并允许基于设备的灵敏度修改设备的组装单元的楼层调度，同时提高整体性能组装单元被公开。调度优化器根据楼层进度分析装配单元运行期间设备的灵敏度数据。然后根据分析的灵敏度数据优化楼层进度。

40. 发明授权

US08105924B2 Deep trench based far subcollector reachthrough 失效
标题翻译：深沟渠远极子集线器达到
公开(公告)号：US08105924B2
公开(公告)日：2012-01-31
申请号：US12691320
申请日：2010-01-21
申请人： Bradley A. Orner , Robert M. Rassel , David C. Sheridan , Steven H. Voldman
发明人： Bradley A. Orner , Robert M. Rassel , David C. Sheridan , Steven H. Voldman
IPC分类号： H01L21/04
CPC分类号： H01L21/763 , H01L29/0821 , H01L29/66272 , H01L29/732
摘要： A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.
摘要翻译：通过将掺杂剂离子注入到初始半导体衬底的区域中，随后半导体材料的外延生长，形成位于超过常规离子注入范围的深度的远的子集电极或掩埋掺杂半导体层。通过从沉积在邻接远子集电极的至少一个深沟槽中的掺杂材料层向外扩散掺杂剂形成远子集电极的到达区域。穿通区域可形成为围绕至少一个深沟槽或仅在至少一个深沟槽的一侧上。如果至少一个沟槽的内部电连接到通孔区域，则可以在至少一个沟槽内的掺杂填充材料上形成金属接触。如果不是，则在与接触区域接触的次级通过区域上形成金属接触。

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