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31. 发明申请

US20050254282A1 REFERENCE GENERATOR SYSTEM AND METHODS FOR READING FERROELECTRIC MEMORY CELLS USING REDUCED BITLINE VOLTAGES 有权
标题翻译：参考发电机系统和使用减少的电子伏特读取电磁记忆体的方法
公开(公告)号：US20050254282A1
公开(公告)日：2005-11-17
申请号：US10847412
申请日：2004-05-17
申请人： Scott Summerfelt , Hugh McAdams
发明人： Scott Summerfelt , Hugh McAdams
IPC分类号： G11C5/14 , G11C11/22
CPC分类号： G11C11/22 , G11C5/147
摘要： Methods (200) and systems (108) are provided for reading data from ferroelectric memory cells (106) in which charge is removed from a sense amp input (SABL/SABLB) prior to application of a plateline signal (PL) to the target cell capacitor (CFE). Where the sense amp input (SABL/SABLB) is initially precharged to zero volts, the extraction of charge provides a negative voltage on the data bitline (BL/BLB) when the plateline signal (PL) is applied, allowing adequate voltage to be applied across the cell capacitor (CFE) together with reduced plateline voltages (PL).
摘要翻译：提供了方法（200）和系统（108），用于从将铁电信号（PL）施加到目标单元之前从感测放大器输入（SABL / SABLB）去除电荷的铁电存储器单元（106）读取数据电容器（C FE）。在感测放大器输入（SABL / SABLB）最初预充电到零伏的情况下，当施加平行线信号（PL）时，提取电荷在数据位线（BL / BLB）上提供负电压，允许施加足够的电压跨越电池电容器（C SUB FE）以及降低的线路电压（PL）。

32. 发明授权

US06867447B2 Ferroelectric memory cell and methods for fabricating the same 有权
标题翻译：铁电存储单元及其制造方法
公开(公告)号：US06867447B2
公开(公告)日：2005-03-15
申请号：US10441619
申请日：2003-05-20
申请人： Scott Summerfelt
发明人： Scott Summerfelt
IPC分类号： H01L21/336 , H01L21/8246 , H01L27/115 , H01L29/76
CPC分类号： H01L27/11502 , H01L27/11507
摘要： Semiconductor devices and ferroelectric memory cells therefor are provided, where the cells include a ferroelectric capacitor with one or more corners, as well as a transistor. Conductive bitline structures are located near the corners of ferroelectric cell capacitors to facilitate increased memory cell density and/or to increase capacitor area within a given cell area. Methods are disclosed for fabricating semiconductor devices with ferroelectric memory cells, wherein bitline structures are located near one or more corners of the ferroelectric cell capacitors.
摘要翻译：提供了半导体器件和铁电存储器单元，其中单元包括具有一个或多个拐角的铁电电容器以及晶体管。导电位线结构位于铁电单元电容器的拐角附近，以便增加存储单元密度和/或增加给定单元区域内的电容器面积。公开了用于制造具有铁电存储器单元的半导体器件的方法，其中位线结构位于铁电电容器的一个或多个拐角附近。

33. 发明申请

US20050012126A1 Hydrogen barrier for protecting ferroelectric capacitors in a semiconductor device and methods for fabricating the same 有权
标题翻译：用于保护半导体器件中的铁电电容器的氢屏障及其制造方法
公开(公告)号：US20050012126A1
公开(公告)日：2005-01-20
申请号：US10620516
申请日：2003-07-16
申请人： K. Udayakumar , Martin Albrecht , Theodore Moise , Scott Summerfelt , Sanjeev Aggarwal , Jeff Large
发明人： K. Udayakumar , Martin Albrecht , Theodore Moise , Scott Summerfelt , Sanjeev Aggarwal , Jeff Large
IPC分类号： H01L21/02 , H01L23/00 , H01L29/06 , H01L21/00 , H01L31/0328 , H01L31/0336 , H01L31/072
CPC分类号： H01L28/57 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and fabrication methods are presented, in which a hydrogen barrier is provided above a ferroelectric capacitor to prevent degradation of the ferroelectric material during back-end manufacturing processes employing hydrogen. The hydrogen barrier comprises silicon rich silicon oxide or amorphous silicon, which can be used in combination with an aluminum oxide layer to inhibit diffusion of process-related hydrogen into the ferroelectric capacitor layer.
摘要翻译：提出了半导体器件和制造方法，其中在铁电电容器上方设置氢气阻挡层，以防止在使用氢的后端制造工艺期间铁电材料的劣化。氢势垒包括富硅氧化物或非晶硅，其可以与氧化铝层组合使用以抑制工艺相关氢扩散到铁电电容器层中。

34. 发明授权

US06734477B2 Fabricating an embedded ferroelectric memory cell 失效
标题翻译：制造嵌入式铁电存储单元
公开(公告)号：US06734477B2
公开(公告)日：2004-05-11
申请号：US09925214
申请日：2001-08-08
申请人： Ted Moise , Scott Summerfelt , Eden Zielinski , Scott Johnson
发明人： Ted Moise , Scott Summerfelt , Eden Zielinski , Scott Johnson
IPC分类号： H01L21824
CPC分类号： H01L27/11502 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L27/11507 , H01L28/55 , H01L28/57 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuit structures comprising an embedded ferroelectric memory cell and methods of forming the same are described. These structures include a transistor level, a ferroelectric device level, a first metal level, an inter-level dielectric level and a second metal level. In a first embodiment, the ferroelectric device level is disposed over an isolation layer of the transistor level and an isolation layer of the ferroelectric level has one or more vias that are laterally sized larger than corresponding contact vias extending through the transistor isolation layer and aligned therewith. In a second embodiment, the first metal level and the ferroelectric device level are integrated into the same level. In a third embodiment, the ferroelectric device level is disposed over the first metal level. In a fourth embodiment, the ferroelectric device level is disposed over the inter-level dielectric level that, in turn, is disposed over the first metal level. In a fifth embodiment, the ferroelectric device level is disposed over the transistor isolation layer and the ferroelectric isolation layer has one or more vias extending through the ferroelectric isolation layer and the transistor isolation layer. These embodiments implement different strategies for improving the yield and performance of embedded ferroelectric devices.
摘要翻译：描述了包括嵌入式铁电存储单元的集成电路结构及其形成方法。这些结构包括晶体管级，铁电器件级，第一金属级，级间介电级和第二金属级。在第一实施例中，铁电体器件级设置在晶体管级的隔离层上，并且铁电层的隔离层具有一个或多个通孔，其横向尺寸大于延伸穿过晶体管隔离层并与其对准的相应接触通孔。在第二实施例中，第一金属水平和铁电体装置水平集成在同一水平。在第三实施例中，铁电体器件级设置在第一金属层上。在第四实施例中，铁电体器件级设置在层间介电水平之上，层间电介质层又设置在第一金属层上。在第五实施例中，铁电体器件电平设置在晶体管隔离层上方，铁电隔离层具有延伸穿过铁电隔离层和晶体管隔离层的一个或多个通孔。这些实施例实现了用于提高嵌入式铁电体器件的产量和性能的不同策略。

35. 发明授权

US06692976B1 Post-etch cleaning treatment 有权
标题翻译：蚀刻后清洗处理
公开(公告)号：US06692976B1
公开(公告)日：2004-02-17
申请号：US09650224
申请日：2000-08-31
申请人： Laura Wills Mirkarimi , Stephen R. Gilbert , Guoqiang Xing , Scott Summerfelt , Tomoyuki Sakoda , Ted Moise
发明人： Laura Wills Mirkarimi , Stephen R. Gilbert , Guoqiang Xing , Scott Summerfelt , Tomoyuki Sakoda , Ted Moise
IPC分类号： H01L21306
CPC分类号： H01L28/55 , H01L21/02052 , H01L21/0206 , H01L21/31111 , H01L21/32134 , H01L28/75
摘要： The present disclosure relates to a post-etch cleaning treatment for a semiconductor device such as a FeRAM. The treatment comprises providing an etchant comprising both a fluorine compound and a chlorine compound, and applying the etchant to the semiconductor device in a wet cleaning process.
摘要翻译：本公开涉及用于诸如FeRAM的半导体器件的后蚀刻清洁处理。该处理包括提供包括氟化合物和氯化合物两者的蚀刻剂，以及在湿清洗工艺中将蚀刻剂施加到半导体器件。

36. 发明授权

US06184074B2 Method of fabrication a self-aligned polysilicon/diffusion barrier/oxygen stable sidewall bottom electrode structure for high-K DRAMS 有权
标题翻译：制造用于高K DRAMS的自对准多晶硅/扩散阻挡层/氧稳定侧壁底电极结构的方法
公开(公告)号：US06184074B2
公开(公告)日：2001-02-06
申请号：US09211663
申请日：1998-12-15
申请人： Darius Crenshaw , Scott Summerfelt
发明人： Darius Crenshaw , Scott Summerfelt
IPC分类号： H01L218234
CPC分类号： H01L28/75 , H01L21/28568 , H01L27/10814 , H01L27/10852 , H01L28/40 , H01L28/60
摘要： The capacitor (12) comprises a HDC dielectric (40) and upper (44) and lower (32-36) electrodes. The lower electrode comprises a polysilicon base (32), a diffusion barrier (34) on the sidewalls of the polysilicon base (32) and an oxygen stable material (36) on the sidewalls adjacent the diffusion barrier (34) and separated from the polysilicon base (32) sidewalls by the diffusion barrier (34). The oxygen stable material (36) is formed on the sidewalls by a deposition and either etchback or CMP process rather than by a patterned etch. The HDC dielectric (40) is then formed adjacent the oxygen stable material (36).
摘要翻译：电容器（12）包括HDC电介质（40）和上电极（44）和下电极（32-36）。下电极包括多晶硅基底（32），在多晶硅基底（32）的侧壁上的扩散阻挡层（34）和邻近扩散阻挡层（34）的侧壁上的氧稳定材料（36）并与多晶硅基底（32）侧壁通过扩散阻挡层（34）。氧稳定材料（36）通过沉积和回蚀或CMP工艺而不是通过图案化蚀刻形成在侧壁上。然后，HDC电介质（40）邻近氧稳定材料（36）形成。

37. 发明授权

US6033919A Method of forming sidewall capacitance structure 失效
标题翻译：形成侧壁电容结构的方法
公开(公告)号：US6033919A
公开(公告)日：2000-03-07
申请号：US955761
申请日：1997-10-22
申请人： Bruce Gnade , Scott Summerfelt , Peter Kirlin
发明人： Bruce Gnade , Scott Summerfelt , Peter Kirlin
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/108 , H01G7/06
CPC分类号： H01L27/10852 , H01L28/40 , H01L28/55 , H01L28/65 , H01L28/82 , H01L28/90
摘要： A capacitive structure on an integrated circuit and a method of making the same are disclosed, which is particularly useful in random-access memory devices. Generally, the method of the present invention comprises the steps of forming a substantially vertical temporary support 54 (preferably by forming a cylindrical aperture in an insulating layer) on a semiconductor substrate 10 and forming a substantially vertical dielectric film 32 (preferably a high dielectric constant perovskite-phase dielectric film, and more preferably barium strontium titanate) on temporary support 54. The method further comprises depositing a first conductive (e.g. platinum) electrode 60 on substantially vertical dielectric film 32, and subsequently replacing temporary support 54 with a second conductive (e.g. platinum) electrode 64, such that a thin film capacitor 44 which is substantially vertical with respect to substrate 10 is formed. The entire capacitor is essentially self-aligned, such that some embodiments require only one lithography step to complete the capacitor. Also, an advantage of this method is that a high temperature, high oxygen activity dielectric deposition may be completed prior to formation of either electrode, thus greatly simplifying both electrode structure and processing.
摘要翻译：公开了集成电路中的电容结构及其制造方法，其在随机存取存储器件中特别有用。通常，本发明的方法包括以下步骤：在半导体衬底10上形成基本上垂直的临时支撑件54（优选通过在绝缘层中形成圆柱形孔），并形成基本垂直的电介质膜32（优选高介电常数钙钛矿相电介质膜，更优选钛酸钡钡）。该方法还包括在基本上垂直的介电膜32上沉积第一导电（例如铂）电极60，随后用第二导电（例如铂）电极64，使得形成相对于衬底10基本垂直的薄膜电容器44。整个电容器基本上是自对准的，使得一些实施例仅需要一个光刻步骤来完成电容器。此外，该方法的优点是可以在形成任一电极之前完成高温，高氧活性的电介质沉积，从而极大地简化电极结构和加工。

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