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31. 发明申请

US20100308877A1 POWER-ON RESET CIRCUIT 有权
标题翻译：上电复位电路
公开(公告)号：US20100308877A1
公开(公告)日：2010-12-09
申请号：US12794227
申请日：2010-06-04
申请人： Yu-Pin Chou , Hsien-Chun Chang , Wen-Che Wu
发明人： Yu-Pin Chou , Hsien-Chun Chang , Wen-Che Wu
IPC分类号： H03L7/00
CPC分类号： H03K17/20
摘要： A power-on reset circuit includes a clamping signal generator and a determining device. The clamping signal generator is adapted to receive a trigger signal, and generates a clamping signal with reference to the trigger signal. The clamping signal generator includes an output unit for generating the clamping signal according to a feedback signal, and a feedback unit for generating the feedback signal according to first and second intermediate signals. The first intermediate signal is generated with reference to the clamping signal. The second intermediate signal is generated according to the trigger signal. The determining device is adapted to receive the trigger signal, is coupled to the clamping signal generator for receiving the clamping signal therefrom, and is operable to generate a reset signal according to the trigger signal and the clamping signal.
摘要翻译：上电复位电路包括钳位信号发生器和确定装置。钳位信号发生器适于接收触发信号，并且参考触发信号产生钳位信号。钳位信号发生器包括用于根据反馈信号产生钳位信号的输出单元和用于根据第一和第二中间信号产生反馈信号的反馈单元。参考钳位信号产生第一中间信号。根据触发信号产生第二中间信号。确定装置适于接收触发信号，耦合到钳位信号发生器用于从其接收钳位信号，并且可操作以根据触发信号和钳位信号产生复位信号。

32. 发明申请

US20080048740A1 METHOD AND APPARATUS FOR GENERATING CLOCK SIGNAL 审中-公开
标题翻译：用于产生时钟信号的方法和装置
公开(公告)号：US20080048740A1
公开(公告)日：2008-02-28
申请号：US11773940
申请日：2007-07-05
申请人： Yu-Pin Chou
发明人： Yu-Pin Chou
IPC分类号： H03L7/06
CPC分类号： H03L7/081
摘要： The present invention relates to an apparatus and a method thereof for generating a clock signal. The apparatus includes a clock generating module and at least one delay stage. The clock generating module receives a reference signal through a first signal path, receives a feedback signal through a second signal path, and provides a clock signal to a third signal path according to the reference signal, wherein the feedback signal corresponds to the clock signal. The at least one delay stage is located on at least one of the first, second, and third signal paths for providing a corresponding delay on the signal path at which the at least one delay stage is positioned.
摘要翻译：本发明涉及一种用于产生时钟信号的装置及其方法。该装置包括时钟产生模块和至少一个延迟级。时钟产生模块通过第一信号路径接收参考信号，通过第二信号路径接收反馈信号，并根据参考信号向第三信号路径提供时钟信号，其中反馈信号对应于时钟信号。所述至少一个延迟级位于所述第一，第二和第三信号路径中的至少一个上，用于在所述至少一个延迟级所位于的信号路径上提供对应的延迟。

33. 发明申请

US20070159263A1 PHASE LOCK LOOP FOR RAPID LOCK-IN AND METHOD THEREFOR 有权
标题翻译：相位锁定用于快速锁定及其方法
公开(公告)号：US20070159263A1
公开(公告)日：2007-07-12
申请号：US11620053
申请日：2007-01-05
申请人： Yu-Pin Chou , Chi-Kung Kuan
发明人： Yu-Pin Chou , Chi-Kung Kuan
IPC分类号： H03L7/00
CPC分类号： H03L7/10 , H03L7/0814 , H03L7/0891 , H03L7/0991 , H03L7/0996 , H03L2207/06 , Y10S331/02
摘要： A phase-locked loop (PLL) for rapid lock-in applicable to digital, analog, or hybrid digital-analog PLL circuits is provided. Besides the units for basic operation, including a phase-frequency detector (PFD), a charge pump, a loop filter, and/or a voltage/current/digital-controlled oscillator (VCO/ICO/DCO), an additional lock-in actuator circuit is provided for providing lock-in signals, achieving the purpose of rapid lock-in through operational processes.
摘要翻译：提供了适用于数字，模拟或混合数字 - 模拟PLL电路的快速锁定锁相环（PLL）。除了用于基本操作的单元，包括相位频率检测器（PFD），电荷泵，环路滤波器和/或电压/电流/数字控制振荡器（VCO / ICO / DCO），附加锁定致动器电路被提供用于提供锁定信号，实现通过操作过程快速锁定的目的。

34. 发明申请

US20060220687A1 CHIP WITH ADJUSTABLE PINOUT FUNCTION AND METHOD THEREOF 有权
标题翻译：具有可调节引脚功能的芯片及其方法
公开(公告)号：US20060220687A1
公开(公告)日：2006-10-05
申请号：US11277361
申请日：2006-03-24
申请人： Hung-Jen Chu , Chao-Hsin Lu , Shiu-Rong Tong , Yu-Pin Chou
发明人： Hung-Jen Chu , Chao-Hsin Lu , Shiu-Rong Tong , Yu-Pin Chou
IPC分类号： H03K19/00
CPC分类号： G06F1/22 , H03K19/1732
摘要： A chip with an adjustable pinout function is disclosed. The chip includes a first pinout, a second pinout, a logic circuit, and a selecting circuit. The logic circuit includes a first port and a second port. The selecting circuit, which is coupled to the logic circuit, the first pinout, and the second pinout, controls the first pinout to be coupled to the first port or the second port, and controls the second pinout to be coupled to the first port or the second port.
摘要翻译：公开了一种具有可调节引脚排列功能的芯片。芯片包括第一引脚，第二引脚，逻辑电路和选择电路。逻辑电路包括第一端口和第二端口。耦合到逻辑电路，第一引脚排列和第二引脚分布的选择电路控制第一引脚被耦合到第一端口或第二端口，并且控制第二引脚分布以耦合到第一端口或第二个港口。

35. 发明申请

US20060136620A1 DATA TRANSFER INTERFACE APPARATUS AND METHOD THEREOF 审中-公开
标题翻译：数据传输接口装置及其方法
公开(公告)号：US20060136620A1
公开(公告)日：2006-06-22
申请号：US10905109
申请日：2004-12-16
申请人： Yu-Pin Chou
发明人： Yu-Pin Chou
IPC分类号： G06F3/06
CPC分类号： G06F5/06
摘要： A data transfer interface apparatus and method for controlling data transfer. The data transfer interface apparatus includes a first storage unit for storing an input data according to a first clock and for outputting a first output data according to a second clock, a single-port memory coupled to the first storage unit for storing the first output data according to the second clock and for outputting a second output data according to the second clock, and a second storage unit coupled to the single-port memory for storing the second output data according to the second clock and for outputting a third output data according to a third clock.
摘要翻译：一种用于控制数据传送的数据传输接口装置和方法。数据传输接口装置包括：第一存储单元，用于根据第一时钟存储输入数据，并用于根据第二时钟输出第一输出数据;耦合到第一存储单元的单端口存储器，用于存储第一输出数据并且根据第二时钟输出第二输出数据，以及第二存储单元，其耦合到单端口存储器，用于根据第二时钟存储第二输出数据，并根据第二时钟输出第三输出数据第三个时钟。

36. 发明申请

US20060071922A1 Device and method for up/down converting data output 审中-公开
标题翻译：用于上/下转换数据输出的设备和方法
公开(公告)号：US20060071922A1
公开(公告)日：2006-04-06
申请号：US11242008
申请日：2005-10-04
申请人： Yu-Pin Chou
发明人： Yu-Pin Chou
IPC分类号： G09G5/00
CPC分类号： G09G5/005 , G09G5/008
摘要： A method for up/down converting display data employs steps of generating a first clock signal, generating display data, writing the display data into a buffer using the first clock signal, generating a second clock signal, reading out the display data written into the buffer using the second signal, and transmitting the read-out display data to a display module.
摘要翻译：用于上/下转换显示数据的方法采用产生第一时钟信号，产生显示数据，使用第一时钟信号将显示数据写入缓冲器的步骤，产生第二时钟信号，读出写入缓冲器的显示数据使用第二信号，并将读出的显示数据发送到显示模块。

37. 发明申请

US20060012438A1 PHASE LOCKED LOOP WITH NONLINEAR PHASE-ERROR RESPONSE CHARACTERISTIC 有权
标题翻译：具有非线性相位误差响应特性的相位锁定环
公开(公告)号：US20060012438A1
公开(公告)日：2006-01-19
申请号：US11160767
申请日：2005-07-07
申请人： Yu-Pin Chou , Chia-Liang Chiang
发明人： Yu-Pin Chou , Chia-Liang Chiang
IPC分类号： H03L7/00
CPC分类号： H03L7/0891 , H03L7/093
摘要： A phase-locked loop includes a phase/frequency detector for generating phase error signal according to a reference signal and an input signal, a charge pump for outputting a voltage signal according to the phase error signal, a voltage-controlled oscillator for outputting an output signal corresponding to the phase error signal according to the voltage signal, an adaptive adjusting unit for outputting a control signal according to the phase error signal, so as to form a nonlinear between the output signal and the phase error signal.
摘要翻译：锁相环包括用于根据参考信号和输入信号产生相位误差信号的相位/频率检测器，用于根据相位误差信号输出电压信号的电荷泵，用于输出输出的电压控制振荡器根据电压信号对应于相位误差信号的信号，自适应调整单元，用于根据相位误差信号输出控制信号，以便在输出信号和相位误差信号之间形成非线性。

38. 发明申请

US20050001656A1 DIGITAL FRACTIONAL PHASE DETECTOR 有权
标题翻译：数字相位检测器
公开(公告)号：US20050001656A1
公开(公告)日：2005-01-06
申请号：US10609535
申请日：2003-07-01
申请人： Yu-Pin Chou
发明人： Yu-Pin Chou
IPC分类号： H03D13/00
CPC分类号： H03D13/003
摘要： A digital fractional phase detector is shown that uses a phase error detector for generating a phase error signal based on the phase difference between a reference clock signal and a feedback clock signal. A quantizer directly measures the pulse width of a phase error signal and outputs the value in a digital form. By directly measuring the phase error signal, quantization accuracy is increased. In order to calibrate the digital fractional phase detector, a calibration pulse generator generates a calibration pulse of a known duration and passes it to the quantizer.
摘要翻译：示出了一种数字分数相位检测器，其使用相位误差检测器基于参考时钟信号和反馈时钟信号之间的相位差产生相位误差信号。量化器直接测量相位误差信号的脉冲宽度，并以数字形式输出该值。通过直接测量相位误差信号，量化精度提高。为了校准数字分数相位检测器，校准脉冲发生器产生已知持续时间的校准脉冲并将其传递给量化器。

39. 发明授权

US08471859B2 Device and method for controlling frame input and output 有权
标题翻译：用于控制帧输入和输出的装置和方法
公开(公告)号：US08471859B2
公开(公告)日：2013-06-25
申请号：US12692389
申请日：2010-01-22
申请人： Chia-Lung Hung , Tzuo-Bo Lin , Hsien-Chun Chang , Yu-Pin Chou
发明人： Chia-Lung Hung , Tzuo-Bo Lin , Hsien-Chun Chang , Yu-Pin Chou
IPC分类号： G09G5/39 , G09G5/36 , G06F12/02 , H04N7/01
CPC分类号： H04N7/0105 , H04N7/0132
摘要： A device and method for controlling frame input and output are applied to the reception of image data from a source device and output of the image data to a destination device, the device includes a buffer, a buffer control circuit, and a frame write controller. The input pixel clock is not equal to the output pixel clock. The frame write controller generates a write permission signal according to the Input DE and the Output DE. The buffer control circuit generates a write control signal according to the Input DE and the write permission signal, and generates a read control signal according to the Output DE. The buffer receives the image data from the source device according to the write control signal and the input pixel clock, and outputs the image data to the destination device according to the read control signal and the output pixel clock.
摘要翻译：用于控制帧输入和输出的装置和方法被应用于从源设备接收图像数据并将图像数据输出到目的地设备，该设备包括缓冲器，缓冲器控制电路和帧写入控制器。输入像素时钟不等于输出像素时钟。帧写入控制器根据输入DE和输出DE生成写许可信号。缓冲器控制电路根据输入DE和写允许信号产生写控制信号，并根据输出DE生成读控制信号。缓冲器根据写控制信号和输入像素时钟从源装置接收图像数据，并根据读控制信号和输出像素时钟将图像数据输出到目的地装置。

40. 发明授权

US08284871B2 Synchronization determining circuit, receiver including the synchronization determining circuit, and method of the receiver 有权
标题翻译：同步确定电路，包括同步确定电路的接收机和接收机的方法
公开(公告)号：US08284871B2
公开(公告)日：2012-10-09
申请号：US12501959
申请日：2009-07-13
申请人： Tzuo-Bo Lin , Bing-Juo Chuang , Yu-Pin Chou
发明人： Tzuo-Bo Lin , Bing-Juo Chuang , Yu-Pin Chou
IPC分类号： H04L27/22
CPC分类号： H04L7/10 , G09G5/006 , G09G5/008 , G09G2370/12 , H04L7/046 , H04L25/4908
摘要： A receiver includes; a recovery circuit for receiving an input signal, and generating a data signal and a recovery clock; a processing circuit for processing the data signal to generate a processed signal; and a synchronization determining circuit for determining a synchronization state of the recovery clock according to the processed signal and a first reference value. The data signal includes a synchronous pattern, and the first reference value corresponds to at least a portion of a value in the synchronous pattern processed by the processing circuit. A method of the receiver is also disclosed.
摘要翻译：接收机包括恢复电路，用于接收输入信号，并产生数据信号和恢复时钟; 处理电路，用于处理数据信号以产生处理的信号; 以及同步确定电路，用于根据处理的信号和第一参考值确定恢复时钟的同步状态。数据信号包括同步模式，第一参考值对应于由处理电路处理的同步模式中的值的至少一部分。还公开了接收机的方法。

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