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    • 31. 发明申请
    • Signature circuit, semiconductor device having the same and method of reading signature information
    • 签名电路,具有相同的半导体器件和读取签名信息的方法
    • US20070030051A1
    • 2007-02-08
    • US11472850
    • 2006-06-22
    • Yu-Lim LeeSung-Hoon Kim
    • Yu-Lim LeeSung-Hoon Kim
    • H01H37/76
    • H01L23/585G11C29/028G11C29/50008G11C2029/4402H01L23/544H01L2223/5444H01L2924/0002H01L2924/3011H01L2924/00
    • A signature circuit in a semiconductor chip includes a signature program circuit configured to be programmed with signature information and to output a signature signal in response to the signature information; a signature output circuit configured to block the signature signal output by the signature program circuit during operation in a normal mode, and configured to pass the signature signal during operation in a test mode; and a pad-driving transistor directly coupled to the pad, configured to drive the pad during operation in the normal mode in response to an operation command, and configured to drive the pad during operation in the test mode in response to the signature signal output by the signature output circuit. The signature circuit outputs the signature information through a transistor for adjusting impedance to reduce a chip size by omitting an additional logic circuit for the signature circuit.
    • 半导体芯片中的签名电路包括签名程序电路,其被配置为对签名信息进行编程,并响应于签名信息输出签名信号; 签名输出电路,被配置为在正常模式下操作期间阻止由所述签名程序电路输出的签名信号,并且被配置为在测试模式下操作期间传递所述签名信号; 以及焊盘驱动晶体管,其直接耦合到所述焊盘,被配置为响应于操作命令在正常模式下操作期间驱动焊盘,并且被配置为响应于在测试模式中的操作期间响应于由 签名输出电路。 签名电路通过用于调整阻抗的晶体管输出签名信息,以通过省略签名电路的附加逻辑电路来减小芯片尺寸。
    • 34. 发明授权
    • Column redundancy circuit for a memory device
    • 用于存储器件的列冗余电路
    • US5953270A
    • 1999-09-14
    • US153343
    • 1998-09-15
    • Sung-Hoon Kim
    • Sung-Hoon Kim
    • G11C29/00G11C7/00
    • G11C29/806
    • The present invention relates to a column redundancy circuit in semiconductor memories which improves yields by means of substituting defective cells with redundant memory cells provided that defective memory cells are detected. The present invention of a redundancy circuit in semiconductor memories having a first memory cell array and a second memory cell arrays with an Y-decoder includes a first row redundancy circuit receiving a row address signal wherein the first row redundancy circuit outputs a first MAT selection signal for repairing a word line in the first memory cell array, a second row redundancy circuit receiving the row address signal wherein the second row to redundancy circuit outputs a second MAT selection signal for repairing a word line in the second memory cell array, a redundancy circuit controller generating a first MAT selection enable signal and a second MAT selection enable signal wherein the first MAT selection enable signal and the second MAT selection enable signal are complementary each other, a MAT selection signal controller receiving the first MAT selection signal and the second MAT selection signal wherein the MAT selection signal controller outputs one of the first MAT selection signal and the second MAT selection signal in accordance with the first MAT selection enable signal and the second MAT selection enable signal, respectively, a column redundancy circuit receiving a column address signal and the MAT selection signal which is outputted from the MAT selection signal controller wherein the column redundancy circuit outputs a repairing decision signal, a first MAT redundant signal and a second MAT redundant signal, and an Y-decoder receiving the first MAT redundant signal and the second MAT redundant signal wherein the Y-decoder outputs a normal column selection signal or a redundant column selection signal under a condition of the repairing decision signal.
    • 半导体存储器中的列冗余电路技术领域本发明涉及半导体存储器中的列冗余电路,其通过用冗余存储器单元替换有缺陷的单元来提高产量,只要检测到有缺陷的存储单元即可。 具有第一存储单元阵列的半导体存储器中的冗余电路的本发明和具有Y解码器的第二存储单元阵列的本发明包括:第一行冗余电路,其接收行地址信号,其中第一行冗余电路输出第一MAT选择信号 用于修复第一存储单元阵列中的字线,接收行地址信号的第二行冗余电路,其中第二行至冗余电路输出用于修复第二存储单元阵列中的字线的第二MAT选择信号,冗余电路 控制器生成第一MAT选择使能信号和第二MAT选择使能信号,其中第一MAT选择使能信号和第二MAT选择使能信号彼此互补; MAT选择信号控制器,接收第一MAT选择信号和第二MAT选择 信号,其中所述MAT选择信号控制器输出所述第一MAT选择中的一个 n信号和第二MAT选择信号,分别根据第一MAT选择使能信号和第二MAT选择使能信号,接收列地址信号的列冗余电路和从MAT选择信号控制器输出的MAT选择信号 其中所述列冗余电路输出修复决定信号,第一MAT冗余信号和第二MAT冗余信号,以及接收所述第一MAT冗余信号和所述第二MAT冗余信号的Y解码器,其中所述Y解码器输出正常列选择 信号或冗余列选择信号。
    • 36. 发明授权
    • Polarizing panel and display device having the same
    • 偏光面板和具有相同的显示装置
    • US09013645B2
    • 2015-04-21
    • US13210215
    • 2011-08-15
    • Dong-Yoon LeeSung-Hoon Kim
    • Dong-Yoon LeeSung-Hoon Kim
    • G02F1/1335G02F1/1333G02F1/01G02B27/26H04N13/04
    • G02F1/0136G02B27/26H04N13/337
    • A polarizing panel includes a first substrate, a second substrate and an interposed first liquid crystal layer. The first substrate includes a plurality of spaced apart and segment electrodes and segments of a first light-blocking member disposed within interval areas between the segment electrodes. The second substrate faces the first substrate to include a common electrode facing the segment electrodes. The first liquid crystal layer is able to selectively apply a first polarizing effect to light rays passing therethrough when in a corresponding first state and to apply a different second polarizing effect to passing through light rays when in a corresponding second state, where the first and second states can be selectively chosen by voltages applied to the segment electrodes. The light-blocking member can reduce image crosstalk lights from being emitted from the interval areas between the segment electrodes, so that a crosstalk component of a formed 3D image may be prevented or reduced due to light-blocking effects.
    • 偏光板包括第一基板,第二基板和插入的第一液晶层。 第一基板包括多个间隔开的分段电极和设置在分段电极之间的间隔区域内的第一遮光部件的部分。 第二基板面向第一基板以包括面向分段电极的公共电极。 当处于相应的第一状态时,第一液晶层能够选择性地对通过其的光线施加第一偏振效果,并且当处于相应的第二状态时,第一液晶层可以施加不同的第二偏振效果以通过光线,其中第一和第二 可以通过施加到段电极的电压来选择性地选择状态。 遮光构件可以减少从段电极之间的间隔区域发射的图像串扰光,从而可以防止或减少由于遮光效应而形成的3D图像的串扰分量。