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31. 发明授权

US06335254B1 Methods of forming transistors 失效
标题翻译：形成晶体管的方法
公开(公告)号：US06335254B1
公开(公告)日：2002-01-01
申请号：US09635279
申请日：2000-08-09
申请人： Jigish D. Trivedi
发明人： Jigish D. Trivedi
IPC分类号： H01L21336
CPC分类号： H01L29/66545 , H01L21/28247 , H01L29/4941
摘要： In accordance with an aspect of the invention, a transistor is formed having a transistor gate, a gate dielectric layer and source/drain regions. The transistor gate includes at least two conductive layers of different conductive materials. One of the two conductive layers is more proximate the gate dielectric layer than the other of the two conductive layers. A source/drain reoxidation is conducted prior to forming the other conductive layer. In another aspect of the invention, a transistor has a transistor gate, a gate dielectric layer and source/drain regions. The transistor gate includes a tungsten layer. A source/drain reoxidation is conducted prior to forming the tungsten layer of the gate. In yet another aspect of the invention, a semiconductor processing method forms a transistor gate having insulative sidewall spacers thereover. After forming the insulative sidewall spacers, an outer conductive tungsten layer of the transistor gate is formed.
摘要翻译：根据本发明的一个方面，形成具有晶体管栅极，栅极电介质层和源极/漏极区域的晶体管。晶体管栅极包括至少两个不同导电材料的导电层。两个导电层之一比栅电介质层更靠近两个导电层中的另一个。源/漏再氧化在形成另一导电层之前进行。在本发明的另一方面，晶体管具有晶体管栅极，栅极电介质层和源极/漏极区域。晶体管栅极包括钨层。在形成栅极的钨层之前进行源极/漏极再氧化。在本发明的另一方面，半导体处理方法形成了具有绝缘侧壁间隔物的晶体管栅极。在形成绝缘侧壁间隔物之后，形成晶体管栅极的外部导电钨层。

32. 发明授权

US08319280B2 Recessed access device for a memory 有权
标题翻译：嵌入式存储设备
公开(公告)号：US08319280B2
公开(公告)日：2012-11-27
申请号：US13231554
申请日：2011-09-13
申请人： Kurt D. Beigel , Jigish D. Trivedi , Kevin G. Duesman
发明人： Kurt D. Beigel , Jigish D. Trivedi , Kevin G. Duesman
IPC分类号： H01L29/66
CPC分类号： H01L29/66621 , H01L27/10876
摘要： Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.
摘要翻译：公开了具有凹陷接入装置的半导体存储器件。在一些实施例中，形成凹陷进入装置的方法包括在衬底材料中形成器件凹部，该衬底材料延伸到衬底中的第一深度，该第一深度包括凹陷中的栅极氧化物层。装置凹部可以延伸到大于第一深度的第二深度，以形成装置凹部的延伸部分。场氧化物层可以设置在器件凹部的内部，其内部延伸到器件凹部的内部并进入衬底。活性区域可以形成在衬底中，其邻接场氧化物层，并且栅极材料可以沉积到器件凹部中。

33. 发明申请

US20120199908A1 CAPACITORLESS DRAM ON BULK SILICON 失效
标题翻译：大容量无机硅电容器
公开(公告)号：US20120199908A1
公开(公告)日：2012-08-09
申请号：US13445711
申请日：2012-04-12
申请人： Suraj Mathew , Jigish D. Trivedi
发明人： Suraj Mathew , Jigish D. Trivedi
IPC分类号： H01L27/12
CPC分类号： G11C7/00 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10882 , H01L27/1203 , H01L29/7841
摘要： A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.
摘要翻译：在局部绝缘体上形成无电容器DRAM的方法包括以下步骤：提供硅衬底，并且硅衬底阵列限定在硅衬底内。绝缘体层限定在硅衬底的至少一部分之上，并且在硅柱之间。围绕绝缘体层上方的硅柱的绝缘体层被限定，并且在绝缘体上硅层内部和上方形成无电容的DRAM。

34. 发明申请

US20110117725A1 Methods of Forming Recessed Access Devices Associated with Semiconductor Constructions 有权
标题翻译：形成与半导体结构相关的嵌入式接入设备的方法
公开(公告)号：US20110117725A1
公开(公告)日：2011-05-19
申请号：US13012675
申请日：2011-01-24
申请人： Kunal R. Parekh , Suraj Mathew , Jigish D. Trivedi , John K. Zahurak , Sanh D. Tang
发明人： Kunal R. Parekh , Suraj Mathew , Jigish D. Trivedi , John K. Zahurak , Sanh D. Tang
IPC分类号： H01L21/76
CPC分类号： H01L27/10876 , H01L27/10823
摘要： The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region.
摘要翻译：本发明包括形成凹入进入装置的方法。提供基板以在其中具有凹入的接入装置沟槽。一对凹进的接入设备沟槽彼此相邻。导电材料形成在凹进的存取装置沟槽内，源极/漏极区域靠近导电材料形成。导电材料和源极/漏极区域一起被并入一对相邻的凹进入器件中。在凹陷的访问设备沟槽形成在衬底内之后，在相邻的凹进的访问设备之间形成隔离区沟槽，并且填充有电绝缘材料以形成沟槽隔离区域。

35. 发明授权

US07919829B2 Liner for shallow trench isolation 有权
标题翻译：衬垫用于浅沟隔离
公开(公告)号：US07919829B2
公开(公告)日：2011-04-05
申请号：US11846427
申请日：2007-08-28
申请人： Jigish D. Trivedi , Robert D. Patraw , Kevin L. Beaman , John A. Smythe, III
发明人： Jigish D. Trivedi , Robert D. Patraw , Kevin L. Beaman , John A. Smythe, III
IPC分类号： H01L29/00
CPC分类号： H01L21/76224 , H01L21/76227
摘要： A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls to protect the walls. The silicon nitride layer further from the trench walls has a low nitrogen content and a high silicon content, to allow improved adhesion. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator. The resulting trench has a well-adhered insulator which helps the insulating properties of the trench.
摘要翻译：提供了将电介质材料沉积到亚微米空间和结构中的方法。在晶片的表面蚀刻沟槽之后，将氮化硅屏障沉积到沟槽中。氮化硅层在沟壁附近具有高氮含量以保护壁。进一步从沟槽壁的氮化硅层具有低的氮含量和高的硅含量，以提高粘附性。然后用旋涂前体填充沟槽。然后施加致密化或反应过程以将旋涂材料转化成绝缘体。所得的沟槽具有良好粘附的绝缘体，其有助于沟槽的绝缘性能。

36. 发明授权

US07897460B2 Methods of forming recessed access devices associated with semiconductor constructions 有权
公开(公告)号：US07897460B2
公开(公告)日：2011-03-01
申请号：US12051620
申请日：2008-03-19
申请人： Kunal R. Parekh , Suraj Mathew , Jigish D. Trivedi , John K. Zahurak , Sanh D. Tang
发明人： Kunal R. Parekh , Suraj Mathew , Jigish D. Trivedi , John K. Zahurak , Sanh D. Tang
IPC分类号： H01L21/336
CPC分类号： H01L27/10876 , H01L27/10823
摘要： The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region.

37. 发明申请

US20110020988A1 CAPACITORLESS DRAM ON BULK SILICON 有权
标题翻译：大容量无机硅电容器
公开(公告)号：US20110020988A1
公开(公告)日：2011-01-27
申请号：US12897999
申请日：2010-10-05
申请人： SURAJ MATHEW , Jigish D. Trivedi
发明人： SURAJ MATHEW , Jigish D. Trivedi
IPC分类号： H01L21/20 , G11C7/00
CPC分类号： G11C7/00 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10882 , H01L27/1203 , H01L29/7841
摘要： A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.
摘要翻译：在局部绝缘体上形成无电容器DRAM的方法包括以下步骤：提供硅衬底，并且硅衬底阵列限定在硅衬底内。绝缘体层限定在硅衬底的至少一部分之上，并且在硅柱之间。围绕绝缘体层上方的硅柱的绝缘体层被限定，并且在绝缘体上硅层内部和上方形成无电容的DRAM。

38. 发明授权

US07514366B2 Methods for forming shallow trench isolation 有权
标题翻译：形成浅沟槽隔离的方法
公开(公告)号：US07514366B2
公开(公告)日：2009-04-07
申请号：US11470150
申请日：2006-09-05
申请人： Jigish D. Trivedi , Robert D. Patraw , Kevin L. Beaman , John A. Smythe, III
发明人： Jigish D. Trivedi , Robert D. Patraw , Kevin L. Beaman , John A. Smythe, III
IPC分类号： H01L21/311
CPC分类号： H01L21/76224 , H01L21/76227
摘要： A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls to protect the walls. The silicon nitride layer further from the trench walls has a low nitrogen content and a high silicon content, to allow improved adhesion. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator. The resulting trench has a well-adhered insulator which helps the insulating properties of the trench.
摘要翻译：提供了将电介质材料沉积到亚微米空间和结构中的方法。在晶片的表面蚀刻沟槽之后，将氮化硅屏障沉积到沟槽中。氮化硅层在沟壁附近具有高氮含量以保护壁。进一步从沟槽壁的氮化硅层具有低的氮含量和高的硅含量，以提高粘附性。然后用旋涂前体填充沟槽。然后施加致密化或反应过程以将旋涂材料转化成绝缘体。所得的沟槽具有良好粘附的绝缘体，其有助于沟槽的绝缘性能。

39. 发明授权

US07005342B2 Method to fabricate surface p-channel CMOS 失效
公开(公告)号：US07005342B2
公开(公告)日：2006-02-28
申请号：US10929284
申请日：2004-08-30
申请人： Suraj J. Mathew , Jigish D. Trivedi
发明人： Suraj J. Mathew , Jigish D. Trivedi
IPC分类号： H01L21/66 , H01L21/425 , H01L21/8238
CPC分类号： H01L21/823842 , H01L27/10873
摘要： An improved method of making CMOS surface channel transistors using fewer masking steps. In-situ doped poly silicon deposition can be used to reduce problems with poly depletion effects in transistor gates. In addition, using this method, the number of layers in each gate dielectric, the dielectric type, and dielectric thickness between n-channel and p-channel devices can be separately controlled. This method also allows the use of a lithography mask normally used to fabricate buried channel devices for use in fabricating surface channel devices, thus saving the manufacture of an additional mask.

40. 发明授权

US06893957B2 Method of forming a dual damascene interconnect by selective metal deposition 失效
标题翻译：通过选择性金属沉积形成双镶嵌互连的方法
公开(公告)号：US06893957B2
公开(公告)日：2005-05-17
申请号：US10038305
申请日：2002-01-02
申请人： Jigish D. Trivedi , Mike P. Violette
发明人： Jigish D. Trivedi , Mike P. Violette
IPC分类号： H01L21/285 , H01L21/44 , H01L21/4763 , H01L21/768 , H01L23/48
CPC分类号： H01L21/76877 , H01L21/28562 , H01L21/76879
摘要： A dual damascene process is disclosed, in which a contact via and trench pattern is etched into insulating layer(s). The via is first partially filled by selective metal (e.g., tungsten) deposition, thereby forming a partial plug that raises the floor and reduces the effective aspect ratio of the trench and via structure. The remaining portion of the contact via is then filled with a more conductive material (e.g., aluminum). This deposition also at least partially fills the overlying trench to form metal runners. In the illustrated embodiment, hot aluminum deposition fills the portion of the contact via left unoccupied by the selective deposition and overfills into the trench. A further, cold aluminum deposition then follows, topping off the trench prior to planarization. The dual damascene structure thus exhibits a raised floor relative to conventional dual damascene metallization, while still retaining the conduction benefits of aluminum through a significant portion of the contact and the metal runner formed in the trench.
摘要翻译：公开了一种双镶嵌工艺，其中接触通孔和沟槽图案被蚀刻到绝缘层中。首先通过选择性金属（例如钨）沉积来部分地填充通孔，从而形成部分插头，其使地板上升并降低沟槽和通孔结构的有效纵横比。接触通孔的剩余部分然后用更导电的材料（例如铝）填充。该沉积还至少部分地填充上覆的沟槽以形成金属流道。在所示实施例中，热铝沉积通过左侧未被占用的选择性沉积填充接触部分，并且过度填充到沟槽中。然后再进行冷铝沉积，然后在平坦化之前将沟槽顶起来。因此，双镶嵌结构相对于传统的双镶嵌金属化显示出高的地板，同时仍然保持铝通过形成在沟槽中的大部分接触和金属流道的传导优点。

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