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31. 发明申请

US20060138480A1 A CMOS IMAGER WITH CU WIRING AND METHOD OF ELIMINATING HIGH REFLECTIVITY INTERFACES THEREFROM 有权
标题翻译：具有CU接线的CMOS成像器和消除其高反射性接口的方法
公开(公告)号：US20060138480A1
公开(公告)日：2006-06-29
申请号：US10905277
申请日：2004-12-23
申请人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Richard Rassel , Anthony Stamper
发明人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Richard Rassel , Anthony Stamper
IPC分类号： H01L31/113 , H01L31/0232 , H01L31/00
CPC分类号： H01L27/14636 , H01L21/76819 , H01L21/76834 , H01L27/14621 , H01L27/14625 , H01L27/14627 , H01L27/14629 , H01L27/14645 , H01L27/14683
摘要： An image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.
摘要翻译：一种图像传感器和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合较薄的层间电介质堆叠以产生呈现增加的光敏度的像素阵列。图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属的最小厚度的结构，或者具有从每个像素的光路中选择性地去除的阻挡层金属的部分，从而使反射率最小化。也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。在另一个实施例中，阻挡金属层可以通过自对准沉积形成在Cu金属化之上。

32. 发明申请

US20080054393A1 METHODS OF FABRICATING PASSIVE ELEMENT WITHOUT PLANARIZING AND RELATED SEMICONDUCTOR DEVICE 有权
标题翻译：无平面化和相关半导体器件制造被动元件的方法
公开(公告)号：US20080054393A1
公开(公告)日：2008-03-06
申请号：US11928798
申请日：2007-10-30
申请人： Anil Chinthakindi , Timothy Dalton , Ebenezer Eshun , Jeffrey Gambino , Anthony Stamper , Kunal Vaed
发明人： Anil Chinthakindi , Timothy Dalton , Ebenezer Eshun , Jeffrey Gambino , Anthony Stamper , Kunal Vaed
IPC分类号： H01L29/00 , H01L21/02
CPC分类号： H01L21/76819 , H01L23/522 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.
摘要翻译：公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在所述电介质层中形成通过所述介电层与所述无源元件的互连以及与所述虚拟无源元件的至少一部分重叠的虚拟互连部分。该方法消除了平面化的需要。

33. 发明申请

US20080036092A1 SACRIFICIAL INORGANIC POLYMER INTERMETAL DIELECTRIC DAMASCENE WIRE AND VIA LINER 有权
标题翻译：无机无机聚合物电介质电绝缘线和通过线
公开(公告)号：US20080036092A1
公开(公告)日：2008-02-14
申请号：US11873300
申请日：2007-10-16
申请人： Jeffrey Gambino , Anthony Stamper
发明人： Jeffrey Gambino , Anthony Stamper
IPC分类号： H01L23/48
CPC分类号： H01L21/02167 , H01L21/02118 , H01L21/02126 , H01L21/02164 , H01L21/0217 , H01L21/02266 , H01L21/02271 , H01L21/02274 , H01L21/312 , H01L21/3121 , H01L21/3122 , H01L21/3148 , H01L21/31612 , H01L21/76807 , H01L21/76811 , H01L21/76813 , H01L21/76831 , H01L21/76835 , H01L23/5226 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2221/1063 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric; depositing an upper low-k dielectric atop the lower metal wiring layer; etching at least one portion of the upper low-k dielectric to provide at least one via to the first metal lines; forming rigid dielectric sidewall spacers in at least one via of the upper low-k dielectric; and forming second metal lines in at least one portion of the upper low-k dielectric. The rigid dielectric sidewall spacers may comprise of SiCH, SiC, SiNH, SiN, or SiO2. Alternatively, the via region of the interconnect structure may be strengthened with a mechanically rigid dielectric comprising SiO2, SiCOH, or doped silicate glass.
摘要翻译：本发明提供一种形成刚性互连结构及其装置的方法，包括以下步骤：提供具有位于下部低k电介质内的第一金属线的下金属布线层; 在下部金属布线层的顶部沉积上部低k电介质; 蚀刻上部低k电介质的至少一部分以向第一金属线提供至少一个通孔; 在所述上部低k电介质的至少一个通路中形成刚性电介质侧壁间隔物; 以及在所述上部低k电介质的至少一部分中形成第二金属线。刚性电介质侧壁间隔物可以包括SiCH，SiC，SiNH，SiN或SiO 2。或者，可以用包含SiO 2，SiCOH或掺杂硅酸盐玻璃的机械刚性电介质来加强互连结构的通孔区域。

34. 发明申请

US20070252282A1 AIR-GAP INSULATED INTERCONNECTIONS 有权
标题翻译：空气隙绝缘互连
公开(公告)号：US20070252282A1
公开(公告)日：2007-11-01
申请号：US11772899
申请日：2007-07-03
申请人： Brent Anderson , Andres Bryant , Jeffrey Gambino , Anthony Stamper
发明人： Brent Anderson , Andres Bryant , Jeffrey Gambino , Anthony Stamper
IPC分类号： H01L23/52
CPC分类号： H01L21/7682 , H01L21/76802 , H01L21/76807 , H01L21/76831 , H01L21/76835 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Air-gap insulated interconnection structures and methods of fabricating the structures, the methods including: forming a dielectric layer on a substrate; forming a capping layer on a top surface of the dielectric layer; forming a trench through the capping layer, the trench extending toward said substrate and into but not through, the dielectric layer; forming a sacrificial layer on opposing sidewalls of the trench; filling the trench with a electrical conductor; and removing a portion of the sacrificial layer from between the electrical conductor and the dielectric layer to form air-gaps.
摘要翻译：气隙绝缘互连结构及其制造方法，包括：在基板上形成电介质层; 在所述电介质层的顶表面上形成覆盖层; 通过所述覆盖层形成沟槽，所述沟槽朝向所述衬底延伸并且穿过所述电介质层; 在沟槽的相对侧壁上形成牺牲层; 用电导体填充沟槽; 以及从所述电导体和所述电介质层之间移除所述牺牲层的一部分以形成气隙。

35. 发明申请

US20070241424A1 VERTICAL PARALLEL PLATE CAPACITOR USING SPACER SHAPED ELECTRODES AND METHOD FOR FABRICATION THEREOF 有权
标题翻译：使用间隔型电极的垂直平行平板电容器及其制造方法
公开(公告)号：US20070241424A1
公开(公告)日：2007-10-18
申请号：US11279434
申请日：2006-04-12
申请人： Timothy Dalton , Jeffrey Gambino , Anthony Stamper
发明人： Timothy Dalton , Jeffrey Gambino , Anthony Stamper
IPC分类号： H01L29/00
CPC分类号： H01G4/33 , H01G4/236 , H01L28/91 , Y10T29/435
摘要： A capacitor structure uses an aperture located within a dielectric layer in turn located over a substrate. A pair of conductor interconnection layers embedded within the dielectric layer terminates at a pair of opposite sidewalks of the aperture. A pair of capacitor plates is located upon the pair of opposite sidewalks of the aperture and contacting the pair of conductor interconnection layers, but not filling the aperture. A capacitor dielectric layer is located interposed between the pair of capacitor plates and filling the aperture. The pair of capacitor plates may be formed using an anisotropic unmasked etch followed by a masked trim etch. Alternatively, the pair of capacitor plates may be formed using an unmasked anisotropic etch only, when the pair of opposite sidewalks of the aperture is vertical and separated by a second pair of opposite sidewalks that is outward sloped.
摘要翻译：电容器结构使用位于电介质层内的开口依次位于衬底上。嵌入电介质层内的一对导体互连层终止于孔的一对相对的人行道。一对电容器板位于孔的一对相对的人行道上，并接触一对导体互连层，但不填充孔。电容器介质层位于一对电容器板之间并填充孔。可以使用各向异性无掩模蚀刻，然后进行掩模修整蚀刻来形成该对电容器板。或者，一对电容器板可以仅使用未屏蔽的各向异性蚀刻形成，当孔的一对相对的人行道是垂直的并且被向外倾斜的第二对相对的人行道分隔开时。

36. 发明申请

US20070114622A1 DAMASCENE COPPER WIRING OPTICAL IMAGE SENSOR 有权
标题翻译： DAMASCENE铜接线光学图像传感器
公开(公告)号：US20070114622A1
公开(公告)日：2007-05-24
申请号：US11623977
申请日：2007-01-17
申请人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Anthony Stamper
发明人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Anthony Stamper
IPC分类号： H01L29/82
CPC分类号： H01L27/14685 , H01L21/76819 , H01L21/76834 , H01L21/76838 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/14687
摘要： A CMOS image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a inner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material. Prior to depositing the refill dielectric, a layer of either reflective or absorptive material is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode or by eliminating light reflections.
摘要翻译： CMOS图像传感器阵列和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合具有改进的厚度均匀性的内部层间电介质叠层，以产生呈现增加的光敏度的像素阵列。在传感器阵列中，每个Cu金属化层包括在每个阵列像素之间的位置处形成的Cu金属线结构，并且阻挡材料层形成在穿过像素光路的每个Cu金属线结构上。通过实现单掩模或自对准掩模方法，进行单次蚀刻以完全去除穿过光路的层间电介质层和阻挡层。然后将蚀刻的开口用电介质材料重新填充。在沉积再充填电介质之前，沿蚀刻开口的侧壁形成反射或吸收材料层，以通过将光反射到下面的光电二极管或通过消除光反射来提高像素的灵敏度。

37. 发明申请

US20080108170A1 CMOS IMAGER WITH CU WIRING AND METHOD OF ELIMINATING HIGH REFLECTIVITY INTERFACES THEREFROM 失效
标题翻译：具有CU布线的CMOS成像器和消除其高反射性接口的方法
公开(公告)号：US20080108170A1
公开(公告)日：2008-05-08
申请号：US11959841
申请日：2007-12-19
申请人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Richard Rassel , Anthony Stamper
发明人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Richard Rassel , Anthony Stamper
IPC分类号： H01L21/04
CPC分类号： H01L27/14636 , H01L21/76819 , H01L21/76834 , H01L27/14621 , H01L27/14625 , H01L27/14627 , H01L27/14629 , H01L27/14645 , H01L27/14683
摘要： A CMOS image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The CMOS image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.
摘要翻译： CMOS图像传感器和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合较薄的层间电介质堆叠以产生呈现增加的光灵敏度的像素阵列。 CMOS图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属的最小厚度的结构，或者具有从每个像素的光路中选择性地去除的阻挡层金属的部分，从而使反射率最小化的结构。也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。在另一个实施例中，阻挡金属层可以通过自对准沉积形成在Cu金属化之上。

38. 发明申请

US20070122957A1 LOW-COST FEOL FOR ULTRA-LOW POWER, NEAR SUB-VTH DEVICE STRUCTURES 有权
标题翻译：低功耗超低功耗，小型设备结构
公开(公告)号：US20070122957A1
公开(公告)日：2007-05-31
申请号：US11164651
申请日：2005-11-30
申请人： Brent Anderson , Andres Bryant , William Clark , Jeffrey Gambino , Shih-Fen Huang , Edward Nowak , Anthony Stamper
发明人： Brent Anderson , Andres Bryant , William Clark , Jeffrey Gambino , Shih-Fen Huang , Edward Nowak , Anthony Stamper
IPC分类号： H01L21/8234 , H01L29/76 , H01L21/336
CPC分类号： H01L21/823412 , H01L21/823418 , H01L29/6653 , H01L29/66545 , H01L29/78
摘要： In order to reduce power dissipation requirements, obtain full potential transistor performance and avoid power dissipation limitations on transistor performance in high density integrated circuits, transistors are operated in a sub-threshold (sub-Vth) or a near sub-Vth voltage regime (generally about 0.2 volts rather than a super-Vth regime of about 1.2 volts or higher) and optimized for such operation, particularly through simplification of the transistor structure, since intrinsic channel resistance is dominant in sub-Vth operating voltage regimes. Such simplifications include an underlap or recess of the source and drain regions from the gate which avoids overlap capacitance to partially recover loss of switching speed otherwise caused by low voltage operation, an ultra-thin gate structure having a thickness of 500 Å or less which also simplifies forming connections to the transistor and an avoidance of silicidation or alloy formation in the source, drain and/or gate of transistors.
摘要翻译：为了降低功耗要求，获得全电位晶体管性能并避免在高密度集成电路中对晶体管性能的功率限制，晶体管以子阈值（sub-V thth th）或接近次级V th电压方式（通常约为0.2伏，而不是大于1.2伏特或更高的超V 2），并且针对这种操作进行了优化，特别是通过简化的晶体管结构，因为固有沟道电阻在次级V 3工作电压方面是主要的。这种简化包括来自栅极的源极和漏极区域的欠叠或凹陷，其避免重叠电容以部分恢复由低电压操作引起的切换速度的损失，厚度为或等于或小于500埃的超薄栅极结构简化了与晶体管的形成连接，避免了晶体管的源极，漏极和/或栅极中的硅化或合金形成。

39. 发明申请

US20060292863A1 PREVENTING DAMAGE TO METAL USING CLUSTERED PROCESSING AND AT LEAST PARTIALLY SACRIFICIAL ENCAPSULATION 有权
标题翻译：使用集中处理和至少部分严格封装防止金属损坏
公开(公告)号：US20060292863A1
公开(公告)日：2006-12-28
申请号：US11160465
申请日：2005-06-24
申请人： Jeffrey Gambino , Anthony Stamper
发明人： Jeffrey Gambino , Anthony Stamper
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , H01L21/76831 , H01L21/76834 , H01L21/76843 , H01L21/76844 , H01L21/76849 , H01L21/76865
摘要： Methods are disclosed for metal encapsulation for preventing exposure of metal during semiconductor processing. In one embodiment, the method includes forming an opening in a structure exposing a metal surface in a bottom of the opening, where the opening forming step occurs in a tool including at least one clustered chamber. An at least partially sacrificial encapsulation layer is then formed on the exposed metal surface in the tool to prevent reaction of the exposed metal surface with the ambient. Exposure of the metal is thereby prevented.
摘要翻译：公开了用于在半导体加工期间防止金属暴露的金属封装的方法。在一个实施例中，该方法包括在露出开口底部的金属表面的结构中形成开口，其中开口形成步骤发生在包括至少一个聚集室的工具中。然后在工具中的暴露的金属表面上形成至少部分牺牲的封装层，以防止暴露的金属表面与环境的反应。从而防止了金属的暴露。

40. 发明申请

US20060189137A1 METHOD OF FORMING DAMASCENE FILAMENT WIRES AND THE STRUCTURE SO FORMED 失效
标题翻译：形成大分子纤维丝的方法和形成的结构
公开(公告)号：US20060189137A1
公开(公告)日：2006-08-24
申请号：US10906552
申请日：2005-02-24
申请人： Brent Anderson , Andres Bryant , Jeffrey Gambino , Anthony Stamper
发明人： Brent Anderson , Andres Bryant , Jeffrey Gambino , Anthony Stamper
IPC分类号： H01L21/302 , H01L23/48 , H01L29/40 , H01L21/461
CPC分类号： H01L21/31144 , H01L21/76808 , H01L21/76811 , H01L21/76816 , H01L21/76831 , H01L21/76835 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor device, and the device so formed. Depositing a low dielectric constant material on a substrate. Depositing a hard mask on the low dielectric constant material. Forming an at least one first feature within the low dielectric constant material and the hard mask. Depositing a conformal liner over the hard mask and within the at least one feature, wherein the liner occupies more than at least 2% of a volume of the at least one feature, and wherein a thickness of the liner is at least approximately ⅓ a minimum width of the at least one feature. Metallizing the at least one feature.
摘要翻译：形成半导体器件的方法和如此形成的器件。在基板上沉积低介电常数材料。在低介电常数材料上沉积硬掩模。在低介电常数材料和硬掩模内形成至少一个第一特征。在所述硬掩模上并且在所述至少一个特征内沉积保形衬垫，其中所述衬垫占据所述至少一个特征的体积的至少2％，并且其中所述衬垫的厚度为至少约1/3 所述至少一个特征的最小宽度。金属化至少一个特征。

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