专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20130307656A1 Stacked Through-Silicon Via (TSV) Transformer Structure 有权
标题翻译：堆叠通硅（TSV）变压器结构
公开(公告)号：US20130307656A1
公开(公告)日：2013-11-21
申请号：US13474239
申请日：2012-05-17
申请人： Gary D. Carpenter , Alan J. Drake , Rachel Gordin , Michael J. Shapiro , Edmund J. Sprogis
发明人： Gary D. Carpenter , Alan J. Drake , Rachel Gordin , Michael J. Shapiro , Edmund J. Sprogis
IPC分类号： H01F27/40 , H01F7/06 , H01F27/28
CPC分类号： H01L23/5227 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L2224/0401 , H01L2224/04042 , H01L2224/0557 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/30107 , Y10T29/49071 , H01L2924/00014 , H01L2924/00
摘要： A distributed active transformer is provided comprising a primary and a secondary winding. The primary winding comprises a first set of conductive vias extending in a direction between a first surface and a second surface of an element, a first set of first electrically conductive lines extending along the first surface, and a first set of second electrically conductive lines extending along the second surface. The secondary winding comprises a second set of conductive vias extending in a direction between the first surface and the second surface, a second set of first electrically conductive lines extending along the first surface, and a second set of second electrically conductive lines extending along the second surface. When energized, the primary winding generates magnetic flux extending in a direction parallel to the first surface and the second surface. The secondary winding receives energy transferred by the magnetic flux generated by the primary winding.
摘要翻译：提供一种分布式有源变压器，其包括初级和次级绕组。初级绕组包括在元件的第一表面和第二表面之间的方向上延伸的第一组导电通孔，沿着第一表面延伸的第一组第一导电线，以及延伸的第一组第二导电线沿着第二个表面。次级绕组包括在第一表面和第二表面之间的方向上延伸的第二组导电通孔，沿着第一表面延伸的第二组第一导电线，以及沿着第二表面延伸的第二组第二导电线表面。当通电时，初级绕组产生沿平行于第一表面和第二表面的方向延伸的磁通量。次级绕组接收由初级绕组产生的磁通传递的能量。

32. 发明申请

US20110291279A1 SEMICONDUCTOR ARTICLE HAVING A THROUGH SILICON VIA AND GUARD RING 有权
标题翻译：具有通过硅和保护环的半导体器件
公开(公告)号：US20110291279A1
公开(公告)日：2011-12-01
申请号：US12791398
申请日：2010-06-01
申请人： Vincent J. McGahay , Michael J. Shapiro
发明人： Vincent J. McGahay , Michael J. Shapiro
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/585 , H01L21/76898 , H01L23/481 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a semiconductor article which includes a semiconductor base portion, a back end of the line (BEOL) wiring portion on the semiconductor base portion, a through silicon via and a guard ring. The semiconductor base portion is made of a semiconductor material. The BEOL wiring portion includes a plurality of wiring layers having metallic wiring and insulating material. The BEOL wiring portion does not include a semiconductor material. The through silicon via provides a conductive path through the BEOL wiring portion and the semiconductor base portion. The guard ring surrounds the through silicon via in the BEOL wiring portion.
摘要翻译：公开了一种半导体制品，其包括半导体基底部分，半导体基底部分上的线（BEOL）布线部分的后端，贯穿硅通孔和保护环。半导体基部由半导体材料制成。 BEOL布线部分包括具有金属布线和绝缘材料的多个布线层。 BEOL布线部分不包括半导体材料。通硅通孔提供穿过BEOL布线部分和半导体基底部分的导电路径。保护环围绕BEOL布线部分中的贯穿硅通孔。

33. 发明申请

US20110215442A1 ALIGNMENT OF WAFERS FOR 3D INTEGRATION 有权
标题翻译：用于3D集成的WAFERS对齐
公开(公告)号：US20110215442A1
公开(公告)日：2011-09-08
申请号：US12719241
申请日：2010-03-08
申请人： Dmitriy Shneyder , Srinivasan Rangarajan , Michael J. Shapiro , Anthony K. Stamper , Huilong Zhu
发明人： Dmitriy Shneyder , Srinivasan Rangarajan , Michael J. Shapiro , Anthony K. Stamper , Huilong Zhu
IPC分类号： H01L23/48 , G01B11/27 , G01J3/02 , G06F15/00 , B32B38/00
CPC分类号： B32B38/00 , G01B11/27 , G01J3/02 , G06F15/00 , H01L23/48 , H01L2924/0002 , H01L2924/00
摘要： A method of aligning substrates, e.g., semiconductor wafers, is provided in which a first substrate can be at least coarsely aligned atop a second substrate. Each substrate can have a pattern thereon, wherein the pattern of the first substrate can be aligned with a window of the first substrate. A return signal can be returned from simultaneously illuminating the patterns of the first and second substrates through the window in the first substrate. The return signal can be compared to at least one stored signal to determine relative misalignment between the first and second substrates. A position of at least one of the first and second substrates can be altered relative to a position of the other of the first and second substrates to address the misalignment.
摘要翻译：提供了对准例如半导体晶片的衬底的方法，其中第一衬底可以至少在第二衬底的顶部上对齐。每个衬底可以具有其上的图案，其中第一衬底的图案可以与第一衬底的窗口对准。可以通过第一衬底中的窗口同时照亮第一和第二衬底的图案来返回返回信号。可以将返回信号与至少一个存储的信号进行比较，以确定第一和第二基板之间的相对不对准。可以相对于第一和第二基板中的另一个的位置改变第一和第二基板中的至少一个的位置，以解决未对准。

34. 发明授权

US07737003B2 Method and structure for optimizing yield of 3-D chip manufacture 有权
标题翻译：优化3-D芯片制造产量的方法和结构
公开(公告)号：US07737003B2
公开(公告)日：2010-06-15
申请号：US11163226
申请日：2005-10-11
申请人： Edward M. DeMulder , Sarah H. Knickerbocker , Michael J. Shapiro , Albert M. Young
发明人： Edward M. DeMulder , Sarah H. Knickerbocker , Michael J. Shapiro , Albert M. Young
IPC分类号： H01L21/00
CPC分类号： H01L21/8221 , H01L27/0688 , H01L2224/13
摘要： The process begins with separate device wafers having complimentary chips. Thin metal capture pads, having a preferred thickness of about 10 microns so that substantial pressure may be applied during processing without damaging capture pads, are deposited on both device wafers, which are then tested and mapped for good chip sites. A handle wafer is attached to one device wafer, which can then be thinned to improve via etching and filling. Capture pads are removed and replaced after thinning. The device wafer with handle wafer is diced, and good chips with attached portions of the diced handle wafer are positioned and bonded to the good chip sites of the other device wafer, and the handle wafer portions are removed. The device wafer having known good 3-D chips then undergoes final processing.
摘要翻译：该过程开始于具有互补芯片的单独的器件晶片。薄金属捕获垫具有约10微米的优选厚度，使得在处理过程中可能施加大的压力而不损坏捕获垫，沉积在两个器件晶片上，然后对其进行测试和映射以获得良好的芯片位置。处理晶片连接到一个器件晶片，然后可以通过蚀刻和填充来减薄其改进。捕获垫被去除并在变薄后更换。切割具有处理晶片的器件晶片，并且将具有切割手柄晶片的附接部分的良好芯片定位并结合到另一器件晶片的良好芯片位置，并移除处理晶片部分。具有已知良好3-D芯片的器件晶片然后进行最终处理。

35. 发明授权

US06573538B2 Semiconductor device with internal heat dissipation 有权
标题翻译：具有内部散热的半导体器件
公开(公告)号：US06573538B2
公开(公告)日：2003-06-03
申请号：US09191721
申请日：1998-11-12
申请人： William T. Motsiff , Michael J. Shapiro
发明人： William T. Motsiff , Michael J. Shapiro
IPC分类号： H01L2348
CPC分类号： H01L23/585 , H01L23/3677 , H01L2924/0002 , H01L2924/00
摘要： A thermal management system for a semiconductor chip including at least one region of thermally conductive material included internally within the semiconductor chip.
摘要翻译：一种用于半导体芯片的热管理系统，包括内部包含导热材料的至少一个区域。

36. 发明授权

US6150258A Plasma deposited fluorinated amorphous carbon films 有权
标题翻译：等离子体沉积的氟化无定形碳膜
公开(公告)号：US6150258A
公开(公告)日：2000-11-21
申请号：US303538
申请日：1999-05-03
申请人： Thomas Weller Mountsier , Michael J. Shapiro
发明人： Thomas Weller Mountsier , Michael J. Shapiro
IPC分类号： H01L21/314 , H01L21/4763
CPC分类号： H01L21/3146 , H01L21/314
摘要： An interlevel dielectric stack for use in semiconductor devices is provided. The interlevel stack includes a bottom adhesion layer, a middle layer composed of a fluorinated amorphous carbon film, and a top adhesion layer. The bottom and top adhesion layers are composed of a silicon carbide material containing hydrogen. The dielectric stack is subjected to rigorous adhesion and thermal testing. A single continuous process for depositing the dielectric stack in a high density plasma reactor is also provided.
摘要翻译：提供了一种用于半导体器件的层间电介质叠层。层间堆叠包括底部粘附层，由氟化无定形碳膜构成的中间层和顶部粘合层。底部和顶部粘附层由含有氢的碳化硅材料组成。电介质叠层经过严格的粘合和热测试。还提供了用于在高密度等离子体反应器中沉积电介质叠层的单一连续工艺。

37. 发明授权

US6057250A Low temperature reflow dielectric-fluorinated BPSG 失效
标题翻译：低温回流电介质氟化BPSG
公开(公告)号：US6057250A
公开(公告)日：2000-05-02
申请号：US14431
申请日：1998-01-27
申请人： Markus Kirchhoff , Ashima Chakravarti , Matthias Ilg , Kevin A. McKinley , Son V. Nguyen , Michael J. Shapiro
发明人： Markus Kirchhoff , Ashima Chakravarti , Matthias Ilg , Kevin A. McKinley , Son V. Nguyen , Michael J. Shapiro
IPC分类号： H01L21/31 , C23C16/40 , H01L21/316 , H01L21/225 , H01L21/469
CPC分类号： H01L21/02271 , C23C16/401 , H01L21/02131 , H01L21/02211 , H01L21/31625 , H01L21/31629
摘要： An apparatus and method are provided for forming a fluorine doped borophosphosilicate (F-BPSG) glass on a semiconductor device using a low pressure chemical vapor deposition process. The F-BPSG glass exhibits a substantially void-free and particle-free layer on the substrate for structures having gaps as narrow as 0.10 microns and with aspect ratios of 6:1. The reactant gases include sources of boron and phosphorous dopants, oxygen and a mixture of TEOS and FTES. Using a mixture of TEOS and FTES in a low pressure CVD process provides a F-BPSG layer having the above enhanced characteristics. It is a preferred method of the invention to perform the deposition at a temperature of about 750-850.degree. C. and a pressure of 1 to 3 torr to provide for in situ reflow of the F-BPSG during the deposition process. An anneal is also preferred under similar conditions in the same chemical vapor deposition chamber to further planarize the F-BPSG surface. A F-BPSG glass and semiconductor wafers having a layer of fluorine doped BPSG thereon formed by the method and apparatus of the invention are also provided.
摘要翻译：提供了一种用于在半导体器件上使用低压化学气相沉积工艺形成氟掺杂硼磷硅酸（F-BPSG）玻璃的装置和方法。 F-BPSG玻璃在基板上表现出基本上无空隙和无颗粒的层，其结构具有窄至0.10微米的间隙，纵横比为6:1。反应物气体包括硼和磷掺杂剂的源，氧和TEOS和FTES的混合物。在低压CVD工艺中使用TEOS和FTES的混合物提供具有上述增强特性的F-BPSG层。本发明的优选方法是在约750-850℃的温度和1至3托的压力下进行沉积，以在沉积过程中提供F-BPSG的原位回流。在相同的化学气相沉积室中的相似条件下还优选退火以进一步平坦化F-BPSG表面。还提供了通过本发明的方法和装置形成的具有氟掺杂BPSG层的F-BPSG玻璃和半导体晶片。

38. 发明授权

US08558345B2 Integrated decoupling capacitor employing conductive through-substrate vias 有权
标题翻译：集成的去耦电容采用导电贯穿衬底通孔
公开(公告)号：US08558345B2
公开(公告)日：2013-10-15
申请号：US12614883
申请日：2009-11-09
申请人： Tae Hong Kim , Edmund J. Sprogis , Michael F. McAllister , Michael J. Shapiro
发明人： Tae Hong Kim , Edmund J. Sprogis , Michael F. McAllister , Michael J. Shapiro
IPC分类号： H01L27/108 , H01L29/94 , H01L23/04 , H01L21/02
CPC分类号： H01L28/40 , H01L21/76898 , H01L23/481 , H01L23/49827 , H01L23/642 , H01L24/16 , H01L25/0657 , H01L2224/13025 , H01L2225/06513 , H01L2225/06541 , H01L2924/01078 , H01L2924/10253 , H01L2924/12044 , H01L2924/1301 , H01L2924/1305 , H01L2924/15311 , H01L2924/19041 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要： A capacitor in a semiconductor substrate employs a conductive through-substrate via (TSV) as an inner electrode and a columnar doped semiconductor region as an outer electrode. The capacitor provides a large decoupling capacitance in a small area, and does not impact circuit density or a Si3D structural design. Additional conductive TSV's can be provided in the semiconductor substrate to provide electrical connection for power supplies and signal transmission therethrough. The capacitor has a lower inductance than a conventional array of capacitors having comparable capacitance, thereby enabling reduction of high frequency noise in the power supply system of stacked semiconductor chips.
摘要翻译：半导体衬底中的电容器采用导电贯穿衬底通孔（TSV）作为内部电极和柱状掺杂半导体区域作为外部电极。电容器在小面积上提供大的去耦电容，并且不影响电路密度或Si3D结构设计。可以在半导体衬底中提供附加的导电TSV，以提供用于电源和通过其的信号传输的电连接。电容器具有比具有相当电容的传统电容器阵列更低的电感，从而能够降低层叠半导体芯片的电源系统中的高频噪声。

39. 发明授权

US08487447B2 Semiconductor structure having offset passivation to reduce electromigration 有权
标题翻译：具有偏移钝化以减少电迁移的半导体结构
公开(公告)号：US08487447B2
公开(公告)日：2013-07-16
申请号：US13111283
申请日：2011-05-19
申请人： Mario J. Interrante , Gary LaFontant , Michael J. Shapiro , Thomas A. Wassick , Bucknell C. Webb
发明人： Mario J. Interrante , Gary LaFontant , Michael J. Shapiro , Thomas A. Wassick , Bucknell C. Webb
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/3171 , H01L23/481 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L2224/02163 , H01L2224/0401 , H01L2224/05147 , H01L2224/05551 , H01L2224/0557 , H01L2224/05571 , H01L2224/05647 , H01L2224/0569 , H01L2224/06131 , H01L2224/06134 , H01L2224/13005 , H01L2224/13016 , H01L2224/13022 , H01L2224/13025 , H01L2224/13026 , H01L2224/13028 , H01L2224/131 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/014 , H01L2924/15311 , H01L2924/049 , H01L2924/053 , H01L2224/05552
摘要： A semiconductor structure which includes a plurality of stacked semiconductor chips in a three dimensional configuration. There is a first semiconductor chip in contact with a second semiconductor chip. The first semiconductor chip includes a through silicon via (TSV) extending through the first semiconductor chip; an electrically conducting pad at a surface of the first semiconductor chip, the TSV terminating in contact at a first side of the electrically conducting pad; a passivation layer covering the electrically conducting pad, the passivation layer having a plurality of openings; and a plurality of electrically conducting structures formed in the plurality of openings and in contact with a second side of the electrically conducting pad, the contact of the plurality of electrically conducting structures with the electrically conducting pad being offset with respect to the contact of the TSV with the electrically conducting pad.
摘要翻译：一种半导体结构，其包括三维结构中的多个层叠半导体芯片。存在与第二半导体芯片接触的第一半导体芯片。第一半导体芯片包括延伸穿过第一半导体芯片的贯穿硅通孔（TSV）; 在所述第一半导体芯片的表面处的导电焊盘，所述TSV终止于所述导电焊盘的第一侧接触; 覆盖所述导电焊盘的钝化层，所述钝化层具有多个开口; 以及形成在所述多个开口中并与所述导电垫的第二侧接触的多个导电结构，所述多个导电结构与所述导电垫的接触相对于所述TSV的接触而偏移与导电垫。

40. 发明授权

US08383505B2 Solder ball contact susceptible to lower stress 有权
标题翻译：焊球接触容易受到较低的应力
公开(公告)号：US08383505B2
公开(公告)日：2013-02-26
申请号：US13080105
申请日：2011-04-05
申请人： Luc Guerin , Mario J. Interrante , Michael J. Shapiro , Thuy Tran-Quinn , Van T. Truong
发明人： Luc Guerin , Mario J. Interrante , Michael J. Shapiro , Thuy Tran-Quinn , Van T. Truong
IPC分类号： H01L21/00
CPC分类号： H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02166 , H01L2224/03462 , H01L2224/03618 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05171 , H01L2224/05572 , H01L2224/05655 , H01L2224/05657 , H01L2224/0566 , H01L2224/05681 , H01L2224/10126 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13022 , H01L2224/13111 , H01L2224/13113 , H01L2224/13118 , H01L2224/1312 , H01L2224/13139 , H01L2224/13147 , H01L2924/00014 , H01L2924/01074 , H01L2924/01029 , H01L2924/01028 , H01L2924/01026 , H01L2224/05552
摘要： A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.
摘要翻译：焊球接触和制造焊球接触的方法包括：在集成电路（IC）芯片和金属焊盘上形成有通孔的第一绝缘层; 设置在所述通孔内和所述第一绝缘层的围绕所述通孔的部分上的凸块下冶金（UBM）结构; 第二绝缘层，形成在所述UBM结构的位于所述通孔的中心的外部的上表面上; 以及填充通孔并且设置在UBM结构的与通孔接触的内部的上表面上方的焊球，其中在焊球下面的UBM结构具有比焊球更大的直径。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式