专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07887711B2 Method for etching chemically inert metal oxides 有权
标题翻译：蚀刻化学惰性金属氧化物的方法
公开(公告)号：US07887711B2
公开(公告)日：2011-02-15
申请号：US10170914
申请日：2002-06-13
申请人： Douglas A. Buchanan , Eduard A. Cartier , Evgeni Gousev , Harald Okorn-Schmidt , Katherine L. Saenger
发明人： Douglas A. Buchanan , Eduard A. Cartier , Evgeni Gousev , Harald Okorn-Schmidt , Katherine L. Saenger
IPC分类号： B44C1/22 , H01L21/00
CPC分类号： H01L21/31122 , Y10S438/924
摘要： A system and method for patterning metal oxide materials in a semiconductor structure. The method comprises a first step of depositing a layer of metal oxide material over a substrate. Then, a patterned mask layer is formed over the metal oxide layer leaving one or more first regions of the metal oxide layer exposed. The exposed first regions of the metal oxide layer are then subjected to an energetic particle bombardment process to thereby damage the first regions of the metal oxide layer. The exposed and damaged first regions of the metal oxide layer are then removed by a chemical etch. Advantageously, the system and method is implemented to provide high-k dielectric materials in small-scale semiconductor devices. Besides using the ion implantation damage (I/I damage) plus wet etch technique to metal oxides (including metal oxides not previously etchable by wet methods), other damage methods including lower energy, plasma-based ion bombardment, may be implemented. Plasma-based ion bombardment typically uses simpler and cheaper tooling, and results in less collateral damage to underlying structures as the damage profile can be more easily localized to the depth of the thin metal oxide film.
摘要翻译：一种在半导体结构中图案化金属氧化物材料的系统和方法。该方法包括在衬底上沉积金属氧化物材料层的第一步骤。然后，在金属氧化物层之上形成图案化掩模层，留下暴露金属氧化物层的一个或多个第一区域。接着对金属氧化物层的暴露的第一区域进行高能粒子轰击处理，从而破坏金属氧化物层的第一区域。然后通过化学蚀刻去除金属氧化物层的暴露和损坏的第一区域。有利地，该系统和方法被实现以在小规模半导体器件中提供高k电介质材料。除了使用离子注入损伤（I / I损伤）以及湿法蚀刻技术对金属氧化物（包括以前不能用湿法蚀刻的金属氧化物）外，还可以实施包括较低能量，基于等离子体的离子轰击等其他损伤方法。基于等离子体的离子轰击通常使用更简单和更便宜的工具，并且导致对下面的结构的较少的附带损伤，因为损伤分布可以更容易地定位于薄金属氧化物膜的深度。

32. 发明授权

US07745278B2 Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high K dielectrics 有权
标题翻译：在具有高K电介质的CMOS器件制造中实现势垒层的选择性实现以实现阈值电压控制
公开(公告)号：US07745278B2
公开(公告)日：2010-06-29
申请号：US12211530
申请日：2008-09-16
申请人： Nestor A. Bojarczuk, Jr. , Cyril Cabral, Jr. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Nestor A. Bojarczuk, Jr. , Cyril Cabral, Jr. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L21/8238
CPC分类号： H01L29/513 , H01L21/28079 , H01L21/28088 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.
摘要翻译：一种形成CMOS结构的方法及其制造的器件，具有改进的阈值电压和平带电压稳定性。本发明的方法包括提供具有nFET区和pFET区的半导体衬底的步骤; 在所述半导体衬底上形成包括在高k电介质顶上的绝缘夹层的电介质叠层; 从nFET区域去除绝缘中间层而不从pFET区域去除绝缘中间层; 以及在pFET区域中提供至少一个栅极堆叠以及在nFET区域中提供至少一个栅极堆叠。绝缘中间层可以是AlN或AlOxNy。高k电介质可以是HfO 2，硅酸铪或铪硅氮氧化物。可以通过包括HCl / H2O2过氧化物溶液的湿蚀刻从nFET区域去除绝缘中间层。

33. 发明授权

US07741188B2 Deep trench (DT) metal-insulator-metal (MIM) capacitor 有权
标题翻译：深沟槽（DT）金属绝缘体金属（MIM）电容器
公开(公告)号：US07741188B2
公开(公告)日：2010-06-22
申请号：US12053846
申请日：2008-03-24
申请人： Thomas W. Dyer , Eduard A. Cartier , Michael P. Chudzik , Naim Moumen
发明人： Thomas W. Dyer , Eduard A. Cartier , Michael P. Chudzik , Naim Moumen
IPC分类号： H01L21/20
CPC分类号： H01L28/90 , H01L21/84 , H01L27/1087 , H01L29/66181 , Y10S438/957
摘要： A deep trench metal-insulator-metal (MIM) capacitor in an SOI-type substrate. In the deep trench, a layer of TiN, followed by a layer of high-k dielectric, followed by a second layer of TiN. The resulting capacitor is completely buried below the SOI layer, thereby allowing for subsequent structures to be placed over the deep trench.
摘要翻译： SOI型衬底中的深沟金属绝缘体金属（MIM）电容器。在深沟槽中，形成TiN层，接着是高k介电层，随后是第二层TiN。所得到的电容器被完全掩埋在SOI层的下面，从而允许随后的结构放置在深沟槽上。

34. 发明申请

US20090302399A1 Using Metal/Metal Nitride Bilayers as Gate Electrodes in Self-Aligned Aggressively Scaled CMOS Devices 有权
标题翻译：使用金属/金属氮化物二层作为自对准激光缩放CMOS器件中的栅极电极
公开(公告)号：US20090302399A1
公开(公告)日：2009-12-10
申请号：US12542087
申请日：2009-08-17
申请人： Eduard A. Cartier , Matthew W. Copel , Bruce B. Doris , Rajarao Jammy , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri , Keith Kwong Hon Wong
发明人： Eduard A. Cartier , Matthew W. Copel , Bruce B. Doris , Rajarao Jammy , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri , Keith Kwong Hon Wong
IPC分类号： H01L29/78
CPC分类号： H01L21/823842
摘要： The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.
摘要翻译：本发明涉及包括位于半导体衬底的一个区域上的至少一个nMOS器件的CMOS结构; 以及位于半导体衬底的另一区域上的至少一个pMOS器件。根据本发明，所述至少一个nMOS器件包括栅极堆叠，其包括栅极电介质，功函数小于4.2eV的低功函数元素金属，原位金属覆盖层和多晶硅封装层，以及所述至少一个pMOS包括包括栅极电介质的栅极堆叠，具有大于4.9eV的功函数的高功函数元素金属，金属覆盖层和多晶硅封装层。本发明还提供了制造这种CMOS结构的方法。

35. 发明申请

US20090236691A1 DEEP TRENCH (DT) METAL-INSULATOR-METAL (MIM) CAPACITOR 有权
标题翻译： DEEP TRENCH（DT）金属绝缘子金属（MIM）电容器
公开(公告)号：US20090236691A1
公开(公告)日：2009-09-24
申请号：US12053846
申请日：2008-03-24
申请人： Thomas W. Dyer , Eduard A. Cartier , Michael P. Chudzik , Naim Moumen
发明人： Thomas W. Dyer , Eduard A. Cartier , Michael P. Chudzik , Naim Moumen
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L28/90 , H01L21/84 , H01L27/1087 , H01L29/66181 , Y10S438/957
摘要： A deep trench metal-insulator-metal (MIM) capacitor in an SOI-type substrate. In the deep trench, a layer of TiN, followed by a layer of high-k dielectric, followed by a second layer of TiN. The resulting capacitor is completely buried below the SOI layer, thereby allowing for subsequent structures to be placed over the deep trench.
摘要翻译： SOI型衬底中的深沟金属绝缘体金属（MIM）电容器。在深沟槽中，形成TiN层，接着是高k介电层，随后是第二层TiN。所得到的电容器被完全掩埋在SOI层的下面，从而允许随后的结构放置在深沟槽上。

36. 发明授权

US07479683B2 Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics 失效
标题翻译：在具有高k电介质的CMOS器件制造中实现势垒层的选择性实现以实现阈值电压控制
公开(公告)号：US07479683B2
公开(公告)日：2009-01-20
申请号：US10957342
申请日：2004-10-01
申请人： Nestor A. Bojarczuk, Jr. , Cyril Cabral, Jr. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Nestor A. Bojarczuk, Jr. , Cyril Cabral, Jr. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L29/94 , H01L29/76
CPC分类号： H01L29/513 , H01L21/28079 , H01L21/28088 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first stack of a pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET device is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.
摘要翻译：本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。该结构还包括位于一些器件通道顶部的pFET器件的第一堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。

37. 发明申请

US20090011610A1 SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE TRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH K DIELECTRICS 有权
标题翻译：采用高K电介质的CMOS器件制造中实现栅极电压控制的障碍层的选择性实现
公开(公告)号：US20090011610A1
公开(公告)日：2009-01-08
申请号：US12211530
申请日：2008-09-16
申请人： Nestor A. Bojarczuk, JR. , Cyril Cabral, JR. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Nestor A. Bojarczuk, JR. , Cyril Cabral, JR. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L21/31
CPC分类号： H01L29/513 , H01L21/28079 , H01L21/28088 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.
摘要翻译：一种形成CMOS结构的方法及其制造的器件，具有改进的阈值电压和平带电压稳定性。本发明的方法包括提供具有nFET区和pFET区的半导体衬底的步骤; 在所述半导体衬底上形成包括在高k电介质顶上的绝缘夹层的电介质叠层; 从nFET区域去除绝缘中间层而不从pFET区域去除绝缘中间层; 以及在pFET区域中提供至少一个栅极堆叠以及在nFET区域中提供至少一个栅极堆叠。绝缘中间层可以是AlN或AlOxNy。高k电介质可以是HfO 2，硅酸铪或铪硅氮氧化物。可以通过包括HCl / H2O2过氧化物溶液的湿蚀刻从nFET区域去除绝缘中间层。

38. 发明申请

US20080308872A1 CMOS TRANSISTORS WITH DIFFERENTIAL OXYGEN CONTENT HIGH-K DIELECTRICS 失效
标题翻译：具有差分氧含量高K电介质的CMOS晶体管
公开(公告)号：US20080308872A1
公开(公告)日：2008-12-18
申请号：US11763047
申请日：2007-06-14
申请人： Huiming Bu , Eduard A. Cartier , Bruce B. Doris , Young-Hee Kim , Barry Linder , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen
发明人： Huiming Bu , Eduard A. Cartier , Bruce B. Doris , Young-Hee Kim , Barry Linder , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823864 , H01L21/823814 , H01L21/823857 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/4908 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention.
摘要翻译：在半导体衬底上形成包含第一高k电介质部分的NFET和包含第二高k栅极电介质部分的PFET。栅极侧壁氮化物形成在NFET的栅极上，而PFET的侧壁保持没有栅极侧壁氮化物。直接在PFET栅极堆叠的侧壁上和NFET上的栅极侧壁氮化物上形成氧化物间隔物。在高温处理之后，第一和第二介质部分含有非化学计量的缺氧高k电介质材料。半导体结构在氧气环境中进行退火，在该环境中，氧气通过氧化物间隔物扩散到第二高k电介质部分。 PFET包括更高化学计量的高k电介质材料，并且NFET包含较少化学计量的高k电介质材料。本发明优化了PFET和NFET的阈值电压。

39. 发明申请

US20080293259A1 METHOD OF FORMING METAL/HIGH-k GATE STACKS WITH HIGH MOBILITY 有权
标题翻译：形成具有高移动性的金属/高k栅极堆叠的方法
公开(公告)号：US20080293259A1
公开(公告)日：2008-11-27
申请号：US12187767
申请日：2008-08-07
申请人： Wanda Andreoni , Alessandro C. Callegari , Eduard A. Cartier , Alessandro Curioni , Christopher P. D'Emic , Evgeni Gousev , Michael A. Gribelyuk , Paul C. Jamison , Rajarao Jammy , Dianne L. Lacey , Fenton R. McFeely , Vijay Narayanan , Carlo A. Pignedoli , Joseph F. Shepard, JR. , Sufi Zafar
发明人： Wanda Andreoni , Alessandro C. Callegari , Eduard A. Cartier , Alessandro Curioni , Christopher P. D'Emic , Evgeni Gousev , Michael A. Gribelyuk , Paul C. Jamison , Rajarao Jammy , Dianne L. Lacey , Fenton R. McFeely , Vijay Narayanan , Carlo A. Pignedoli , Joseph F. Shepard, JR. , Sufi Zafar
IPC分类号： H01L21/263
CPC分类号： H01L21/28176 , H01L29/4908 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6656 , H01L29/66575 , H01L29/66772 , H01L29/7833 , H01L29/78684
摘要： The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.
摘要翻译：本发明提供具有高移动性和低界面电荷的栅叠层结构，以及包括其的半导体器件，即金属氧化物半导体场效应晶体管（MOSFET）。在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间。本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（大约800℃）。本发明中使用的高温退火提供了具有大约8×10 10电荷/ cm 2或更小的电荷泵浦的界面状态密度，约250cm 2 / s以上的峰值迁移率和基本上没有约6.0×10 12反相电荷/ cm 2以上的迁移率降解。

40. 发明申请

US20080017936A1 Semiconductor device structures (gate stacks) with charge compositions 审中-公开
标题翻译：具有电荷组成的半导体器件结构（栅极堆叠）
公开(公告)号：US20080017936A1
公开(公告)日：2008-01-24
申请号：US11477707
申请日：2006-06-29
申请人： Douglas A. Buchanan , Eduard A. Cartier , Kevin K. Chan , Leland Chang , Christopher P. D'Emic , Martin M. Frank , Evgeni Gusev , Jin-Ping Han , Rajarao Jammy , Vamsi K. Paruchuri , Sufi Zafar
发明人： Douglas A. Buchanan , Eduard A. Cartier , Kevin K. Chan , Leland Chang , Christopher P. D'Emic , Martin M. Frank , Evgeni Gusev , Jin-Ping Han , Rajarao Jammy , Vamsi K. Paruchuri , Sufi Zafar
IPC分类号： H01L29/94 , H01L29/76 , H01L31/00
CPC分类号： H01L21/823857 , H01L21/28167 , H01L21/28194 , H01L29/51 , H01L29/513 , H01L29/78
摘要： A semiconductor structure, particularly a gate stack, useful in field effect transistors (FETs) in which the threshold voltage thereof is controlled by introducing a fixed spatial distribution of electric charge density to the gate dielectric material and a method of forming the same are provided. nFETs and/or pFETs structures are disclosed. In accordance with the present invention, the fixed spatial distribution of electric charge density of the gate stack or FET denotes an electrical charge density that occupies space which remains substantially constant as a function of time under device operation conditions and is non-zero at least at one location within the dielectric material or at its interface with the channel, gate electrode, spacer, or any other structural elements of the device.
摘要翻译：提供了一种半导体结构，特别是栅极堆叠，其中通过向栅极电介质材料引入电荷密度的固定空间分布来控制其阈值电压的场效应晶体管（FET）及其形成方法。公开了nFET和/或pFET结构。根据本发明，栅极堆叠或FET的电荷密度的固定空间分布表示占空间的电荷密度，其在器件操作条件下作为时间的函数保持基本上恒定，并且至少在电介质材料内的一个位置，或其与沟道，栅电极，间隔物或器件的任何其它结构元件的界面。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式