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31. 发明授权

US08578311B1 Method and system for optimal diameter bounding of designs with complex feed-forward components 失效
标题翻译：具有复杂前馈组件的设计的最佳直径界限的方法和系统
公开(公告)号：US08578311B1
公开(公告)日：2013-11-05
申请号：US13467425
申请日：2012-05-09
申请人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
发明人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A computer-implemented method includes a processor identifying, within the netlist, at least one strongly connected components (SCCs) that has a reconvergent fanin input with at least two input paths from the reconvergent fanin input having a different propagation delay to the SCC. The method then computes an additive diameter for the netlist comprising at least one SCC, where the additive diameter includes a fanin additive diameter determined based on a propagation delay difference of the at least two input paths to a SCC and a number of complex feed-forward components within at least one input path. In response to the reconvergent fanin input to the SCC providing a binate function, the method computes a multiplicative diameter for the SCC utilizing a least common multiple (LCM) derived from one or more propagation delay differences across each reconvergent fanin input leading to the SCC.
摘要翻译：计算机实现的方法包括处理器，其在网表内识别至少一个强连接组件（SCC），其具有从具有与SCC不同的传播延迟的再聚合扇区输入的至少两个输入路径的重新接收扇区输入。该方法然后计算包括至少一个SCC的网表的添加剂直径，其中添加剂直径包括基于至少两个输入路径到SCC的传播延迟差和多个复合前馈确定的扇形添加剂直径在至少一个输入路径内的组件。响应于提供一个功能的SCC的再混合扇区输入，该方法利用从通向SCC的每个再聚合扇区输入上的一个或多个传播延迟差导出的最小公倍数（LCM）来计算SCC的乘法直径。

32. 发明授权

US08527922B1 Method and system for optimal counterexample-guided proof-based abstraction 失效
标题翻译：用于最佳反例引导证明抽象的方法和系统
公开(公告)号：US08527922B1
公开(公告)日：2013-09-03
申请号：US13455789
申请日：2012-04-25
申请人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
发明人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
IPC分类号： G06F17/50 , G06F7/60
CPC分类号： G06F17/504
摘要： A computer-implemented method includes receiving an input containing a candidate netlist, a target, and a number, K, of cycles of interest, where K represents a number of cycles required to be analyzed for the proof-based abstraction. In response to receiving the inputs, a computing device builds an inductively unrolled netlist, utilizing random, symbolic initial values, for K cycles and provides the unrolled netlist with a first initial value constraint to a satisfiability (SAT) solver, with the first initial value constraint empty. The method includes determining whether a result of the SAT solver is satisfiable, and in response to the result not being satisfiable, performing an abstraction on the netlist and outputting the abstraction. However, in response to the result being satisfiable, the method includes performing one of: (a) outputting a valid counterexample of the original netlist; and (b) lazily adding initial value constraints to avoid spurious counterexamples.
摘要翻译：计算机实现的方法包括接收包含候选网表，目标和感兴趣的周期数K的输入，其中K表示为了基于证明的抽象而需要分析的周期数。响应于接收到输入，计算设备利用K周期的随机符号初始值构建感应式展开的网表，并向第一初始值约束提供具有第一初始值的可满足性（SAT）求解器的第一初始值约束约束空。该方法包括确定SAT求解器的结果是否可满足，并且响应于结果不可满足，在网表上执行抽象并输出抽象。然而，响应于可满足的结果，该方法包括执行以下之一：（a）输出原始网表的有效反例; 和（b）延迟添加初始值约束以避免虚假的反例。

33. 发明授权

US08418119B2 Logical circuit netlist reduction and model simplification using simulation results containing symbolic values 失效
标题翻译：逻辑电路网表减少和模型简化，使用包含符号值的模拟结果
公开(公告)号：US08418119B2
公开(公告)日：2013-04-09
申请号：US13104573
申请日：2011-05-10
申请人： Michael L. Case , Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony
发明人： Michael L. Case , Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony
IPC分类号： G06F9/455
CPC分类号： G06F17/505
摘要： A logic synthesis program, method and system for simplifying and/or reducing a logic design receives output from a logic simulator that uses symbolic values for stimulus and contains symbolic values in the logic simulator output. Relationships between the nodes dependent on symbolic values can be used to merge nodes or otherwise simplify the logic design. Behaviors such as oscillators, transient values, identical signals, dependent logical states and chicken-switch determined states that depend on the symbolic values can be detected in the simulation results and the netlist simplified using the results of the detection. The netlist can be simplified by inserting registers to represent nodes that assume a symbolic value or combination based on symbolic values either statically or after an initial transient. Oscillating nodes can be replaced with equivalent oscillator circuits, and nodes having values dependent on chicken-switch operation can be detected and replaced with registers initialized from the chicken-switch input states.
摘要翻译：用于简化和/或减少逻辑设计的逻辑综合程序，方法和系统从逻辑模拟器接收输出，该逻辑模拟器使用符号值作为刺激，并在逻辑模拟器输出中包含符号值。依赖于符号值的节点之间的关系可用于合并节点或简化逻辑设计。可以在仿真结果和使用检测结果简化的网表中检测到依赖于符号值的振荡器，瞬态值，相同信号，依赖逻辑状态和鸡开关确定状态等行为。可以通过插入寄存器来简化网表，以代表以静态方式或初始瞬态之后基于符号值假设符号值或组合的节点。振荡节点可以用等效的振荡器电路代替，并且可以检测具有取决于鸡开关操作的值的节点，并用从鸡开关输入状态初始化的寄存器替换振荡节点。

34. 发明授权

US08418093B2 Method and system for design simplification through implication-based analysis 失效
标题翻译：通过暗示分析进行设计简化的方法和系统
公开(公告)号：US08418093B2
公开(公告)日：2013-04-09
申请号：US12467097
申请日：2009-05-15
申请人： Jason R. Baumgartner , Michael L. Case , Geert Janssen , Robert L. Kanzelman
发明人： Jason R. Baumgartner , Michael L. Case , Geert Janssen , Robert L. Kanzelman
IPC分类号： G06F9/45
CPC分类号： G06F17/505
摘要： Methods and systems are provided for reducing an original circuit design into a simplified circuit design by merging gates that may not be equivalent but can be demonstrated to preserve target assertability with respect to the original circuitry design. A composite netlist is created from the simplified netlist and the original netlist. The composite netlist includes a number of targets that imply the existence of a target in the simplified netlist and a corresponding target in the original netlist. The implications are verified and then validated to ensure the simplified circuit design is a suitable replacement for the original circuit design.
摘要翻译：提供了方法和系统，用于通过合并可能不相等但可被证明能够保持目标可靠性的原始电路设计的门来将原始电路设计减少为简化的电路设计。复合网表由简化网表和原网表创建。复合网表包括许多目标，这些目标意味着简化网表中存在目标，而在原始网表中存在相应的目标。这些含义经过验证，然后得到验证，以确保简化的电路设计是原始电路设计的合适替代品。

35. 发明申请

US20120290282A1 REACHABILITY ANALYSIS BY LOGICAL CIRCUIT SIMULATION FOR PROVIDING OUTPUT SETS CONTAINING SYMBOLIC VALUES 审中-公开
标题翻译：通过逻辑电路模拟提供包含符号值的输出集的可追溯性分析
公开(公告)号：US20120290282A1
公开(公告)日：2012-11-15
申请号：US13104478
申请日：2011-05-10
申请人： Michael L. Case , Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony
发明人： Michael L. Case , Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/504
摘要： A logic simulation program, method and system for obtaining a set of reachable states for a logic design that can be used to provide input to other algorithms that simplify the netlist describing the logic design or perform other types of processing, provides an efficient, compact behavior when simulating large designs. Rather than simulating using ternary input and state value representations that are restricted to true, false and unknown, the techniques of the present invention use input symbolic values that are retained in the set of reachable states retained as the output. Behaviors such as oscillators, transient values, identical signals, dependent logical states and chicken-switch determined states can be detected in the simulation results and the netlist simplified using the results of the detection.
摘要翻译：用于获得逻辑设计的一组可达状态的逻辑仿真程序，方法和系统可以用于向简化描述逻辑设计或执行其他类型处理的网表的其他算法提供输入，从而提供有效的紧凑行为当模拟大型设计时。不是使用限于真，假和未知的三进制输入和状态值表示来模拟，而是本发明的技术使用保留在作为输出保留的可达状态集合中的输入符号值。可以在仿真结果和使用检测结果简化的网表中检测诸如振荡器，瞬态值，相同信号，依赖逻辑状态和鸡开关确定状态等行为。

36. 发明授权

US08291359B2 Array concatenation in an integrated circuit design 有权
标题翻译：集成电路设计中的数组连接
公开(公告)号：US08291359B2
公开(公告)日：2012-10-16
申请号：US12775633
申请日：2010-05-07
申请人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
发明人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Mechanisms are provided in a design environment for array concatenation. The design environment comprises one mechanism to concatenate arrays with enable- and address-compatible ports, thereby reducing the number of arrays in a netlist. The design environment comprises another mechanism to migrate read ports from one array to another based upon compatible enable-, address-, and data-compatible write ports, thereby reducing the number of arrays in a netlist. The design environment comprises yet another mechanism to eliminate unnecessary arrays.
摘要翻译：在用于数组连接的设计环境中提供了机制。设计环境包括将阵列与启用和地址兼容的端口连接起来的一种机制，从而减少网表中的阵列数量。设计环境包括基于兼容的使能，地址和数据兼容的写入端口将读取端口从一个阵列迁移到另一个阵列的另一种机制，从而减少网表中的阵列数量。设计环境还包括消除不必要的阵列的另一种机制。

37. 发明授权

US08245166B2 Optimal correlated array abstraction 有权
标题翻译：最优相关数组抽象
公开(公告)号：US08245166B2
公开(公告)日：2012-08-14
申请号：US12871962
申请日：2010-08-31
申请人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
发明人： Jason R. Baumgartner , Michael L. Case , Robert L. Kanzelman , Hari Mony
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： Mechanisms are provided for refining an abstraction of a netlist for verification or synthesis of an integrated circuit design. The mechanisms receive an abstracted netlist corresponding to an original netlist of the integrated circuit design. The mechanisms determine elements already present in the abstracted netlist and refine the abstracted netlist by expanding the abstracted netlist to include additional elements that are correlated with the elements already present in the abstracted netlist to thereby generate a refined abstracted netlist. In addition, the mechanisms utilize the refined abstracted netlist to perform at least one of verification or synthesis of the integrated circuit design.
摘要翻译：提供了用于改进用于验证或综合集成电路设计的网表的抽象的机制。这些机制接收到与集成电路设计的原始网表相对应的抽象网表。这些机制确定已经存在于抽象网表中的元素，并通过扩展抽象网表来改进抽象网表，以包括与抽象网表中已经存在的元素相关联的附加元素，从而生成精简抽象网表。另外，这些机制利用精简的抽象网表来执行集成电路设计的验证或合成中的至少一个。

38. 发明授权

US08201117B2 Method for scalable derivation of an implication-based reachable state set overapproximation 失效
标题翻译：基于隐含的可达状态集过度近似的可伸缩推导方法
公开(公告)号：US08201117B2
公开(公告)日：2012-06-12
申请号：US12357907
申请日：2009-01-22
申请人： Jason R. Baumgartner , Michael L. Case , Geert Janssen , Hari Mony
发明人： Jason R. Baumgartner , Michael L. Case , Geert Janssen , Hari Mony
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/504
摘要： A method, system and computer program product for integrating implication-based analysis and equivalent gate analysis to maintain transitive reduction in an implication graph over a sequence of graph operations. One or more gates of a design are identified that are equivalent in all reachable states. Equivalent gates are assigned to an equivalence class when all gates within the equivalence class are equal. During the implication-based analysis the system determines when one or more implication paths are associated with the one or more equivalence classes, and an implication is generated at the implication path associated with the equivalence classes. A transitively reduced graph is received depicting the implications and equivalence classes of the design. When one or more operations are assigned to the transitively reduced graph, the graph is automatically adjusted to maintain transitive reduction.
摘要翻译：一种方法，系统和计算机程序产品，用于整合基于影响的分析和等效门分析，以维持图形操作序列中的含义图形的传递性减少。识别出在所有可达状态下等效的设计的一个或多个门。当等价类中的所有门相等时，将等效门分配给等价类。在基于暗示的分析中，系统确定何时一个或多个含义路径与一个或多个等价类相关联，并且在与等价类相关联的隐含路径上生成含义。接收到一个过渡缩减的图形，描述了设计的含义和等价类。当将一个或多个操作分配给转移缩减图时，会自动调整图表以维持传递减少。

39. 发明授权

US08181134B2 Techniques for performing conditional sequential equivalence checking of an integrated circuit logic design 有权
标题翻译：用于执行集成电路逻辑设计的条件顺序等价性检查的技术
公开(公告)号：US08181134B2
公开(公告)日：2012-05-15
申请号：US12580373
申请日：2009-10-16
申请人： Jason R. Baumgartner , Michael L. Case , Hari Mony , Jun Sawada
发明人： Jason R. Baumgartner , Michael L. Case , Hari Mony , Jun Sawada
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A technique for conditional sequential equivalence checking of logic designs embodied in netlists includes creating an equivalence-checking netlist over a first netlist and a second netlist. The conditional sequential equivalence checking includes conditions under which equivalences of the first and second netlists are checked. The technique derives a set of candidate conditional equivalence invariants for each correlated gate in a correlated gate pair set and attempts to prove that each candidate conditional equivalence invariant in the set of candidate conditional equivalence invariants is accurate. The candidate conditional equivalence invariants that cannot be proven accurate are removed from the set of candidate conditional equivalence invariants. The candidate conditional equivalence invariants that have been proven accurate are recorded as a set of conditional equivalence invariants. Finally, the conditional sequential equivalence checking of the equivalence-checking netlist is completed using the set of conditional equivalence invariants that are recorded.
摘要翻译：用于在网表中体现的逻辑设计的条件顺序等价检查的技术包括在第一网表和第二网表上创建等价检查网表。条件顺序等价检查包括检查第一和第二网表的等价物的条件。该技术为相关门对集合中的每个相关门导出一组候选条件等价不变量，并尝试证明候选条件等价不变量集合中的每个候选条件等价不变量是准确的。从候选条件等价不变量集合中删除不能被证明是准确的候选条件等价不变量。已被证明是准确的候选条件等价不变量被记录为一组条件等价不变量。最后，使用记录的条件等价不变量集来完成等价检查网表的条件序列等价性检查。

40. 发明授权

US08141048B2 Sequential encoding for relational analysis (SERA) of a software model 有权
标题翻译：软件模型的关系分析（SERA）的顺序编码
公开(公告)号：US08141048B2
公开(公告)日：2012-03-20
申请号：US11677652
申请日：2007-02-22
申请人： Jason R. Baumgartner , Ali S. El-Zein , Viresh Paruthi , Fadi A. Zaraket
发明人： Jason R. Baumgartner , Ali S. El-Zein , Viresh Paruthi , Fadi A. Zaraket
IPC分类号： G06F9/44 , G06F9/455
CPC分类号： G06F8/43
摘要： A method of verifying a software system includes receiving a description of a software system described utilizing a high-level modeling language, and responsive thereto, parsing the description and constructing an abstract syntax graph. The abstract syntax graph is transformed into a sequential logic representation of the software system. The sequential logic representation is formed by reference to a Hardware Description Language (HDL) library. Then, the sequential logic representation is transformed into a gate-level sequential logic representation. Following the transforming, the software system is verified based upon the gate-level sequential logic representation. Following verification, results of verification of the software system are output.
摘要翻译：验证软件系统的方法包括接收使用高级建模语言描述的软件系统的描述，并且响应于此，解析描述并构造抽象语法图。抽象语法图被转换成软件系统的顺序逻辑表示。通过参考硬件描述语言（HDL）库形成顺序逻辑表示。然后，顺序逻辑表示被转换成门级顺序逻辑表示。在变换之后，基于门级顺序逻辑表示验证软件系统。验证后，输出软件系统的验证结果。

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