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31. 发明授权

US09870315B2 Memory and processor hierarchy to improve power efficiency 有权
公开(公告)号：US09870315B2
公开(公告)日：2018-01-16
申请号：US15417676
申请日：2017-01-27
申请人： International Business Machines Corporation
发明人： Jan Van Lunteren , Heiner Giefers
IPC分类号： G06F12/02 , G06F1/32 , G06F9/30 , G06F9/26
CPC分类号： G06F12/02 , G06F1/3275 , G06F9/265 , G06F9/30007 , G06F9/3004 , G06F9/3824 , G06F9/3836 , G06F9/3889 , G06F15/7821 , G06F15/80 , Y02D10/13 , Y02D10/14
摘要： A computing memory includes an execution unit and an access processor coupled with a memory system, where the execution unit and the access processor are logically separated units. The execution unit is for processing operand data. The access processor is for providing operand data and configuration data to the execution unit. The access processor reads operand data from the memory system and sends the operand data to the execution unit. The execution unit executes the operand data according to the provided configuration data. The access processor includes information about execution times of operations of the execution unit for the provided configuration. The access processor reserves time-slots for writing execution unit results provided by the execution unit into selected locations in the memory system based on the information about the execution times, upon sending at least one of the operand data and the configuration data to the execution unit.

32. 发明申请

US20160275013A1 PROGRAMMABLE MEMORY MAPPING SCHEME WITH INTERLEAVE PROPERTIES 有权
标题翻译：具有间隔特性的可编程存储器映射方案
公开(公告)号：US20160275013A1
公开(公告)日：2016-09-22
申请号：US14661010
申请日：2015-03-18
申请人： International Business Machines Corporation
发明人： Jan Van Lunteren
IPC分类号： G06F12/06
CPC分类号： G06F12/0607 , G06F2212/1041 , G06F2212/657
摘要： Mapping an address for memory access in a memory system. The mapping may be performed in a combination comprising a memory bank identifier and a memory bank internal address indicative of an address within the memory bank. Data may be stored in a plurality of memory banks in an interleaved fashion. The address is partitioned into a first portion, a second portion, and a third portion. The memory bank identifier is determined as output of a look-up operation in a look-up matrix using as a first input the first portion and using, as at least two further inputs for the look-up operation in the look-up matrix, results of parity functions applied to the second and the third portion. The memory bank internal address is derived based on the second portion and third portion of the address for memory access address.
摘要翻译：在内存系统中映射内存访问的地址。该映射可以以包括存储器组标识符和指示存储器组内的地址的存储体内部地址的组合来执行。数据可以以交错方式存储在多个存储体中。该地址被划分为第一部分，第二部分和第三部分。存储体标识符被确定为使用第一部分作为第一输入的查找矩阵中的查找操作的输出，并且使用作为查找矩阵中的查找操作的至少两个另外的输入，奇偶校验功能的结果应用于第二和第三部分。基于存储器访问地址的地址的第二部分和第三部分导出存储体内部地址。

33. 发明公开

US20240338580A1 DECISION TREE TRAINING AND INFERENCE WITH MIXED PRECISION 审中-公开
公开(公告)号：US20240338580A1
公开(公告)日：2024-10-10
申请号：US18295307
申请日：2023-04-04
申请人： International Business Machines Corporation
发明人： Nikolaos Papandreou , Milos Stanisavljevic , Charalampos Pozidis , Jan Van Lunteren , Cedric Lichtenau
IPC分类号： G06N5/04 , G06N5/01
CPC分类号： G06N5/04 , G06N5/01
摘要： A method, system, and computer program product perform machine-learning inferences with a tree-based model. The tree-based model includes a decision tree that was trained on a first system, which is configured to perform computations with a first arithmetic precision. The inferences are performed with the tree-based model on a second system, which is configured to perform computations with an arithmetic precision that is lower than the first arithmetic precision. Performing the inference includes determining that an input feature value is equal to a threshold value of a corresponding node and, in response, using a majority voting to select a left or right path of the decision tree. The majority voting is based on historical statistical data that includes tree-path statistics.

34. 发明授权

US10996949B2 Address generation for high-performance vector processing 有权
公开(公告)号：US10996949B2
公开(公告)日：2021-05-04
申请号：US16408575
申请日：2019-05-10
申请人： International Business Machines Corporation
发明人： Jan Van Lunteren
IPC分类号： G06F9/30 , G06F12/06
摘要： A method for accessing a binary data vector in a memory unit comprising a plurality of memory banks in which the binary data vector is stored in portions includes receiving a start address of the binary data vector and a power-of-2-stride elements of the data vector and determining offsets, wherein the offsets are determined by applying a plurality of bit-level XOR functions to the start address resulting in a Z vector, using the Z vector for accessing a mapping table, and shifting mapping table access results according to a power-of-2-stride of the binary data vector. Additionally, the method includes determining a sequence of portions of the binary data vector in the n memory banks depending on a binary equivalent value of the Z vector, and accessing the binary data vector in the n memory banks of the memory unit in parallel.

35. 发明授权

US10776118B2 Index based memory access using single instruction multiple data unit 有权
公开(公告)号：US10776118B2
公开(公告)日：2020-09-15
申请号：US15261216
申请日：2016-09-09
申请人： International Business Machines Corporation
发明人： Heiner Giefers , Raphael Polig , Jan Van Lunteren
IPC分类号： G06F9/345 , G06F9/35 , G06F9/30 , G06F12/06 , G06F12/0802 , G11C5/02 , G06F12/0879
摘要： A computing system comprising a central processing unit (CPU), a memory processor and a memory device comprising a data array and an index array. The computing system is configured to store data lines comprising data elements in the data array and to store index lines comprising a plurality of memory indices in the index array. The memory indices indicate memory positions of data elements in the data array with respect to a start address of the data array. There is further provided a related computer implemented method and a related computer program product.

36. 发明申请

US20180074962A1 INDEX BASED MEMORY ACCESS 审中-公开
公开(公告)号：US20180074962A1
公开(公告)日：2018-03-15
申请号：US15261216
申请日：2016-09-09
申请人： International Business Machines Corporation
发明人： Heiner Giefers , Raphael Polig , Jan Van Lunteren
IPC分类号： G06F12/0853 , G11C7/10 , G06F17/30 , G11C5/02
摘要： A computing system comprising a central processing unit (CPU), a memory processor and a memory device comprising a data array and an index array. The computing system is configured to store data lines comprising data elements in the data array and to store index lines comprising a plurality of memory indices in the index array. The memory indices indicate memory positions of data elements in the data array with respect to a start address of the data array. There is further provided a related computer implemented method and a related computer program product.

37. 发明申请

US20170061304A1 THREE-DIMENSIONAL CHIP-BASED REGULAR EXPRESSION SCANNER 审中-公开
标题翻译：三维基于芯片的正则表达式扫描仪
公开(公告)号：US20170061304A1
公开(公告)日：2017-03-02
申请号：US14841825
申请日：2015-09-01
申请人： International Business Machines Corporation
发明人： Jan Van Lunteren , James Coghlan , Douglas J. Joseph
IPC分类号： G06N5/04
摘要： A method for performing enhanced pattern scanning includes the steps of: providing a three-dimensional memory structure including multiple physical memory elements; compiling multiple programmable finite state machines, each of the programmable finite state machines representing at least one deterministic finite automation data structure, the data structure being distributed over at least a subset of the physical memory elements; configuring a subset of the programmable finite state machines to operate in parallel on a same input data stream, while each of the subset of programmable finite state machines processes a different pattern subset; and providing a local result processor, the local result processor transferring at least a part of a match state from the deterministic finite automation data structures to corresponding registers within the local result processor, the part of the match state being manipulated being based on instructions embedded within the deterministic finite automation data structures.
摘要翻译：执行增强图案扫描的方法包括以下步骤：提供包括多个物理存储元件的三维存储器结构; 编译多个可编程有限状态机，每个可编程有限状态机代表至少一个确定性有限自动化数据结构，数据结构分布在物理存储器元件的至少一个子集上; 配置可编程有限状态机的子集以在相同的输入数据流上并行操作，而可编程有限状态机的子集中的每一个处理不同的模式子集; 并且提供本地结果处理器，所述本地结果处理器将至少一部分匹配状态从所述确定性有限自动化数据结构传送到所述本地结果处理器内的对应寄存器，所述被匹配状态的部分基于嵌入在所述本地结果处理器内的指令确定性有限自动化数据结构。

38. 发明申请

US20130238792A1 APPARATUS AND METHOD FOR ANALYZING A NETWORK 有权
标题翻译：用于分析网络的装置和方法
公开(公告)号：US20130238792A1
公开(公告)日：2013-09-12
申请号：US13868402
申请日：2013-04-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Andreas Kind , Jan Van Lunteren
IPC分类号： H04L12/26
CPC分类号： H04L43/08 , H04L43/026 , H04L63/1425
摘要： An apparatus and method for analyzing a network flow. The apparatus includes a parser for extracting flow identification information from the network flow, a flow metering unit, and a programmable controller and the parser, wherein the parser and flow metering unit are controlled in parallel by the programmable controller, wherein the programmable controller is implemented as state machine, and wherein the state machine includes a transition rule memory, a rule selector, and a state register, wherein the rule selector is configured for receiving an external input signal and an internal input signal from the state register and wherein the rule selector is configured for observing the internal and external input signal by means of the transition rule memory for transition rules and for changing the state of the state register and generation of an output signal having parsing or flow metering instructions when a transition rule applies.
摘要翻译：一种用于分析网络流的装置和方法。该装置包括用于从网络流提取流量识别信息的解析器，流量计量单元以及可编程控制器和解析器，其中解析器和流量计量单元由可编程控制器并行控制，其中可编程控制器被实现作为状态机，并且其中所述状态机包括转移规则存储器，规则选择器和状态寄存器，其中所述规则选择器被配置为从所述状态寄存器接收外部输入信号和内部输入信号，并且其中所述规则选择器被配置为通过用于转换规则的转换规则存储器来观察内部和外部输入信号，并且用于当转换规则适用时改变状态寄存器的状态和产生具有解析或流量计量指令的输出信号。

39. 发明申请

US20130144830A1 METHOD AND DEVICE FOR DISTRIBUTING PATTERNS TO SCANNING ENGINES FOR SCANNING PATTERNS IN A PACKET STREAM 审中-公开
标题翻译：用于分布图案的扫描模式的方法和装置，用于分组流中的扫描模式
公开(公告)号：US20130144830A1
公开(公告)日：2013-06-06
申请号：US13758203
申请日：2013-02-04
申请人： International Business Machines Corporation
发明人： Kubilay ATASU , Christoph HAGLEITNER , Jonathan Bruno ROHRER , Jan Van Lunteren
IPC分类号： G06N5/02
CPC分类号： G06N5/02 , H04L63/0227 , H04L63/1441 , H04L69/22
摘要： A method and a device for distributing patterns to scanning engines for scanning packets in a packet stream are provided. The method includes providing a plurality of scanning engines and patterns, calculating a respective distance metric for every pair of patterns, and providing a plurality of distribution functions. Further, the method includes calculating a respective sum of the calculated distance metrics for distributing the patterns for each of the distribution functions, and utilizing the sums for selecting a distribution function of the D distribution functions for distributing the patterns to the M scanning engines. A device for implementing the method is also provided.
摘要翻译：提供了一种用于向扫描引擎分发模式以扫描分组流中的分组的方法和设备。该方法包括提供多个扫描引擎和模式，为每对模式计算相应的距离度量，并提供多个分布函数。此外，该方法包括计算用于分配每个分布函数的模式的所计算的距离度量的相应和，并且使用用于选择用于将模式分发给M个扫描引擎的D分布函数的分布函数的和。还提供了一种用于实现该方法的设备。

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