专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20140209988A1 NONVOLATILE MEMORY BITCELL 审中-公开
标题翻译：非易失性存储器BITCELL
公开(公告)号：US20140209988A1
公开(公告)日：2014-07-31
申请号：US13756248
申请日：2013-01-31
申请人： Xin Lin , Hongning Yang , Zhihong Zhang , Jiang-Kai Zuo
发明人： Xin Lin , Hongning Yang , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/66 , H01L27/088
CPC分类号： H01L29/66825 , H01L27/11558 , H01L29/7881
摘要： A multiple time programmable nonvolatile memory device having a single polysilicon memory cell includes a select transistor and a bitcell transistor. The bitcell transistor has asymmetrically configured source, drain, and channel regions including asymmetrically configured source-body and drain-body junctions. Compared with the drain-body junction, the impurity concentration gradient of the source-body junction is more gradual, which may significantly improve program disturb immunity. The bitcell transistor gate may be connected to an electrode of a coupling capacitor, but may be otherwise floating or Ohmically isolated. The floating gate of the bitcell is protected by a dielectric layer for potentially improved data retention.
摘要翻译：具有单个多晶硅存储单元的多时间可编程非易失性存储器件包括选择晶体管和位单元晶体管。位单元晶体管具有不对称配置的源极，漏极和沟道区域，包括不对称配置的源极体和漏极 - 体部结。与漏 - 体结相比，源 - 体结的杂质浓度梯度更为平缓，可以显着提高程序的干扰免疫力。位单元晶体管栅极可以连接到耦合电容器的电极，但是可以以浮置或欧姆隔离的方式。位单元的浮动栅极由介电层保护，以便潜在地改善数据保持。

32. 发明申请

US20140203358A1 SEMICONDUCTOR DEVICE WITH ENHANCED 3D RESURF 有权
标题翻译：具有增强3D修复功能的半导体器件
公开(公告)号：US20140203358A1
公开(公告)日：2014-07-24
申请号：US13748076
申请日：2013-01-23
申请人： Hongning Yang , Xin Lin , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Xin Lin , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/66681 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/0847 , H01L29/1045 , H01L29/1095 , H01L29/7835
摘要： A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions. The drift region has a notched dopant profile in a second lateral dimension along an interface between the drift region and the drain region.
摘要翻译：一种器件包括半导体衬底，半导体衬底中的源极和漏极区域以及沿着第一横向尺寸彼此间隔开的半导体衬底中的漂移区域，并且在施加偏置电压之前电荷载体在操作期间漂移源极和漏极区域。漂移区域沿着漂移区域和漏极区域之间的界面在第二横向维度上具有缺口掺杂剂分布。

33. 发明申请

US20130234246A1 Semiconductor Device with Composite Drift Region 有权
标题翻译：具有复合漂移区域的半导体器件
公开(公告)号：US20130234246A1
公开(公告)日：2013-09-12
申请号：US13413440
申请日：2012-03-06
申请人： Hongning Yang , Jiang-Kai Zuo
发明人： Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L21/76
CPC分类号： H01L21/76224 , H01L29/0653 , H01L29/0847 , H01L29/66659 , H01L29/7835
摘要： A device includes a semiconductor substrate, a channel region in the semiconductor substrate having a first conductivity type, and a composite drift region in the semiconductor substrate, having a second conductivity type. The composite drift region includes a first drift region and a second drift region spaced from the channel region by the first drift region. The device further includes a drain region in the semiconductor substrate, spaced from the channel region by the composite drain region, and having the second conductivity type. The first drift region has a dopant concentration profile with a first concentration level where adjacent the channel region and a second concentration level where adjacent the second drift region, the first concentration level being higher than the second concentration level. In some embodiments, the first and second drift regions are stacked vertically, with the first drift region being shallower than the second drift region.
摘要翻译：一种器件包括半导体衬底，具有第一导电类型的半导体衬底中的沟道区域和具有第二导电类型的半导体衬底中的复合漂移区域。复合漂移区域包括第一漂移区域和第一漂移区域与沟道区域间隔开的第二漂移区域。该器件还包括在半导体衬底中的漏极区域，通过复合漏极区域与沟道区域间隔开并具有第二导电类型。第一漂移区域具有第一浓度水平的掺杂剂浓度分布，其中邻近通道区域的第一浓度水平和与第二漂移区域相邻的第二浓度水平，第一浓度水平高于第二浓度水平。在一些实施例中，第一漂移区域和第二漂移区域垂直堆叠，其中第一漂移区域比第二漂移区域浅。

34. 发明授权

US08513734B2 Switch mode converter employing dual gate MOS transistor 有权
标题翻译：采用双栅极MOS晶体管的开关模式转换器
公开(公告)号：US08513734B2
公开(公告)日：2013-08-20
申请号：US13069158
申请日：2011-03-22
申请人： Hongning Yang , Jiang-Kai Zuo
发明人： Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/76
CPC分类号： H01L27/0705 , H01L29/1045 , H01L29/1083 , H01L29/402 , H01L29/41775 , H01L29/66659 , H01L29/7831 , H01L29/7835
摘要： A disclosed power transistor, suitable for use in a switch mode converter that is operable with a switching frequency exceeding, for example, 5 MHz or more, includes a gate dielectric layer overlying an upper surface of a semiconductor substrate and first and second gate electrodes overlying the gate dielectric layer. The first gate electrode is laterally positioned overlying a first region of the substrate. The first substrate region has a first type of doping, which may be either n-type or p-type. A second gate electrode of the power transistor overlies the gate dielectric and is laterally positioned over a second region of the substrate. The second substrate region has a second doping type that is different than the first type. The transistor further includes a drift region located within the substrate in close proximity to an upper surface of the substrate and laterally positioned between the first and second substrate regions.
摘要翻译：适用于可以以超过例如5MHz或更大的开关频率工作的开关模式转换器的公开的功率晶体管包括覆盖在半导体衬底的上表面上的栅极电介质层和覆盖的半导体衬底的第一和第二栅电极栅介质层。第一栅电极横向定位成覆盖在衬底的第一区域上。第一衬底区域具有第一类型的掺杂，其可以是n型或p型。功率晶体管的第二栅电极覆盖栅极电介质，并且横向地位于衬底的第二区域上方。第二衬底区域具有与第一类型不同的第二掺杂类型。晶体管还包括位于衬底内的漂移区域，该漂移区域紧邻衬底的上表面并横向地位于第一和第二衬底区域之间。

35. 发明授权

US08247869B2 LDMOS transistors with a split gate 有权
标题翻译： LDMOS晶体管与分闸
公开(公告)号：US08247869B2
公开(公告)日：2012-08-21
申请号：US12767536
申请日：2010-04-26
申请人： Hongning Yang , Jiang-Kai Zuo
发明人： Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/0692 , H01L29/0878 , H01L29/1083 , H01L29/402 , H01L29/42376 , H01L29/4238 , H01L29/456 , H01L29/66659 , H01L29/7835
摘要： A transistor including a source region, drain region, channel region, drift region, isolation region, a first gate structure over the channel region, and a second gate structure over the isolation region is provided. The drift region includes a first portion located under the isolation region and a second portion located laterally adjacent to the isolation region. The first gate structure is separated by a first separation space from the second gate structure. The first separation space is located over a portion of the second portion of the drift region and a portion of the isolation region.
摘要翻译：提供了一种晶体管，其包括源极区，漏极区，沟道区，漂移区，隔离区，沟道区上的第一栅极结构以及隔离区上的第二栅极结构。漂移区域包括位于隔离区下方的第一部分和位于横向邻近隔离区域的第二部分。第一栅极结构由第一分隔空间与第二栅极结构隔开。第一分离空间位于漂移区的第二部分的一部分和隔离区的一部分之上。

36. 发明申请

US20120098095A1 BIPOLAR TRANSISTOR WITH IMPROVED STABILITY 有权
标题翻译：双极晶体管具有改进的稳定性
公开(公告)号：US20120098095A1
公开(公告)日：2012-04-26
申请号：US12908586
申请日：2010-10-20
申请人： Xin Lin , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
发明人： Xin Lin , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/73 , H01L21/8222
CPC分类号： H01L29/6625 , H01L21/82285 , H01L27/0826 , H01L29/735
摘要： Instability and drift sometimes observed in bipolar transistors, having a portion of the base extending to the transistor surface between the emitter and base contact, can be reduced or eliminated by providing a further doped region of the same conductivity type as the emitter at the transistor surface between the emitter and the base contact. The further region is desirably more heavily doped than the base region at the surface and less heavily doped than the adjacent emitter. In another embodiment, a still or yet further region of the same conductivity type as the emitter is provided either between the further region and the emitter or laterally within the emitter. The still or yet further region is desirably more heavily doped than the further region. Such further regions shield the near surface base region from trapped charge that may be present in dielectric layers or interfaces overlying the transistor surface.
摘要翻译：通过提供与晶体管表面上的发射极相同的导电类型的另外的掺杂区域，可以减少或消除具有延伸到发射极和基极接触之间的晶体管表面的基极的一部分的双极晶体管中的不稳定性和漂移在发射极和基极之间。另外的区域期望比表面上的基极区域重掺杂，并且比相邻的发射极更重掺杂。在另一个实施例中，与发射器相同的导电类型的仍然还是另外的区域被提供在另外的区域和发射极之间或者在发射极内侧。仍然还是进一步的区域期望比其他区域更重掺杂。这样的另外的区域屏蔽近表面碱基区域可能存在于覆盖晶体管表面的电介质层或界面中的俘获电荷。

37. 发明申请

US20110147893A1 BIPOLAR TRANSISTORS WITH HUMP REGIONS 有权
标题翻译：带红色区域的双极晶体管
公开(公告)号：US20110147893A1
公开(公告)日：2011-06-23
申请号：US13041531
申请日：2011-03-07
申请人： Xin Lin , Bernhard H. Grote , Hongning Yang , Jiang-Kai Zuo
发明人： Xin Lin , Bernhard H. Grote , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/70
CPC分类号： H01L29/7322 , H01L21/8222 , H01L21/8249 , H01L29/0821 , H01L29/1004 , H01L29/66272
摘要： By providing a novel bipolar device design implementation, a standard CMOS process can be used unchanged to fabricate useful bipolar transistors and other bipolar devices having adjustable properties by partially blocking the P or N well doping used for the transistor base. This provides a hump-shaped base region with an adjustable base width, thereby achieving, for example, higher gain than can be obtained with the unmodified CMOS process alone. By further partially blocking the source/drain doping step used to form the emitter of the bipolar transistor, the emitter shape and effective base width can be further varied to provide additional control over the bipolar device properties. The embodiments thus include prescribed modifications to the masks associated with the bipolar device that are configured to obtain desired device properties. The CMOS process steps and flow are otherwise unaltered and no additional process steps are required.
摘要翻译：通过提供一种新颖的双极器件设计实现，标准CMOS工艺可以不变地用于制造有用的双极晶体管和具有可调特性的其它双极器件，通过部分阻塞用于晶体管基极的P或N阱掺杂。这提供了具有可调底座宽度的驼峰形基部区域，从而实现例如比仅用未修改的CMOS工艺可获得的增益更高的增益。通过进一步部分地阻挡用于形成双极晶体管的发射极的源极/漏极掺杂步骤，可以进一步改变发射极形状和有效基极宽度，以提供对双极器件性质的附加控制。因此，这些实施例包括对被配置为获得期望的器件特性的与双极器件相关联的掩模的规定修改。 CMOS工艺步骤和流程否则不变，不需要额外的工艺步骤。

38. 发明授权

US07649234B2 Semiconductor devices 有权
标题翻译：半导体器件
公开(公告)号：US07649234B2
公开(公告)日：2010-01-19
申请号：US12129861
申请日：2008-05-30
申请人： Hongning Yang , Jiang-Kai Zuo
发明人： Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L21/336
CPC分类号： H01L29/7835 , H01L21/26586 , H01L21/823807 , H01L21/823892 , H01L29/1045 , H01L29/1083 , H01L29/66659
摘要： An embodiment of a semiconductor device includes a gate electrode overlying a substrate and a lightly doped epitaxial layer formed on the substrate. A high energy implant region forms a well in a source side of the lightly doped epitaxial layer. A self-aligned halo implant region is formed on a source side of the device and within the high energy well implant. An implant region on a drain side of the lightly doped epitaxial layer forms a gate overlapped LDD (GOLD). A doped region within the halo implant region forms a source. A doped region within the gate overlapped LDD (GOLD) forms a drain.
摘要翻译：半导体器件的实施例包括覆盖衬底的栅电极和形成在衬底上的轻掺杂外延层。高能注入区域在轻掺杂外延层的源极侧形成阱。自对准的晕圈植入区域形成在器件的源极侧和高能阱植入体内。在轻掺杂外延层的漏极侧的注入区域形成栅极重叠LDD（GOLD）。卤素注入区域内的掺杂区域形成源。栅极重叠LDD（GOLD）内的掺杂区域形成漏极。

39. 发明申请

US20090315145A1 ADJUSTABLE BIPOLAR TRANSISTORS FORMED USING A CMOS PROCESS 有权
标题翻译：使用CMOS工艺形成的可调节双极晶体管
公开(公告)号：US20090315145A1
公开(公告)日：2009-12-24
申请号：US12142115
申请日：2008-06-19
申请人： Xin Lin , Bernhard H. Grote , Hongning Yang , Jiang-Kai Zuo
发明人： Xin Lin , Bernhard H. Grote , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L21/331 , H01L29/73
CPC分类号： H01L29/7322 , H01L21/8222 , H01L21/8249 , H01L29/0821 , H01L29/1004 , H01L29/66272
摘要： By providing a novel bipolar device design implementation, a standard CMOS process (105-109) can be used unchanged to fabricate useful bipolar transistors (80) and other bipolar devices having adjustable properties by partially blocking the P or N well doping (25) used for the transistor base (581). This provides a hump-shaped base (583, 584) region with an adjustable base width (79), thereby achieving, for example, higher gain than can be obtained with the unmodified CMOS process (101-104) alone. By further partially blocking the source/drain doping step (107) used to form the emitter (74) of the bipolar transistor (80), the emitter shape and effective base width (79) can be further varied to provide additional control over the bipolar device (80) properties. The embodiments thus include prescribed modifications to the masks (57, 62, 72, 46) associated with the bipolar device (80) that are configured to obtain desired device properties. The CMOS process steps (105-109) and flow are otherwise unaltered and no additional process steps are required.
摘要翻译：通过提供一种新颖的双极器件设计实现，标准CMOS工艺（105-109）可以不变地用于制造有用的双极晶体管（80）和其他具有可调整特性的双极器件，通过部分阻塞使用的P或N阱掺杂（25）用于晶体管基极（581）。这提供了具有可调底座宽度（79）的驼峰形基部（583,584）区域，从而实现例如比仅用未修改的CMOS工艺（101-104）可获得的增益更高的增益。通过进一步部分地阻挡用于形成双极晶体管（80）的发射极（74）的源/漏掺杂步骤（107），可以进一步改变发射极形状和有效基极宽度（79），以提供对双极晶体管设备（80）属性。因此，这些实施例包括与被配置为获得期望的器件特性的与双极器件（80）相关联的掩模（57,62,72,46）的规定修改。 CMOS工艺步骤（105-109）和流程否则不变，并且不需要额外的工艺步骤。

40. 发明授权

US07411270B2 Composite capacitor and method for forming the same 有权
标题翻译：复合电容器及其形成方法
公开(公告)号：US07411270B2
公开(公告)日：2008-08-12
申请号：US11397493
申请日：2006-04-03
申请人： Won Gi Min , Geno L. Fallico , Amanda M. Kroll , Hongning Yang , Jiang-Kai Zuo
发明人： Won Gi Min , Geno L. Fallico , Amanda M. Kroll , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L27/04
CPC分类号： H01G4/33 , H01G4/236 , H01L23/5223 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： An electronic assembly (98) includes a substrate (20), a capacitor having first and second conductors (38,54) formed over the substrate, a first set of conductive members (76) formed over the substrate and being electrically connected to the first conductor of the capacitor, and a second set of conductive members (78) formed over the substrate and being electrically connected to the second conductor of the capacitor.
摘要翻译：电子组件（98）包括衬底（20），具有形成在衬底上的第一和第二导体（38,54）的电容器，形成在衬底上并且电连接到第一衬底的第一组导电构件（76）电容器的导体，以及形成在衬底上并且电连接到电容器的第二导体的第二组导电构件（78）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式