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31. 发明授权

US08535753B2 Methods of forming carbon nanotubes 有权
标题翻译：形成碳纳米管的方法
公开(公告)号：US08535753B2
公开(公告)日：2013-09-17
申请号：US12625896
申请日：2009-11-25
申请人： Xianfeng Wang , Hong-Sik Yoon , In-Seok Yeo
发明人： Xianfeng Wang , Hong-Sik Yoon , In-Seok Yeo
IPC分类号： B82Y40/00
CPC分类号： C23C16/0281 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B32/162 , C23C16/26 , H01L51/0002 , H01L51/0048
摘要： Methods of forming carbon nanotubes include forming a catalytic metal layer on a sidewall of an electrically conductive region, such as a metal or metal nitride pattern. A plurality of carbon nanotubes are grown from the catalytic metal layer. These carbon nanotubes can be grown from a sidewall of the catalytic metal layer. The plurality of carbon nanotubes are then exposed to an organic solvent. This step of exposing the carbon nanotubes to the organic solvent may be preceded by a step of applying centrifugal forces to the plurality of carbon nanotubes. Alternatively, the exposing step may include applying a centrifugal force to the plurality of carbon nanotubes while simultaneously exposing the plurality of carbon nanotubes to an organic solvent.
摘要翻译：形成碳纳米管的方法包括在诸如金属或金属氮化物图案的导电区域的侧壁上形成催化金属层。从催化金属层生长多个碳纳米管。这些碳纳米管可以从催化金属层的侧壁生长。然后将多个碳纳米管暴露于有机溶剂。之前将碳纳米管暴露于有机溶剂的步骤之前可以将离心力施加到多个碳纳米管。或者，曝光步骤可以包括向多个碳纳米管施加离心力，同时将多个碳纳米管暴露于有机溶剂。

32. 发明授权

US08405137B2 Single transistor floating-body DRAM devices having vertical channel transistor structures 失效
标题翻译：具有垂直沟道晶体管结构的单晶体管浮体DRAM器件
公开(公告)号：US08405137B2
公开(公告)日：2013-03-26
申请号：US13301254
申请日：2011-11-21
申请人： Zong-Liang Huo , Seung-Jae Baik , In-Seok Yeo , Hong-Sik Yoon , Shi-Eun Kim
发明人： Zong-Liang Huo , Seung-Jae Baik , In-Seok Yeo , Hong-Sik Yoon , Shi-Eun Kim
IPC分类号： H01L29/788
CPC分类号： H01L27/108 , H01L21/84 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： Single transistor floating-body DRAM devices have a vertical channel transistor structure. The DRAM devices include a substrate, and first and second floating bodies disposed on the substrate and isolated from each other. A source region and a drain region are disposed under and above each of the first and second floating bodies. A gate electrode is disposed between the first and second floating bodies. Methods of fabricating the single transistor floating-body DRAM devices are also provided.
摘要翻译：单晶体体浮体DRAM器件具有垂直沟道晶体管结构。 DRAM器件包括衬底，以及设置在衬底上并彼此隔离的第一和第二浮体。源极区域和漏极区域设置在第一和第二浮体的每一个之下和之上。栅电极设置在第一和第二浮体之间。还提供了制造单晶体管浮体DRAM器件的方法。

33. 发明授权

US08358527B2 Multi-level nonvolatile memory devices using variable resistive elements 有权
标题翻译：使用可变电阻元件的多级非易失性存储器件
公开(公告)号：US08358527B2
公开(公告)日：2013-01-22
申请号：US12656754
申请日：2010-02-16
申请人： In-Gyu Baek , Hyun-Jun Sim , Hong-Sik Yoon , Jin-Shi Zhao , Min-Young Park
发明人： In-Gyu Baek , Hyun-Jun Sim , Hong-Sik Yoon , Jin-Shi Zhao , Min-Young Park
IPC分类号： G11C11/00 , H01L47/00
CPC分类号： G11C13/0007 , G11C11/5685 , G11C13/0069 , G11C2013/0073 , G11C2211/5641 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/72
摘要： Multi-level nonvolatile memory devices using variable resistive elements, the multi-level nonvolatile memory devices including a word line, a bit line, and a multi-level memory cell coupled between the word line and the bit line, the multi-level memory cell having first resistance level and a second resistance level higher than the first resistance level when the first and second write biases having the same polarity are applied thereto, and a third resistance level and a fourth resistance level ranging between the first and second resistance levels, when third and fourth write biases having different polarities from each other are applied thereto.
摘要翻译：使用可变电阻元件的多级非易失性存储器件，多级非易失性存储器件包括字线，位线和耦合在字线和位线之间的多电平存储器单元，多电平存储器单元当施加具有相同极性的第一和第二写入偏置时，具有高于第一电阻电平的第一电阻电平和第二电阻电平，以及在第一和第二电阻电平之间范围内的第三电阻电平和第四电阻电平，当施加具有彼此不同极性的第三和第四写入偏置。

34. 发明授权

US07795659B2 DRAM device and method of manufacturing the same 失效
标题翻译： DRAM装置及其制造方法
公开(公告)号：US07795659B2
公开(公告)日：2010-09-14
申请号：US12149406
申请日：2008-05-01
申请人： Hong-Sik Yoon , In-Seok Yeo , Seung-Jae Baik , Zong-Liang Huo , Shi-Eun Kim
发明人： Hong-Sik Yoon , In-Seok Yeo , Seung-Jae Baik , Zong-Liang Huo , Shi-Eun Kim
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10873 , H01L27/10829
摘要： In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation layer and a gate electrode are formed on a sidewall of the MTJ structure. A word line is connected with the MTJ structure, and a bit line is connected with one of top and bottom surfaces of the MTJ structure. A capacitor is connected with one of top and bottom surfaces of the MTJ structure that is not connected with the bit line. Current leakage in the DRAM device is reduced and a unit cells may be vertically stacked on the substrate, so a smaller surface area of the substrate is required for the DRAM device.
摘要翻译：在DRAM器件及其制造方法中，提供了多隧道结（MTJ）结构，其包括彼此交替堆叠的导电图案和非导电图案。非导电图案具有比导电图案的带隙大的带隙。在MTJ结构的侧壁上形成栅极绝缘层和栅电极。字线与MTJ结构连接，位线与MTJ结构的顶面和底面之一连接。电容器与MTJ结构的一个顶表面和底表面连接，不与位线连接。 DRAM器件中的电流泄漏减少，并且单元电池可以垂直地堆叠在衬底上，因此DRAM器件需要较小的衬底表面积。

35. 发明申请

US20100136226A1 Methods of Forming Carbon Nanotubes 有权
标题翻译：形成碳纳米管的方法
公开(公告)号：US20100136226A1
公开(公告)日：2010-06-03
申请号：US12625896
申请日：2009-11-25
申请人： Xiaofeng Wang , Hong-Sik Yoon , In-Seok Yeo
发明人： Xiaofeng Wang , Hong-Sik Yoon , In-Seok Yeo
IPC分类号： B05D5/12
CPC分类号： C23C16/0281 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B32/162 , C23C16/26 , H01L51/0002 , H01L51/0048
摘要： Methods of forming carbon nanotubes include forming a catalytic metal layer on a sidewall of an electrically conductive region, such as a metal or metal nitride pattern. A plurality of carbon nanotubes are grown from the catalytic metal layer. These carbon nanotubes can be grown from a sidewall of the catalytic metal layer. The plurality of carbon nanotubes are then exposed to an organic solvent. This step of exposing the carbon nanotubes to the organic solvent may be preceded by a step of applying centrifugal forces to the plurality of carbon nanotubes. Alternatively, the exposing step may include applying a centrifugal force to the plurality of carbon nanotubes while simultaneously exposing the plurality of carbon nanotubes to an organic solvent.
摘要翻译：形成碳纳米管的方法包括在诸如金属或金属氮化物图案的导电区域的侧壁上形成催化金属层。从催化金属层生长多个碳纳米管。这些碳纳米管可以从催化金属层的侧壁生长。然后将多个碳纳米管暴露于有机溶剂。之前将碳纳米管暴露于有机溶剂的步骤之前可以将离心力施加到多个碳纳米管。或者，曝光步骤可以包括向多个碳纳米管施加离心力，同时将多个碳纳米管暴露于有机溶剂。

36. 发明申请

US20080138991A1 METHOD OF MANUFACTURING A TRANSISTOR 失效
标题翻译：制造晶体管的方法
公开(公告)号：US20080138991A1
公开(公告)日：2008-06-12
申请号：US11932994
申请日：2007-10-31
申请人： Hong Cho , Seung-Pil Chung , Hong-Sik Yoon , Kyung-Rae Byun
发明人： Hong Cho , Seung-Pil Chung , Hong-Sik Yoon , Kyung-Rae Byun
IPC分类号： H01L21/308 , H01L21/465
CPC分类号： H01L51/057 , B82Y10/00 , H01L51/0048 , Y10T29/49105
摘要： A multilayer insulating structure including a first stop layer, a first insulating layer and a second stop layer is formed on the first conductive structure. A second conductive structure and a second insulating layer are formed on the first conductive structure. The second insulating layer and the second conductive structure are etched to form a first hole and a second hole having a first radius. A spacer is formed on sidewalls of the first and second holes. The second stop layer and the first insulating layer are etched using the spacer as an etch mask to form a third hole having a second radius smaller than the first radius. A sacrificial filler is formed on the first stop layer to fill the third hole. After removing the spacer, the sacrificial filler is removed. The first stop layer is etched. A carbon nano-tube is grown from the first conductive structure.
摘要翻译：在第一导电结构上形成包括第一阻挡层，第一绝缘层和第二阻挡层的多层绝缘结构。在第一导电结构上形成第二导电结构和第二绝缘层。蚀刻第二绝缘层和第二导电结构以形成具有第一半径的第一孔和第二孔。间隔件形成在第一孔和第二孔的侧壁上。使用间隔物作为蚀刻掩模蚀刻第二阻挡层和第一绝缘层，以形成具有小于第一半径的第二半径的第三孔。在第一停止层上形成牺牲填料以填充第三孔。去除间隔物后，去除牺牲填料。第一个停止层被蚀刻。从第一导电结构生长碳纳米管。

37. 发明申请

US20080128802A1 SINGLE TRANSISTOR FLOATING BODY DRAM CELL HAVING RECESS CHANNEL TRANSISTOR STRUCTURE 审中-公开
标题翻译：具有输入通道晶体管结构的单晶片浮动体
公开(公告)号：US20080128802A1
公开(公告)日：2008-06-05
申请号：US12013547
申请日：2008-01-14
申请人： Zong-Liang Huo , Seung-Jae Baik , In-Seok Yeo , Hong-Sik Yoon , Shi-Eun Kim
发明人： Zong-Liang Huo , Seung-Jae Baik , In-Seok Yeo , Hong-Sik Yoon , Shi-Eun Kim
IPC分类号： H01L29/786
CPC分类号： H01L27/108 , H01L27/10802 , H01L29/7841 , H01L29/78648
摘要： Single transistor floating body dynamic random access memory (DRAM) cells include a semiconductor substrate and a barrier layer on the semiconductor substrate and a recess channel transistor on the barrier layer. The recess channel transistor includes a source region of a first conductivity type, a drain region of the first conductivity type spaced apart from the source region and a floating body of a second conductivity type between the barrier layer and the source region and the drain region. The floating body includes a recess region between the source region and the drain region.
摘要翻译：单晶体管浮体动态随机存取存储器（DRAM）单元包括半导体衬底和半导体衬底上的阻挡层以及阻挡层上的凹槽通道晶体管。凹槽沟道晶体管包括第一导电类型的源极区域，与源极区域隔开的第一导电类型的漏极区域和在阻挡层与源极区域和漏极区域之间的第二导电类型的浮动体。浮体包括在源极区域和漏极区域之间的凹陷区域。

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