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31. 发明申请

US20070286290A1 Mosquito reduction filter in standard definition and high definition digital decoders 有权
标题翻译：标准清晰度和高分辨率数字解码器中的减速滤波器
公开(公告)号：US20070286290A1
公开(公告)日：2007-12-13
申请号：US11452030
申请日：2006-06-13
申请人： Ho-Ming Leung , Suryanaryana M. Potharaju
发明人： Ho-Ming Leung , Suryanaryana M. Potharaju
IPC分类号： H04B1/66
CPC分类号： G06T5/20 , G06T5/002 , G06T2207/10016 , H04N19/86
摘要： A method for processing a compressed signal of digital video is disclosed. The method generally includes the steps of (A) generating a decompressed signal by decompressing the compressed signal of digital video, (B) generating a filtered signal by spatial filtering the decompressed signal, wherein the spatial filtering is arranged to reduce mosquito noise within the decompressed signal and (C) generating a video signal by adding synchronization information to the filtered signal, the synchronization information being suitable for synchronizing a video display to the filtered signal.
摘要翻译：公开了一种处理数字视频压缩信号的方法。该方法通常包括以下步骤：（A）通过解压缩数字视频的压缩信号来产生解压缩信号，（B）通过对解压缩信号进行空间滤波来产生经滤波的信号，其中空间滤波被设置为减少解压缩的消除噪声信号和（C）通过向经滤波的信号添加同步信息来生成视频信号，所述同步信息适于使视频显示同步到滤波信号。

32. 发明申请

US20070153013A1 Hybrid multiple bit-depth video processing architecture 有权
标题翻译：混合多位深度视频处理架构
公开(公告)号：US20070153013A1
公开(公告)日：2007-07-05
申请号：US11325291
申请日：2006-01-04
申请人： Aaron Wells , Hidetaka Magoshi , Ho-Ming Leung
发明人： Aaron Wells , Hidetaka Magoshi , Ho-Ming Leung
IPC分类号： G09G5/36
CPC分类号： H04N19/423 , H04N19/61
摘要： An apparatus including a processor and a memory. The processor may be configured to process pixel data comprising eight or more bits. For pixel data having bit-depths greater than eight bits, a number of most significant bits (MSBs) of a pixel are presented as a first byte and a number of least significant bits (LSBs) of the pixel are packed with LSBs from one or more other pixels into a second byte. The memory may be coupled to the processor and configured to store the first byte in response to a first pointer and the second byte in response to a second pointer. The first byte and the second byte are stored independently in the memory.
摘要翻译：一种包括处理器和存储器的装置。处理器可以被配置为处理包括八个或更多位的像素数据。对于具有大于8位的位深度的像素数据，像素的多个最高有效位（MSB）被呈现为第一字节，并且像素的最低有效位数（LSB）由LSB或更多其他像素进入第二个字节。存储器可以耦合到处理器并且被配置为响应于第一指针存储第一字节，并响应于第二指针存储第二字节。第一个字节和第二个字节独立存储在存储器中。

33. 发明申请

US20070040840A1 Method and/or apparatus for video data storage 失效
标题翻译：用于视频数据存储的方法和/或装置
公开(公告)号：US20070040840A1
公开(公告)日：2007-02-22
申请号：US11590516
申请日：2006-10-31
申请人： Elliot Linzer , Ho-Ming Leung
发明人： Elliot Linzer , Ho-Ming Leung
IPC分类号： G06T1/60
CPC分类号： G09G5/39 , G09G2360/122
摘要： An apparatus and method for storing image data comprising a first storage device and a second storage device. The first storage device may be configured to store at least one first pixel from a first field of a frame of the image at a first physical address in the first storage device. The second storage device may be configured to store a second pixel from a second field of the frame of the image at a second physical address in the second storage device. The first and second physical addresses may have the same relative position in an address space of the respective storage devices.
摘要翻译：一种用于存储包括第一存储装置和第二存储装置的图像数据的装置和方法。第一存储设备可以被配置为在第一存储设备中的第一物理地址处存储来自图像的帧的第一字段的至少一个第一像素。第二存储设备可以被配置为在第二存储设备中的第二物理地址处从图像的帧的第二字段存储第二像素。第一和第二物理地址可以在各个存储设备的地址空间中具有相同的相对位置。

34. 发明申请

US20070009181A1 Efficient and high speed 2D data transpose engine for SOC application 有权
标题翻译：高效，高速的2D数据转换引擎，适用于SOC应用
公开(公告)号：US20070009181A1
公开(公告)日：2007-01-11
申请号：US11176040
申请日：2005-07-07
申请人： Ho-Ming Leung , Gary Chang , Wern-Yan Koe
发明人： Ho-Ming Leung , Gary Chang , Wern-Yan Koe
IPC分类号： G06K9/32
CPC分类号： G06T3/606
摘要： An apparatus comprising a buffer circuit, a rotation circuit and a memory. The buffer may be configured to store original image data in one or more sub-matrices. The rotation circuit may be configured to (i) produce rotated data and (ii) store the rotated data in a transposed matrix. The memory may be configured to position the rotated data in the transposed matrix. The transposed matrix comprises final image data rotated by a predetermined angle from the original image data.
摘要翻译：一种包括缓冲电路，旋转电路和存储器的装置。缓冲器可以被配置为将原始图像数据存储在一个或多个子矩阵中。旋转电路可以被配置为（i）产生旋转的数据和（ii）将转动的数据存储在转置的矩阵中。存储器可以被配置为将旋转的数据定位在转置的矩阵中。转置矩阵包括从原始图像数据旋转预定角度的最终图像数据。

35. 发明申请

US20060209958A1 Method and/or apparatus for implementing global motion compensation in a video system 有权
标题翻译：用于在视频系统中实现全局运动补偿的方法和/或装置
公开(公告)号：US20060209958A1
公开(公告)日：2006-09-21
申请号：US11082639
申请日：2005-03-17
申请人： Kasturiranga Rangam , Elliot Sowadsky , Ho-Ming Leung
发明人： Kasturiranga Rangam , Elliot Sowadsky , Ho-Ming Leung
IPC分类号： H04N11/02 , H04N11/04 , H04N7/12 , H04B1/66
CPC分类号： H04N19/523 , H04N19/23 , H04N19/43 , H04N19/433 , H04N19/44 , H04N19/527 , H04N19/537 , H04N19/61
摘要： An apparatus comprising a video decoder, a video memory and a global motion circuit. The video decoder may be configured to generate a decoded video signal in response to a coded video signal. The video memory may be connected to the video decoder. The global motion circuit may be configured within the video decoder circuit. The global motion circuit may be configured to (i) receive one or more warp points and (ii) generate one or more warping addresses presented directly to the video memory.
摘要翻译：一种包括视频解码器，视频存储器和全局运动电路的装置。视频解码器可以被配置为响应于编码的视频信号产生解码的视频信号。视频存储器可以连接到视频解码器。全局运动电路可以配置在视频解码器电路内。全局运动电路可以被配置为（i）接收一个或多个翘曲点，并且（ii）生成直接呈现给视频存储器的一个或多个翘曲地址。

36. 发明授权

US06895488B2 DSP memory bank rotation 失效
标题翻译： DSP存储器组旋转
公开(公告)号：US06895488B2
公开(公告)日：2005-05-17
申请号：US10153090
申请日：2002-05-22
申请人： Ho-Ming Leung , Wern-Yan Koe , Fan Zhang , Kasturiranga N. Rangam , Venkatesh Balasubramanian
发明人： Ho-Ming Leung , Wern-Yan Koe , Fan Zhang , Kasturiranga N. Rangam , Venkatesh Balasubramanian
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0292
摘要： An apparatus comprising a memory, a plurality of modules, an address translation unit and a controller. The memory may be arranged as a plurality of memory banks. Each of the plurality of modules may be configured to generate one or more addresses for accessing a particular one of the plurality of memory banks. The address translation unit may be configured to modify the one or more addresses in response to a control signal. The controller may be configured to generate the control signal in response to a computer executable instruction.
摘要翻译：一种包括存储器，多个模块，地址转换单元和控制器的装置。存储器可以被布置为多个存储体。多个模块中的每一个可以被配置为生成用于访问多个存储体中的特定一个的一个或多个地址。地址转换单元可以被配置为响应于控制信号修改一个或多个地址。控制器可以被配置为响应于计算机可执行指令来生成控制信号。

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