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31. 发明授权

US08619487B2 Semiconductor memory device and method of controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US08619487B2
公开(公告)日：2013-12-31
申请号：US13356341
申请日：2012-01-23
申请人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
发明人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3268 , G06F1/3275 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C14/00 , G11C2207/2227 , G11C2211/4067 , H02M3/07 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.
摘要翻译：半导体器件包括具有多个存储单元的存储器芯，内部电压发生器和低功率入口电路。低功率入口电路接收提供给命令解码器的多个控制信号，并产生指示禁止刷新操作的低功耗模式的低功率信号。内部电压发生器包括检测器和至少一个升压电路。内部电压发生器通过内部电源线耦合到存储器核心，基于外部电压产生升压的内部电压，并通过内部电源线将升压的内部电压提供给存储器核心。内部电压发生器在向外部电压提供给半导体器件时停止向内部电源线提供升压的内部电压以响应于低功率信号。

32. 发明授权

US07688661B2 Semiconductor memory device, and method of controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US07688661B2
公开(公告)日：2010-03-30
申请号：US12234969
申请日：2008-09-22
申请人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
发明人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3268 , G06F1/3275 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C14/00 , G11C2207/2227 , G11C2211/4067 , H02M3/07 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.
摘要翻译：内部电压发生器激活时，产生内部电压供给内部电路。操作内部电压发生器消耗预定量的功率。响应来自外部的控制信号，入口电路使内部电压发生器失活。内部电压发生器未激活时，不产生内部电压，从而降低功耗。因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器记忆细胞。

33. 发明授权

US07495986B2 Semiconductor memory device, and method of controlling the same 有权
公开(公告)号：US07495986B2
公开(公告)日：2009-02-24
申请号：US11189858
申请日：2005-07-27
申请人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
发明人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3268 , G06F1/3275 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C14/00 , G11C2207/2227 , G11C2211/4067 , H02M3/07 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

34. 发明申请

US20060256639A1 Semiconductor memory device and memory system 有权
公开(公告)号：US20060256639A1
公开(公告)日：2006-11-16
申请号：US11488785
申请日：2006-07-19
申请人： Shinya Fujioka , Kotoku Sato
发明人： Shinya Fujioka , Kotoku Sato
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/1039 , G11C11/40603 , G11C11/40615
摘要： A command register holding a decoded result of information relating to an access request supplied from an outside and an address register are provided, and decode of the information relating to an access request from the outside in a processing circuit, namely, a chip control circuit and an address decoder, and an operation corresponding to the external access request in a memory cell array by an access control circuit are made executable independently in parallel, whereby access requests from the outside can be inputted in multiple, and a pipelined operation can be realized for decode and an operation corresponding to the external access request in the memory cell array, thus making it possible to speed up the access operation to a semiconductor memory device without causing any problem.

35. 发明授权

US07102949B2 Semiconductor memory device and memory system 有权
标题翻译：半导体存储器件和存储器系统
公开(公告)号：US07102949B2
公开(公告)日：2006-09-05
申请号：US11024737
申请日：2004-12-30
申请人： Shinya Fujioka , Kotoku Sato
发明人： Shinya Fujioka , Kotoku Sato
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/1039 , G11C11/40603 , G11C11/40615
摘要： A command register holding a decoded result of information relating to an access request supplied from an outside and an address register are provided, and decode of the information relating to an access request from the outside in a processing circuit, namely, a chip control circuit and an address decoder, and an operation corresponding to the external access request in a memory cell array by an access control circuit are made executable independently in parallel, whereby access requests from the outside can be inputted in multiple, and a pipelined operation can be realized for decode and an operation corresponding to the external access request in the memory cell array, thus making it possible to speed up the access operation to a semiconductor memory device without causing any problem.
摘要翻译：提供保持与从外部提供的访问请求相关的信息的解码结果和地址寄存器的命令寄存器，并且在处理电路即芯片控制电路中解码与来自外部的访问请求有关的信息，一个地址解码器和一个由访问控制电路对应于存储单元阵列中的外部访问请求的操作可以独立地并行执行，从而可以多次输入来自外部的访问请求，并且可以实现流水线操作解码和对应于存储单元阵列中的外部访问请求的操作，从而使得可以加速对半导体存储器件的访问操作而不引起任何问题。

36. 发明授权

US07057959B2 Semiconductor memory having mode register access in burst mode 有权
标题翻译：半导体存储器在突发模式下具有模式寄存器访问
公开(公告)号：US07057959B2
公开(公告)日：2006-06-06
申请号：US11001619
申请日：2004-12-02
申请人： Shinya Fujioka , Shinichi Yamada , Kotoku Sato , Jun Ohno
发明人： Shinya Fujioka , Shinichi Yamada , Kotoku Sato , Jun Ohno
IPC分类号： G11C7/22 , G11C5/14
CPC分类号： G11C7/1018 , G11C7/22 , G11C2207/2227
摘要： A method for controlling a semiconductor memory in which a mode register can be set in a burst mode. To set an operation mode in the burst mode, the semiconductor memory is changed first from the burst mode, through a power-down mode, to a standby mode of non-burst mode. Then the semiconductor memory is changed to a mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.
摘要翻译：一种用于控制其中可以以突发模式设置模式寄存器的半导体存储器的方法。为了在突发模式下设置操作模式，首先将半导体存储器从突发模式通过掉电模式改变为非突发模式的待机模式。然后，当以与非突发模式中使用的相同的预定顺序输入命令时，半导体存储器被改变为模式寄存器设置模式以设置模式寄存器。

37. 发明申请

US20050262369A1 Semiconductor memory device, and method of controlling the same 有权
公开(公告)号：US20050262369A1
公开(公告)日：2005-11-24
申请号：US11189858
申请日：2005-07-27
申请人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
发明人： Shinya Fujioka , Tomohiro Kawakubo , Koichi Nishimura , Kotoku Sato
IPC分类号： G06F1/26 , G06F1/32 , G11C5/14 , G11C11/406 , H02M3/07
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3268 , G06F1/3275 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C14/00 , G11C2207/2227 , G11C2211/4067 , H02M3/07 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

38. 发明授权

US07848176B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07848176B2
公开(公告)日：2010-12-07
申请号：US12428828
申请日：2009-04-23
申请人： Hitoshi Ikeda , Shinya Fujioka , Takahiro Sawamura
发明人： Hitoshi Ikeda , Shinya Fujioka , Takahiro Sawamura
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C7/1018 , G11C7/1042 , G11C11/4076 , G11C11/408 , G11C11/4085
摘要： A word control circuit activates word lines corresponding to a start row address and a next row address overlappingly in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word line becomes unnecessary. Memory cells connected to different word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and a control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.
摘要翻译：字控制电路在连续模式下重叠地起动对应于起始行地址和下一行地址的字线。因此，即使在开始地址指示连接到字线的结束存储单元的情况下，也不需要字线的切换操作。可以按顺序的方式访问连接到不同字线的存储单元。也就是说，访问半导体存储器件的控制器可以访问存储器而没有数据中断。这可以防止数据传输速率降低。此外，不需要形成信号和控制电路，用于通知控制器正在切换字线的事实，使得可以简化控制器的半导体存储器件和控制电路的结构。这导致系统成本的降低。

39. 发明申请

US20060256642A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060256642A1
公开(公告)日：2006-11-16
申请号：US11488024
申请日：2006-07-18
申请人： Hitoshi Ikeda , Shinya Fujioka , Takahiro Sawamura
发明人： Hitoshi Ikeda , Shinya Fujioka , Takahiro Sawamura
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C7/1018 , G11C7/1042 , G11C11/4076 , G11C11/408 , G11C11/4085
摘要： A word control circuit activates word lines corresponding to a start row address and a next row address overlapping in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.
摘要翻译：字控制电路激活对应于连续模式重叠的起始行地址和下一行地址的字线。因此，即使在开始地址指示连接到字线的结束存储单元的情况下，也可以顺序地访问字线的切换操作。也就是说，访问半导体存储器件的控制器可以访问存储器而没有数据中断。这可以防止数据传输速率降低。此外，不需要形成用于通知控制器正在切换字线的事实的信号和控制电路，使得可以简化控制器的半导体存储器件和控制电路的结构。这导致系统成本的降低。

40. 发明授权

US07102960B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07102960B2
公开(公告)日：2006-09-05
申请号：US11114087
申请日：2005-04-26
申请人： Hitoshi Ikeda , Shinya Fujioka , Takahiro Sawamura
发明人： Hitoshi Ikeda , Shinya Fujioka , Takahiro Sawamura
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C7/1018 , G11C7/1042 , G11C11/4076 , G11C11/408 , G11C11/4085
摘要： A word control circuit activates word lines corresponding to a start row address and a next row address overlappingly in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word line becomes unnecessary. Memory cells connected to different word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and a control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.
摘要翻译：字控制电路在连续模式下重叠地起动对应于起始行地址和下一行地址的字线。因此，即使在开始地址指示连接到字线的结束存储单元的情况下，也不需要字线的切换操作。可以按顺序的方式访问连接到不同字线的存储单元。也就是说，访问半导体存储器件的控制器可以访问存储器而没有数据中断。这可以防止数据传输速率降低。此外，不需要形成信号和控制电路，用于通知控制器正在切换字线的事实，使得可以简化控制器的半导体存储器件和控制电路的结构。这导致系统成本的降低。

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