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31. 发明授权

US06751116B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06751116B2
公开(公告)日：2004-06-15
申请号：US10233486
申请日：2002-09-04
申请人： Naoki Kuroda , Masashi Agata
发明人： Naoki Kuroda , Masashi Agata
IPC分类号： G11C1124
CPC分类号： G11C7/22 , G11C7/1072 , G11C2207/2281
摘要： A port A of the path including a first transistor of a memory cell to be accessed, a first bit line pair, a first column selection switch and a data line pair interleaves with a port B of the path including a second transistor of the memory cell to be accessed, a second bit line pair, a second column selection switch and the data line pair in two cycles of a clock. A read amplifier amplifies data transferred from a bit line pair to the data line pair and outputs the resultant data to an input/output buffer in one cycle of the clock. The input/output buffer outputs the data received from the read amplifier to the outside in one cycle of the clock.
摘要翻译：包括要访问的存储单元的第一晶体管，第一位线对，第一列选择开关和数据线对的路径的端口A与包括存储器单元的第二晶体管的路径的端口B交错要被访问的第二位线对，第二列选择开关和数据线对在时钟的两个周期中。读取放大器将从位线对传送的数据放大到数据线对，并在时钟的一个周期内将结果数据输出到输入/输出缓冲器。输入/输出缓冲器在时钟的一个周期内将从读取放大器接收到的数据输出到外部。

32. 发明授权

US06229758B1 Semiconductor memory device that can read out data faster than writing it 有权
标题翻译：半导体存储器件可以比写入数据更快地读出数据
公开(公告)号：US06229758B1
公开(公告)日：2001-05-08
申请号：US09662149
申请日：2000-09-14
申请人： Masashi Agata
发明人： Masashi Agata
IPC分类号： G11C800
CPC分类号： G11C7/1072
摘要： The semiconductor memory device of the invention includes: a data storage section for storing data thereon; a data write section for writing data on the storage section; and a data read section for reading out the data stored on the storage section. The read section generates a read clock signal responsive to an external clock signal, and the write section generates a write clock signal responsive to the external clock signal. And one cycle of the read clock signal is set shorter than one cycle of the write clock signal.
摘要翻译：本发明的半导体存储器件包括：数据存储部分，用于在其上存储数据; 用于在存储部分上写入数据的数据写入部分; 以及用于读出存储在存储部分上的数据的数据读取部分。读取部分响应于外部时钟信号产生读取时钟信号，并且写入部分响应于外部时钟信号产生写入时钟信号。读时钟信号的一个周期被设置为短于写时钟信号的一个周期。

33. 发明授权

US07184304B2 Nonvolatile semiconductor memory device and method for fabricating the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07184304B2
公开(公告)日：2007-02-27
申请号：US11191963
申请日：2005-07-29
申请人： Ryuji Nishihara , Masashi Agata , Toshiaki Kawasaki , Masanori Shirahama
发明人： Ryuji Nishihara , Masashi Agata , Toshiaki Kawasaki , Masanori Shirahama
IPC分类号： G11C16/04
CPC分类号： G11C16/12
摘要： A semiconductor memory device includes: first and second bit cells for storing complementary data; a scan circuit for outputting a selected data signal; a bit-cell selector receiving the output of the scan circuit and selecting one of the bit cells; and a data write controlling circuit for controlling data writing. Write paths for all the bit cells for storing “0” are not selected and data is written only in a bit cell for storing “1”, so that write operation performed in steps is achieved.
摘要翻译：半导体存储器件包括：用于存储互补数据的第一和第二位单元; 用于输出所选数据信号的扫描电路; 接收所述扫描电路的输出并选择所述位单元之一的位单元选择器; 以及用于控制数据写入的数据写入控制电路。用于存储“0”的所有位单元的写入路径不被选择，并且数据仅被写入用于存储“1”的位单元中，从而实现了步骤执行的写入操作。

34. 发明授权

US06862205B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06862205B2
公开(公告)日：2005-03-01
申请号：US10372971
申请日：2003-02-26
申请人： Masashi Agata , Kazunari Takahashi
发明人： Masashi Agata , Kazunari Takahashi
IPC分类号： G11C11/403 , G11C8/18 , G11C11/405 , G11C11/406 , G11C11/408 , G11C11/24 , G11C7/00 , G11C7/02 , G11C8/00 , G11C11/34
CPC分类号： G11C8/18 , G11C11/405 , G11C11/406 , G11C11/4085
摘要： The semiconductor memory device includes: a memory cell including a capacitor having a charge storage node and a first MIS transistor and a second MIS transistor each having a source connected to the charge storage node; a first word line and a first bit line respectively connected to the gate and the drain of the first MIS transistor; a second word line and a second bit line respectively connected to the gate and the drain of the second MIS transistor; and a timer circuit for generating a periodic signal having a predetermined period. The first word line or the second word line is activated in response to the periodic signal.
摘要翻译：半导体存储器件包括：存储单元，其包括具有电荷存储节点的电容器和第一MIS晶体管和第二MIS晶体管，每个MIS晶体管的源极连接到电荷存储节点; 分别连接到第一MIS晶体管的栅极和漏极的第一字线和第一位线; 分别连接到第二MIS晶体管的栅极和漏极的第二字线和第二位线; 以及用于产生具有预定周期的周期信号的定时器电路。第一字线或第二字线响应于周期性信号被激活。

35. 发明授权

US06744657B2 Read only data bus and write only data bus forming in different layer metals 有权
标题翻译：只读数据总线，只写数据总线形成在不同的金属层
公开(公告)号：US06744657B2
公开(公告)日：2004-06-01
申请号：US10245012
申请日：2002-09-16
申请人： Masashi Agata
发明人： Masashi Agata
IPC分类号： G11C506
CPC分类号： G11C5/063 , G11C7/10
摘要： A semiconductor memory device that enables data buses to operate at high speed by reducing wiring capacitance and interference noise between data bus lines is provided. A semiconductor memory device includes a read-only data bus which is formed in a first metal layer and has plural pairs of read lines precharged to an arbitrary voltage and two lines in a pair transmitting complementary read signals. A write-only data bus, which is positioned in parallel with the read-only data bus, is formed in a second metal layer different from the first metal layer and has plural pairs of write lines precharged to an arbitrary voltage, and two lines in a pair transmitting complementary write signals.
摘要翻译：提供一种使数据总线能够通过减少数据总线之间的布线电容和干扰噪声而高速运行的半导体存储器件。半导体存储器件包括：只读数据总线，其形成在第一金属层中，并且具有预先充电到任意电压的多对读取线和成对发送互补读取信号的两条线。与只读数据总线并联设置的只写数据总线形成在与第一金属层不同的第二金属层中，并且具有预先充电到任意电压的多对写入线，一对发送补充写信号。

36. 发明授权

US06563757B2 Semiconductor memory device 有权
公开(公告)号：US06563757B2
公开(公告)日：2003-05-13
申请号：US10043324
申请日：2002-01-14
申请人： Masashi Agata
发明人： Masashi Agata
IPC分类号： G11C1908
CPC分类号： G11C11/406 , G11C11/4087
摘要： One memory cell array is divided into three memory sub-arrays, each having a sense amplifier sub-array. A refresh word line selection circuit is provided for each memory sub-array. When a word line in the memory sub-array located in the center, for example, is to be selected in response to an external access request, a selector in the center selects a row decoder to allow selection of the word line designated by the external address. Simultaneously, a selector for each of the other memory sub-arrays selects the refresh word line selection circuit to allow selection of one word line to be refreshed in the memory sub-array. Thus, refresh operation can be performed simultaneously in the memory cell array in which a word line is being selected in response to the external access request.

37. 发明授权

US06333876B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06333876B1
公开(公告)日：2001-12-25
申请号：US09536697
申请日：2000-03-28
申请人： Toshiaki Kawasaki , Masashi Agata , Toshihiro Inokuchi
发明人： Toshiaki Kawasaki , Masashi Agata , Toshihiro Inokuchi
IPC分类号： G11C700
CPC分类号： G11C29/802 , G11C29/848
摘要： The semiconductor memory device of the present invention has: a memory cell array including a plurality of memory cell groups and a redundant cell group having a plurality of redundant cells arranged in parallel with the memory cell groups; a cell selection circuit for allowing one of a plurality of cell selection lines to select a specific memory cell group; a defective cell designation section for outputting defective cell designation signals designating a predetected defective cell out of the plurality of memory cells; and a connection change circuit for electrically disconnecting the cell selection line selecting the memory cell group including the defective cell from the cell selection circuit and outputting an output signal from the cell selection circuit to the redundant cell group. The defective cell designation section includes: a plurality of defective cell designation circuits for outputting designation signals capable of designating the plurality of cell selection lines; and a defective cell designation signal generation circuit for generating and outputting the defective cell designation signals based on the designation signals output from the plurality of defective cell designation circuits. The number of the plurality of defective cell designation circuits is smaller than the number of the plurality of cell selection lines.
摘要翻译：本发明的半导体存储器件具有：包括多个存储单元组的存储单元阵列和具有与存储单元组并联布置的多个冗余单元的冗余单元组;单元选择电路，用于允许多个单元选择线，用于选择特定的存储单元组;缺陷单元指定单元，用于输出指定多个存储单元中预先检测的缺陷单元的缺陷单元指定信号;以及连接变换电路，用于电连接单元选择，存储单元组，其包括来自单元选择电路的缺陷单元，并将来自单元选择电路的输出信号输出到冗余单元组。有缺陷单元指定部分包括：多个缺陷单元指定电路，用于输出能够指定多个单元选择线的指定信号; 以及有缺陷单元指定信号产生电路，用于基于从多个有缺陷单元指定电路输出的指定信号产生和输出有缺陷单元指定信号。多个有缺陷单元指定电路的数量小于多个单元选择线的数量。

38. 发明授权

US06327210B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06327210B1
公开(公告)日：2001-12-04
申请号：US09711884
申请日：2000-11-15
申请人： Naoki Kuroda , Masashi Agata
发明人： Naoki Kuroda , Masashi Agata
IPC分类号： G11C800
CPC分类号： G11C11/406
摘要： A semiconductor memory device allowing for high-speed random accesses and yet requiring no external refreshing by performing internal refreshing automatically and efficiently. If no external commands /RE or /WT, instructing that data should be read out or written on a memory cell, are given, the output signal of a first AND gate is asserted. A second AND gate is provided to obtain a logical product of the output signal of the first AND gate and an internal refresh signal INTREF representing that refreshing may be performed internally and independently. The output signal REFEN of the second AND gate is used as a reference signal for automatic refreshing. Thus, refreshing is performed automatically by taking advantage of a window during which no external commands are input. And when an external command is input, refreshing is canceled.
摘要翻译：半导体存储器件允许高速随机存取，并且通过自动而有效地执行内部刷新而不需要外部刷新。如果没有指定数据应该被读出或写入存储单元的外部命令/ RE或/ WT，则第一个与门的输出信号被断言。提供第二与门以获得第一与门的输出信号和内部刷新信号INTREF的逻辑积，表示刷新可以在内部和独立地执行。第二与门的输出信号REFEN用作自动刷新的参考信号。因此，通过利用没有输入外部命令的窗口来自动执行刷新。当输入外部命令时，刷新被取消。

39. 发明授权

US06243301B1 Semiconductor memory device and signal line switching circuit 有权
标题翻译：半导体存储器件和信号线开关电路
公开(公告)号：US06243301B1
公开(公告)日：2001-06-05
申请号：US09447674
申请日：1999-11-23
申请人： Masashi Agata , Naoki Kuroda , Makoto Kojima
发明人： Masashi Agata , Naoki Kuroda , Makoto Kojima
IPC分类号： G11C700
CPC分类号： G11C29/848
摘要： Redundancy function with excellent repair efficiency is implemented by specifying a single address for a semiconductor memory device of a multi-bit accessing type. A memory array includes a plurality of memory segments associated with respective addresses. Each memory segment is coupled to a data bus multiplexer via an associated first data bus. A sub-data bus, which includes a larger number of signal lines than that of those included in the first data bus, is provided for each memory segment. These signal lines are connected to associated bit lines in each memory sub-array. A data bus switching circuit is associated with each memory segment to electrically connect the respective signal lines included in the first data bus to the counterparts included in the sub-data bus to meet a predetermined relationship by cutting one of fuses off. In this manner, redundancy function with excellent repair efficiency is implementable on a bit-by-bit basis, not on an address basis.
摘要翻译：通过为多位访问类型的半导体存储器件指定单个地址来实现具有优异修复效率的冗余功能。存储器阵列包括与相应地址相关联的多个存储器段。每个存储器段通过相关联的第一数据总线耦合到数据总线多路复用器。为每个存储器段提供了包括比包括在第一数据总线中的信号线数量更多的信号线的子数据总线。这些信号线连接到每个存储器子阵列中的相关位线。数据总线切换电路与每个存储器段相关联，以将包括在第一数据总线中的各个信号线与包含在子数据总线中的对应电路电连接，以通过切断熔断器之一来满足预定的关系。以这种方式，具有优异的修复效率的冗余功能可以逐位地实现，而不是基于地址。

40. 发明授权

US06226223B1 Low latency dynamic random access memory 有权
标题翻译：低延迟动态随机存取存储器
公开(公告)号：US06226223B1
公开(公告)日：2001-05-01
申请号：US09511901
申请日：2000-02-23
申请人： Masanori Shirahama , Tsutomu Fujita , Masashi Agata , Kazunari Takahashi , Naoki Kuroda
发明人： Masanori Shirahama , Tsutomu Fujita , Masashi Agata , Kazunari Takahashi , Naoki Kuroda
IPC分类号： G11C800
CPC分类号： G11C7/222 , G11C7/22 , G11C11/24 , G11C11/4076
摘要： In a semiconductor memory device with multiple memory cells, each including a charge storage device and two transfer devices for transferring its charge, these memory cells are accessible with no select signal provided externally. The memory device includes a clock generator for generating first and second mutually complementary clock signals. In response to the first and second clock signals, one of first word lines and one of second word lines are activated alternately. Specifically, the first clock signal makes a memory cell accessible through a first bit line by activating the first word line and first transistor, while the second clock signal makes the memory cell accessible through a second bit line by activating the second word line and second transistor.
摘要翻译：在具有多个存储器单元的半导体存储器件中，每个存储单元包括一个电荷存储器件和两个用于传送其电荷的转移器件，这些存储器单元是可以被访问的，没有从外部提供的选择信号。存储器件包括用于产生第一和第二互补时钟信号的时钟发生器。响应于第一和第二时钟信号，交替地激活第一字线和第二字线之一中的一个。具体地，第一时钟信号通过激活第一字线和第一晶体管使得可通过第一位线访问存储单元，而第二时钟信号通过激活第二字线和第二晶体管使存储单元通过第二位线访问。

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