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    • 31. 发明申请
    • THREE-DIMENSIONAL DATA DISPLAY APPARATUS AND METHOD
    • 三维数据显示装置和方法
    • US20110050686A1
    • 2011-03-03
    • US12862981
    • 2010-08-25
    • Kai NOJIMAAtsushi TakeuchiKenji NagaseEiji Ohta
    • Kai NOJIMAAtsushi TakeuchiKenji NagaseEiji Ohta
    • G06T15/00
    • G06F3/04815
    • A three-dimensional data display apparatus is provided with a screen display processing section that generates a display screen with a structure arranged in a virtual space of a three-dimensional orthogonal coordinate system based on structure information stored in a data storage section and displays the display screen on a monitor, a grid setting-updating section that sets a grid in the virtual space, an operation information acquiring section that acquires operation information from a mouse, an input point position calculation section that calculates coordinates of an input point in the virtual space, calculates a moving destination of the input point based on the operation information, selects coordinates nearest to the moving destination of the input point from any one of the coordinates of each grid lattice based on the grid in the virtual space, the coordinates of a boundary of the structure and the coordinates of the point of intersection between the boundary of the structure and the grid and updates the coordinates of the input point and an input point display processing section that displays the input point at the updated coordinates.
    • 三维数据显示装置具有:屏幕显示处理部,其基于存储在数据存储部中的结构信息,生成具有布置在三维正交坐标系的虚拟空间中的结构的显示画面,并显示该显示画面 屏幕,在虚拟空间中设置网格的网格设置更新部分,从鼠标获取操作信息的操作信息获取部分,计算虚拟空间中的输入点的坐标的输入点位置计算部分 基于操作信息计算输入点的移动目的地,基于虚拟空间中的网格,从每个网格的任意一个坐标中选择最接近输入点的移动目的地的坐标,边界的坐标 的结构和坐标点之间的交点的结构a的边界 d网格并更新输入点的坐标和在更新的坐标处显示输入点的输入点显示处理部分。
    • 36. 发明授权
    • Semiconductor integrated circuit with stepped-down voltage generating circuit
    • 具有降压产生电路的半导体集成电路
    • US07538602B2
    • 2009-05-26
    • US11651966
    • 2007-01-11
    • Atsushi Takeuchi
    • Atsushi Takeuchi
    • G05F3/16H02M3/16
    • G05F3/242G11C5/145H02M1/36H02M3/073H02M2001/0032H03K5/2481Y02B70/16
    • A semiconductor integrated circuit includes a voltage generating circuit configured to generate a predetermined voltage, an NMOS transistor configured to receive at a gate node thereof the predetermined voltage generated by the voltage generating circuit, to receive at a drain node thereof an external power supply voltage, and to generate at a source node thereof a stepped-down voltage by reducing the external power supply voltage in response to the predetermined voltage, and a PMOS transistor, provided between the drain node of the NMOS transistor and the external power supply voltage, configured to receive at a gate node thereof a power-down signal indicative of a power-down mode. The predetermined voltage applied to the gate node of the NMOS transistor is set to LOW in response to a HIGH state of the power-down signal applied to the gate node of the PMOS transistor.
    • 半导体集成电路包括:电压产生电路,被配置为产生预定电压; NMOS晶体管,被配置为在其栅极节点处接收由所述电压产生电路产生的预定电压,以在其漏极节点接收外部电源电压; 并且在其源节点处通过响应于预定电压减小外部电源电压而产生降压电压,以及设置在NMOS晶体管的漏极节点和外部电源电压之间的PMOS晶体管,被配置为 在其门节点处接收指示掉电模式的掉电信号。 响应于施加到PMOS晶体管的栅极节点的掉电信号的HIGH状态,施加到NMOS晶体管的栅极节点的预定电压被设置为LOW。
    • 40. 发明申请
    • Voltage supply circuit and semiconductor memory
    • 电源电路和半导体存储器
    • US20060291317A1
    • 2006-12-28
    • US11260196
    • 2005-10-28
    • Atsushi Takeuchi
    • Atsushi Takeuchi
    • G11C5/14
    • G11C11/4074G11C5/14G11C7/12G11C11/4094G11C2207/2227
    • Each of first and second differential amplifiers has a function of increasing a bias current in response to the activation of a drivability control signal. A first driving circuit connects an output node to a high power supply line in response to the activation of an output signal of the first differential amplifier, and connects the output node to a low power supply line in response to the activation of an output signal of the second differential amplifier. Only during the activation period of the drivability control signal, a second driving circuit connects the output node to the high power supply line in response to the activation of the output signal of the first differential amplifier, and connects the output node to the low power supply line in response to the activation of the output signal of the second differential amplifier.
    • 第一和第二差分放大器中的每一个具有响应于驾驶性能控制信号的激活而增加偏置电流的功能。 响应于第一差分放大器的输出信号的激活,第一驱动电路将输出节点连接到高电源线,并且响应于激活输出信号的输出信号而将输出节点连接到低电源线 第二个差分放大器。 仅在驾驶员控制信号的激活期间,响应于第一差分放大器的输出信号的激活,第二驱动电路将输出节点连接到高电源线,并将输出节点连接到低电源 响应于第二差分放大器的输出信号的激活。