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31. 发明申请

US20050278516A1 Predicted return address selection upon matching target in branch history table with entries in return address stack 失效
标题翻译：在分支历史表中匹配目标的预测返回地址选择与返回地址堆栈中的条目
公开(公告)号：US20050278516A1
公开(公告)日：2005-12-15
申请号：US11207825
申请日：2005-08-22
申请人： Masaki Ukai , Kyoko Tashima , Aiichiro Inoue
发明人： Masaki Ukai , Kyoko Tashima , Aiichiro Inoue
IPC分类号： G06F9/00 , G06F9/32 , G06F9/38 , G06F9/42
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/3844 , G06F9/3861
摘要： An information processing apparatus is capable of speculatively performing an execution, such as a pipeline/superscalar/out-of-order execution and equipped with a branch prediction mechanism (a branch history). The information processing apparatus, in order to process an instruction sequence that includes a subroutine at a high speed, is further equipped with a return address stack, of which the stack operation is activated at a time of completing execution of an subroutine call/return correspondent instruction and an entry designating unit (pointer), in order to adjust a time difference resulting from an instruction fetch being executed prior to completing an instruction, pointing to a position relative to the stack front and adjusting a time difference between an instruction fetch performed speculatively in advance and completion of an instruction both at a time of completing execution of a branch instruction that is correspondent to a subroutine call/return and at a time of predicting a subroutine call/return in synchrony to the instruction fetch. An entry position correspondent to a stack position pointed to by the entry designation unit is adopted as a subroutine call/return prediction address and consequently the prediction of the subroutine return address becomes more accurate and the processing speed becomes higher.
摘要翻译：信息处理装置能够推测性地执行诸如流水线/超标量/无序执行并且配备有分支预测机制（分支历史）的执行。信息处理装置为了处理包含子程序的高速指令序列，还配备有返回地址堆栈，在完成子程序调用/返回对应的执行时堆栈操作被激活指令和条目指定单元（指针），以便调整在完成指令之前执行的指令提取导致的时间差，指向相对于堆栈前端的位置，并且调整在推测上执行的指令提取之间的时间差在完成执行与子程序调用/返回相对应的分支指令时以及在与指令获取同步地预测子程序调用/返回时，提前执行指令并完成指令。采用由入口指定单元指向的堆栈位置的入口位置作为子程序调用/返回预测地址，因此子程序返回地址的预测变得更准确，处理速度变高。

32. 发明申请

US20050246506A1 Information processing device, processor, processor control method, information processing device control method and cache memory 有权
标题翻译：信息处理装置，处理器，处理器控制方法，信息处理装置控制方法和缓存
公开(公告)号：US20050246506A1
公开(公告)日：2005-11-03
申请号：US10937253
申请日：2004-09-10
申请人： Masaki Ukai
发明人： Masaki Ukai
IPC分类号： G06F1/32 , G06F9/30 , G06F9/312 , G06F9/34 , G06F9/38 , G06F9/46 , G06F9/52 , G06F12/08 , G06F15/16 , G06F15/177 , G06F12/00
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30087 , G06F9/3009 , G06F9/526 , G06F2209/521
摘要： In a method for controlling a processor which accesses information of a storage device through cache memory, when reading information stored in a target address or an address range of the storage device, it is monitored whether there is an update access to the address or address range from another processor, and also the processor is entered into a suspense status, which is released using the occurrence of the update access to the storage device from another processor as a trigger.
摘要翻译：一种用于控制通过高速缓冲存储器访问存储设备的信息的处理器的方法，当读取存储在存储设备的目标地址或地址范围中的信息时，监视是否存在对地址或地址范围的更新访问并且还将处理器输入到暂停状态，该状态使用从作为触发器的另一处理器对存储设备的更新访问的发生而被释放。

33. 发明申请

US20050198480A1 Apparatus and method of controlling instruction fetch 审中-公开
标题翻译：控制指令提取的装置和方法
公开(公告)号：US20050198480A1
公开(公告)日：2005-09-08
申请号：US11125212
申请日：2005-05-10
申请人： Masaki Ukai , Aiichiro Inoue
发明人： Masaki Ukai , Aiichiro Inoue
IPC分类号： G06F9/00 , G06F9/38
CPC分类号： G06F9/3804 , G06F9/3802
摘要： An instruction control apparatus, and method, used with a device including a cache memory, a lower memory, an instruction fetch device issuing an instruction fetch request for a target of a first branch instruction to the cache memory, and an instruction control device processing a instruction sequence stored in the cache memory. The apparatus and method pre-prefetch a target instruction sequence for a target of a second branch instruction. A predetermined instruction sequence based on a past history is preliminarily transferred from the lower memory to the cache memory when the target instruction sequence for the target of the first branch instruction is not in the cache memory.
摘要翻译：一种指令控制装置和方法，与包括高速缓冲存储器，下位存储器，向第一转移指令的指令取出请求发出到高速缓冲存储器的指令取出装置的装置一起使用，以及指令控制装置，存储在高速缓冲存储器中的指令序列。该装置和方法为第二分支指令的目标预预取目标指令序列。当第一分支指令的目标的目标指令序列不在高速缓冲存储器中时，基于过去历史的预定指令序列被预先从下部存储器传送到高速缓冲存储器。

34. 发明授权

US06912650B2 Pre-prefetching target of following branch instruction based on past history 失效
标题翻译：根据过去的历史预先预取跟随分支指令的目标
公开(公告)号：US06912650B2
公开(公告)日：2005-06-28
申请号：US09793559
申请日：2001-02-27
申请人： Masaki Ukai , Aiichiro Inoue
发明人： Masaki Ukai , Aiichiro Inoue
IPC分类号： G06F9/00 , G06F9/38
CPC分类号： G06F9/3804 , G06F9/3802
摘要： An instruction control apparatus, and method, used with a device including a cache memory, a lower memory, an instruction fetch device issuing an instruction fetch request for a target of a first branch instruction to the cache memory, and an instruction control device processing a instruction sequence stored in the cache memory. The apparatus and method pre-prefetch a target instruction sequence for a target of a second branch instruction. A predetermined instruction sequence based on a past history is preliminarily transferred from the lower memory to the cache memory when the target instruction sequence for the target of the first branch instruction is not in the cache memory.
摘要翻译：一种指令控制装置和方法，与包括高速缓冲存储器，下位存储器，向第一转移指令的指令取出请求发出到高速缓冲存储器的指令取出装置的装置一起使用，以及指令控制装置，存储在高速缓冲存储器中的指令序列。该装置和方法为第二分支指令的目标预预取目标指令序列。当第一分支指令的目标的目标指令序列不在高速缓冲存储器中时，基于过去历史的预定指令序列被预先从下部存储器传送到高速缓冲存储器。

35. 发明授权

US08312218B2 Cache controller and cache control method 有权
标题翻译：缓存控制器和缓存控制方法
公开(公告)号：US08312218B2
公开(公告)日：2012-11-13
申请号：US12230244
申请日：2008-08-26
申请人： Masaki Ukai
发明人： Masaki Ukai
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F12/0844 , G06F12/0857 , G06F12/0859 , G06F2212/1016 , G06F2212/1056
摘要： A cache controller that writes data to a cache memory, includes a first buffer unit that retains data flowing in via an external bus, a second buffer unit that retrieves a piece of the data to be written to the cache memory, and a write controlling unit that controls writing of the piece of the data retrieved by the second buffer unit to the cache memory.
摘要翻译：一种将数据写入高速缓冲存储器的高速缓存控制器，包括保持经由外部总线流入的数据的第一缓冲单元，检索要写入高速缓冲存储器的一段数据的第二缓冲单元，以及写入控制单元其控制将由第二缓冲单元检索的数据片段写入缓存存储器。

36. 发明授权

US08060698B2 Method and apparatus for controlling degradation data in cache 失效
标题翻译：控制缓存中的劣化数据的方法和装置
公开(公告)号：US08060698B2
公开(公告)日：2011-11-15
申请号：US12219080
申请日：2008-07-15
申请人： Souta Kusachi , Kuniki Morita , Masaki Ukai , Tomoyuki Okawa
发明人： Souta Kusachi , Kuniki Morita , Masaki Ukai , Tomoyuki Okawa
IPC分类号： G06F12/00 , G06F12/16
CPC分类号： G06F12/0846 , G06F11/1064 , G06F12/0864
摘要： A cache controller controls at least one cache. The cache includes ways including a plurality of blocks that stores therein entry data. A writing unit writes degradation data to a failed block. The degradation data indicates that the failed block is in a degradation state. A reading unit reads entry data from a block. A determining unit determines, if the entry data obtained by the reading unit includes the degradation data, that the block is in the degradation state.
摘要翻译：缓存控制器控制至少一个缓存。缓存包括包括存储入口数据的多个块的方式。写入单元将劣化数据写入故障块。劣化数据表明故障块处于劣化状态。读取单元从块读取条目数据。确定单元确定由读取单元获得的输入数据是否包括劣化数据，判定该块处于退化状态。

37. 发明申请

US20100187116A1 Paste form heat-blowing injection composition and method for injecting and soundproofing closed section of automobile body member 有权
标题翻译：糊状热风注射成型及汽车车身密封部分注射隔音方法
公开(公告)号：US20100187116A1
公开(公告)日：2010-07-29
申请号：US12659507
申请日：2010-03-11
申请人： Yutaka Sugiura , Masaki Ukai , Kiyoyuki Gotou
发明人： Yutaka Sugiura , Masaki Ukai , Kiyoyuki Gotou
IPC分类号： B62D25/00 , C25D7/00 , C25D5/50
CPC分类号： B62D29/002 , C08J9/0061 , C08J2321/00 , C08J2363/00 , C08J2421/00 , C08J2463/00 , C08L21/00
摘要： An automatic injecting type paste form heat-blowing injection composition comprising a partially crosslinked rubber, an unvulcanized rubber, a crosslinking agent, a plasticizer, a thermoplastic resin, an epoxy resin and a latent curing agent thereof, and a blowing agent. This composition can be used in a injecting and soundproofing method comprising forming an insulation wall by heating and foaming of a injection composition in a closed section of an automobile body part having a closed section frame which is produced by press molding in a body welding step of an automobile manufacturing line, and it has a good anti-stringy property and suffers form less sagging during heating and foaming.
摘要翻译：一种包含部分交联橡胶，未硫化橡胶，交联剂，增塑剂，热塑性树脂，环氧树脂和潜在性固化剂的自动注射型糊状热喷射组合物和发泡剂。该组合物可用于注射和隔音方法中，包括通过在具有封闭截面框架的汽车车身部件的封闭部分中加热和发泡注射组合物来形成绝缘壁，所述封闭部分框架通过在本体焊接步骤汽车制造生产线，具有良好的抗拉性能，在加热和发泡过程中形成较少的下垂。

38. 发明授权

US07636837B2 Apparatus and method for controlling instructions at time of failure of branch prediction 失效
标题翻译：用于在分支预测失败时控制指令的装置和方法
公开(公告)号：US07636837B2
公开(公告)日：2009-12-22
申请号：US11114202
申请日：2005-04-26
申请人： Ryuichi Sunayama , Aiichirou Inoue , Masaki Ukai
发明人： Ryuichi Sunayama , Aiichirou Inoue , Masaki Ukai
IPC分类号： G06F12/00
CPC分类号： G06F9/3804
摘要： An apparatus includes a branch instruction prediction unit configured to make branch prediction, and a branch prediction control unit configured to control an instruction fetch control unit, an instruction buffer, an instruction decoder, and the branch instruction prediction unit, wherein when the branch prediction control unit ascertains that the branch prediction by the branch instruction prediction unit is erroneous, the branch prediction control unit outputs to the instruction fetch control unit a signal for suppressing an instruction fetch request already supplied to the memory unit and outputs to the instruction buffer a signal for nullifying the instruction buffer during a period between a point in time at which the ascertainment is made by the branch prediction control unit that the branch prediction by the branch instruction prediction unit is erroneous and a point in time at which the instruction buffer fetches a correct instruction from the memory unit.
摘要翻译：一种装置，包括：分支指示预测单元，用于进行分支预测;以及分支预测控制单元，被配置为控制指令获取控制单元，指令缓冲器，指令解码器和分支指令预测单元，其中当分支预测控制单元确定分支指令预测单元的分支预测是错误的，分支预测控制单元向指令获取控制单元输出用于抑制已经提供给存储单元的指令获取请求的信号，并向指令缓冲器输出用于在分支预测控制单元确定分支指令预测单元的分支预测错误的时间点和指令缓冲器获取正确指令的时间点之间的时间段期间使指令缓冲器无效从存储单元。

39. 发明申请

US20080162818A1 Cache-memory control apparatus, cache-memory control method and computer product 有权
标题翻译：缓存存储器控制装置，缓存存储器控制方法和计算机产品
公开(公告)号：US20080162818A1
公开(公告)日：2008-07-03
申请号：US11980386
申请日：2007-10-31
申请人： Tomoyuki Okawa , Hiroyuki Kojima , Hideki Sakata , Masaki Ukai
发明人： Tomoyuki Okawa , Hiroyuki Kojima , Hideki Sakata , Masaki Ukai
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0811
摘要： A cache-memory control apparatus controls a level-1 (L1) cache and a level-2 (L2) cache having a cache line divided into a plurality of sub-lines for storing data from the L1 cache. The cache-memory control apparatus includes a control-flag adding unit, an L1 cache control unit, and an L2 cache control unit. The control-flag adding unit provides an SP flag to each of the sub-lines. The L1-cache control unit acquires an access virtual address, and, when there is no data at the access virtual address, outputs an L2 cache-access address to the L2-cache control unit. The L2-cache control unit switches the SP flag based on a virtual page number in an L1 index and a physical page number in an L2 index. Based on the SP flag, corresponding one of the sub-lines is written back to the L1 cache.
摘要翻译：高速缓冲存储器控制装置控制一级（L1）高速缓存和二级（L2）高速缓存，该缓存具有被划分成用于存储来自L1高速缓存的数据的多条子行的高速缓存行。高速缓冲存储器控制装置包括控制标志添加单元，L1高速缓存控制单元和L2高速缓存控制单元。控制标志添加单元向每个子线提供SP标志。 L1高速缓存控制单元获取访问虚拟地址，并且当在访问虚拟地址处没有数据时，向L2高速缓存控制单元输出L2高速缓存访问地址。 L2缓存控制单元基于L1索引中的虚拟页号和L2索引中的物理页号来切换SP标志。基于SP标志，相应的一条子行被写回到L1高速缓存。

40. 发明授权

US07350062B2 Predicted return address from return stack entry designated by computation unit with multiple inputs including return hit flag and re-fetch signal 失效
标题翻译：由具有多个输入的计算单元指定的返回堆栈条目的预测返回地址包括返回命中标志和重新获取信号
公开(公告)号：US07350062B2
公开(公告)日：2008-03-25
申请号：US11207825
申请日：2005-08-22
申请人： Masaki Ukai , Kyoko Tashima , Aiichiro Inoue
发明人： Masaki Ukai , Kyoko Tashima , Aiichiro Inoue
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/3844 , G06F9/3861
摘要： An information processing apparatus is capable of speculatively performing an execution, such as a pipeline/superscalar/out-of-order execution and equipped with a branch prediction mechanism (a branch history). The information processing apparatus, in order to process an instruction sequence that includes a subroutine at a high speed, is further equipped with a return address stack, of which the stack operation is activated at a time of completing execution of an subroutine call/return correspondent instruction and an entry designating unit (pointer), in order to adjust a time difference resulting from an instruction fetch being executed prior to completing an instruction, pointing to a position relative to the stack front and adjusting a time difference between an instruction fetch performed speculatively in advance and completion of an instruction both at a time of completing execution of a branch instruction that is correspondent to a subroutine call/return and at a time of predicting a subroutine call/return in synchrony to the instruction fetch. An entry position correspondent to a stack position pointed to by the entry designation unit is adopted as a subroutine call/return prediction address and consequently the prediction of the subroutine return address becomes more accurate and the processing speed becomes higher.
摘要翻译：信息处理装置能够推测性地执行诸如流水线/超标量/无序执行并且配备有分支预测机制（分支历史）的执行。信息处理装置为了处理包含子程序的高速指令序列，还配备有返回地址堆栈，其中堆栈操作在完成子程序调用/返回通讯器的执行时被激活指令和条目指定单元（指针），以便调整在完成指令之前执行的指令提取导致的时间差，指向相对于堆栈前端的位置，并且调整在推测上执行的指令提取之间的时间差在完成执行与子程序调用/返回相对应的分支指令时以及在与指令获取同步地预测子程序调用/返回时，提前执行指令并完成指令。采用由入口指定单元指向的堆栈位置的入口位置作为子程序调用/返回预测地址，因此子程序返回地址的预测变得更准确，处理速度变高。

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