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31. 发明授权

US08462908B2 Digital phase locked loop circuitry and methods 有权
标题翻译：数字锁相环电路及方法
公开(公告)号：US08462908B2
公开(公告)日：2013-06-11
申请号：US12974949
申请日：2010-12-21
申请人： Ramanand Venkata , Chong H. Lee
发明人： Ramanand Venkata , Chong H. Lee
IPC分类号： H03D3/24
CPC分类号： H03M9/00 , H03L7/089 , H03L2207/50 , H04L7/0008 , H04L7/0337
摘要： Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.
摘要翻译：锁相环电路以数字方式进行数字操作，至少在很大程度上从多个相位分布的候选时钟信号中选择最接近相位的信号，以便在诸如时钟数据恢复（“CDR”）信号的另一个信号中转换。该电路被构造和操作以避免由于候选时钟信号的选择变化而导致的输出时钟信号中的毛刺。候选时钟信号的分频可以用于帮助电路以低于锁相环电路的模拟部分可以经济地提供的频率的比特率来支持串行通信。出于同样的原因，发射侧可能会使用过量传输或过采样。

32. 发明授权

US07538578B2 Multiple data rates in programmable logic device serial interface 失效
标题翻译：可编程逻辑器件串行接口中的多个数据速率
公开(公告)号：US07538578B2
公开(公告)日：2009-05-26
申请号：US11177034
申请日：2005-07-08
申请人： Ramanand Venkata , Chong H Lee , Rakesh H Patel
发明人： Ramanand Venkata , Chong H Lee , Rakesh H Patel
IPC分类号： H03K19/177 , G06F13/42
CPC分类号： H03K19/17744
摘要： A serial interface for a programmable logic device can be operated according to various communications protocols and includes both a receiver portion and a transmitter portion. The receiver portion includes at least a word or byte alignment stage, a de-skew stage, a rate compensation or matching stage, a padded protocol decoder stage (e.g., 8B/10B decoder circuitry or 64B/66B decoder circuitry), a byte deserializer stage, a byte reorder stage, and a phase compensation stage. The transmitter portion includes at least a phase compensation stage, a byte deserializer stage, and a padded protocol encoder stage (e.g., an 8B/10B encoder circuitry or 64B/66B encoder circuitry). Each stage may have multiple occurrences of relevant circuitry. Selection circuitry, such as multiplexers, selects the appropriate stages, and circuitry within each stage, for the protocol being used.
摘要翻译：用于可编程逻辑器件的串行接口可以根据各种通信协议进行操作，并且包括接收器部分和发射器部分。接收器部分至少包括字或字节对准级，去偏移级，速率补偿或匹配级，填充协议解码器级（例如，8B / 10B解码器电路或64B / 66B解码器电路），字节解串器阶段，字节重排阶段和相位补偿阶段。发射机部分至少包括相位补偿级，字节解串器级和填充协议编码器级（例如，8B / 10B编码器电路或64B / 66B编码器电路）。每个阶段可能有多次出现相关的电路。选择电路，例如多路复用器，为所使用的协议选择适当的阶段和每个阶段内的电路。

33. 发明授权

US07310399B1 Clock signal circuitry for multi-protocol high-speed serial interface circuitry 有权
公开(公告)号：US07310399B1
公开(公告)日：2007-12-18
申请号：US11650163
申请日：2007-01-05
申请人： Ramanand Venkata , Chong H. Lee
发明人： Ramanand Venkata , Chong H. Lee
IPC分类号： H04L25/40
CPC分类号： G06F1/10
摘要： A programmable logic device (“PLD”) includes high-speed serial interface (“HSSI”) circuitry. The HSSI circuitry includes clock signal circuitry that allows various components of the HSSI circuitry to be clocked in different ways to facilitate use of the HSSI circuitry to support a number of different communication protocols. Some of the HSSI clock signals may be routed through the clock distribution network of the associated PLD logic circuitry. The HSSI circuitry may include phase compensation buffer circuitry to compensate for possible phase differences across the interface between the HSSI circuitry and the associated PLD logic circuitry.

34. 发明授权

US07180972B1 Clock signal circuitry for multi-protocol high-speed serial interface circuitry 有权
标题翻译：用于多协议高速串行接口电路的时钟信号电路
公开(公告)号：US07180972B1
公开(公告)日：2007-02-20
申请号：US10273899
申请日：2002-10-16
申请人： Ramanand Venkata , Chong H Lee
发明人： Ramanand Venkata , Chong H Lee
IPC分类号： H04L7/00
CPC分类号： G06F1/10
摘要： A programmable logic device (“PLD”) includes high-speed serial interface (“HSSI”) circuitry. The HSSI circuitry includes clock signal circuitry that allows various components of the HSSI circuitry to be clocked in different ways to facilitate use of the HSSI circuitry to support a number of different communication protocols. Some of the HSSI clock signals may be routed through the clock distribution network of the associated PLD logic circuitry. The HSSI circuitry may include phase compensation buffer circuitry to compensate for possible phase differences across the interface between the HSSI circuitry and the associated PLD logic circuitry.
摘要翻译：可编程逻辑器件（“PLD”）包括高速串行接口（“HSSI”）电路。 HSSI电路包括时钟信号电路，其允许HSSI电路的各种组件以不同的方式计时，以便于使用HSSI电路来支持多种不同的通信协议。一些HSSI时钟信号可以通过相关联的PLD逻辑电路的时钟分配网络路由。 HSSI电路可以包括相位补偿缓冲器电路，以补偿跨越HSSI电路和相关联的PLD逻辑电路之间的接口上的可能的相位差。

35. 发明申请

US20070188189A1 PROGRAMMABLE LOGIC DEVICE WITH SERIAL INTERCONNECT 有权
标题翻译：具有串行互连的可编程逻辑器件
公开(公告)号：US20070188189A1
公开(公告)日：2007-08-16
申请号：US11539006
申请日：2006-10-05
申请人： Ramanand Venkata , Rakesh Patel , Chong Lee
发明人： Ramanand Venkata , Rakesh Patel , Chong Lee
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17744 , H03K19/17784
摘要： In a programmable logic device, some or all of the parallel interconnect resources are replaced by serial interconnect resources within the device. Some or all of the functional blocks on the device are supplemented with serial interfaces. Although this makes the functional blocks more complex, it allows a significant reduction in the area consumed by interconnect resources. This translates into a significant reduction in device power consumption. The serial interfaces may operate synchronously from a global device clock (such as a PLL). In some cases, serial interfaces that are provided in the input/output blocks for external signalling can be omitted because the serial interfaces in the functional blocks can take over the external serial interface function as well, although in those cases the serial interfaces in the functional blocks would have to be more complex because they would have to be able to operate asynchronously with external devices.
摘要翻译：在可编程逻辑器件中，部分或全部并行互连资源由器件内的串行互连资源代替。设备上的部分或全部功能块被补充有串行接口。尽管这使得功能块更加复杂，但它允许显着减少互连资源消耗的面积。这意味着设备功耗的显着降低。串行接口可以与全局设备时钟（例如PLL）同步工作。在某些情况下，可以省略输入/输出块中提供的用于外部信号的串行接口，因为功能块中的串行接口也可以接管外部串行接口功能，尽管在这些情况下，功能中的串行接口块将不得不更复杂，因为它们必须能够与外部设备异步操作。

36. 发明申请

US20060233172A1 Multiple data rates in programmable logic device serial interface 失效
公开(公告)号：US20060233172A1
公开(公告)日：2006-10-19
申请号：US11177034
申请日：2005-07-08
申请人： Ramanand Venkata , Chong Lee , Rakesh Patel
发明人： Ramanand Venkata , Chong Lee , Rakesh Patel
IPC分类号： H04L12/28
CPC分类号： H03K19/17744
摘要： A serial interface for a programmable logic device can be operated according to various communications protocols and includes both a receiver portion and a transmitter portion. The receiver portion includes at least a word or byte alignment stage, a de-skew stage, a rate compensation or matching stage, a padded protocol decoder stage (e.g., 8B/10B decoder circuitry or 64B/66B decoder circuitry), a byte deserializer stage, a byte reorder stage, and a phase compensation stage. The transmitter portion includes at least a phase compensation stage, a byte deserializer stage, and a padded protocol encoder stage (e.g., an 8B/10B encoder circuitry or 64B/66B encoder circuitry). Each stage may have multiple occurrences of relevant circuitry. Selection circuitry, such as multiplexers, selects the appropriate stages, and circuitry within each stage, for the protocol being used.

37. 发明申请

US20070139232A1 Next generation 8B10B architecture 有权
公开(公告)号：US20070139232A1
公开(公告)日：2007-06-21
申请号：US11655797
申请日：2007-01-18
申请人： Ramanand Venkata , Rakesh Patel , Chong Lee
发明人： Ramanand Venkata , Rakesh Patel , Chong Lee
IPC分类号： H03M7/00
CPC分类号： G06F13/385
摘要： Eight-bit ten-bit (8B10B) coding is provided in a hard intellectual property (IP) block with the capability of supporting a greater range of data rates (e.g., data rates less than, equal to, and greater than 3.125 Gbps). Each channel of high speed serial interface circuitry includes receiver circuitry having two 8B10B decoders and transmitter circuitry having two 8B10B encoders. The receiver and transmitter circuitry can be configured to operate in one of three modes of operation: cascade mode, dual channel mode, and single channel mode.

38. 发明申请

US20060095613A1 Next generation 8B10B architecture 有权
标题翻译：下一代8B10B架构
公开(公告)号：US20060095613A1
公开(公告)日：2006-05-04
申请号：US10977952
申请日：2004-10-29
申请人： Ramanand Venkata , Rakesh Patel , Chong Lee
发明人： Ramanand Venkata , Rakesh Patel , Chong Lee
IPC分类号： G06F13/38
CPC分类号： G06F13/385
摘要： Eight-bit ten-bit (8B10B) coding is provided in a hard intellectual property (IP) block with the capability of supporting a greater range of data rates (e.g., data rates less than, equal to, and greater than 3.125 Gbps). Each channel of high speed serial interface circuitry includes receiver circuitry having two 8B10B decoders and transmitter circuitry having two 8B10B encoders. The receiver and transmitter circuitry can be configured to operate in one of three modes of operation: cascade mode, dual channel mode, and single channel mode.
摘要翻译：在具有支持更大范围的数据速率（例如，数据速率小于等于并且大于3.125Gbps）的能力的硬知识产权（IP）块中提供八位十位（8B10B）编码。高速串行接口电路的每个通道包括具有两个8B10B解码器和具有两个8B10B编码器的发射机电路的接收机电路。接收器和发射器电路可以配置为在三种工作模式之一下工作：级联模式，双通道模式和单通道模式。

39. 发明申请

US20050007996A1 Programmable logic devices with multi-standard byte synchronization and channel alignment for communication 有权
标题翻译：可编程逻辑器件具有多标准字节同步和通道对齐通讯
公开(公告)号：US20050007996A1
公开(公告)日：2005-01-13
申请号：US10835081
申请日：2004-04-28
申请人： Ramanand Venkata , Chong Lee , Rakesh Patel
发明人： Ramanand Venkata , Chong Lee , Rakesh Patel
IPC分类号： H03K19/177 , H04Q11/04 , H04J3/06
CPC分类号： H03K19/17744 , H03K19/17732 , H04J3/1617 , H04J2203/0082 , H04J2203/0094
摘要： A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.
摘要翻译：可编程逻辑器件（“PLD”）包括通信接口电路，其可以支持任何广泛的通信协议，包括分组超声波（“POS-5”）和8位/ 10比特（“8B10B”）协议。接口电路包括至少部分硬连线以执行特定类型的功能的各种功能块，但是在至少许多情况下也可部分地可编程以允许基本功能适应各种协议。对各种功能块之间，之间和/或周围的信号的路由也优选地至少可部分地可编程以便于以各种方式组合功能块来支持各种协议。

40. 发明授权

US07659838B2 Deserializer circuitry for high-speed serial data receivers on programmable logic device integrated circuits 有权
标题翻译：用于可编程逻辑器件集成电路上的高速串行数据接收器的解串器电路
公开(公告)号：US07659838B2
公开(公告)日：2010-02-09
申请号：US11359273
申请日：2006-02-21
申请人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch Zaliznyak , Tim Tri Hoang , Ramanand Venkata , Chong Lee
发明人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch Zaliznyak , Tim Tri Hoang , Ramanand Venkata , Chong Lee
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： Deserializer circuitry for high-speed serial data receiver circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting serial data to parallel data having any of several data widths. The circuitry can also operate at any frequency in a wide range of frequencies. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).
摘要翻译：用于可编程逻辑器件（“PLD”）等上的高速串行数据接收器电路的解串器电路包括用于将串行数据转换成具有若干数据宽度的并行数据的电路。电路也可以在宽频率范围内的任何频率下工作。该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

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