专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US08537595B2 Resistance change memory device 有权
标题翻译：电阻变化记忆装置
公开(公告)号：US08537595B2
公开(公告)日：2013-09-17
申请号：US13231687
申请日：2011-09-13
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C13/02
CPC分类号： G11C8/12 , G11C13/00 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/71 , G11C2213/72
摘要： A resistance change memory device includes: a cell array having multiple layers of mats laminated thereon, each of the mats having word lines and bit lines intersecting each other as well as resistance change type memory cells arranged at intersections thereof, each of the mats further having therein a reference cell and a reference bit line connected to the reference cell, the reference cell set to a state of a certain resistance value; a selection circuit configured to select a word line in each mat of the cell array, and select a bit line intersecting a selected word line and the reference bit line at the same time; and a sense amplifier configured to sense data by comparing respective cell currents of a selected memory cell on the selected bit line and the reference cell on the reference bit line.
摘要翻译：一种电阻变化存储器件包括：具有层叠在其上的多层垫的单元阵列，每个垫具有彼此相交的字线和位线以及布置在其交叉处的电阻变化型存储单元，每个垫还具有其中参考单元和连接到参考单元的参考位线，参考单元设置为一定电阻值的状态; 选择电路，被配置为选择单元阵列的每个矩阵中的字线，并且同时选择与所选择的字线和参考位线相交的位线; 以及读出放大器，被配置为通过比较所选位线上的所选存储单元和参考位线上的参考单元的各个单元电流来检测数据。

32. 发明授权

US08400816B2 Resistance change memory device 有权
标题翻译：电阻变化记忆装置
公开(公告)号：US08400816B2
公开(公告)日：2013-03-19
申请号：US13237500
申请日：2011-09-20
申请人： Haruki Toda , Hirofumi Inoue , Hiroto Nakai
发明人： Haruki Toda , Hirofumi Inoue , Hiroto Nakai
IPC分类号： G11C11/00
CPC分类号： G11C13/00 , G11C5/063 , G11C8/14 , G11C11/56 , G11C13/0028 , G11C13/004 , G11C2013/0054 , G11C2213/71 , G11C2213/72
摘要： A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.
摘要翻译：电阻变化存储器件包括：存储单元阵列，其中布置有存储单元，所述存储单元具有用于存储可重写电阻值的可变电阻元件; 由与存储单元阵列中的高电阻状态相同的存储单元形成的参考单元，通过选择并联连接的存储单元的数量来修整参考单元以具有用于检测数据的参考电流值存储单元阵列; 以及读出放大器，被配置为将存储单元阵列中选择的存储单元的单元电流值与参考单元的参考电流值进行比较。

33. 发明授权

US08315082B2 Resistance-changing memory device 有权
标题翻译：电阻变化存储器件
公开(公告)号：US08315082B2
公开(公告)日：2012-11-20
申请号：US13446137
申请日：2012-04-13
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/56 , G11C13/0033 , G11C13/004 , G11C16/3431 , G11C2013/0047 , G11C2013/0054 , G11C2213/72
摘要： A resistance-changing memory device has a cell array having memory cells, each of which stores as data a reversibly settable resistance value, a sense amplifier for reading data from a selected memory cell in the cell array, and a voltage generator circuit which generates, after having read data of the selected memory cell, a voltage pulse for convergence of a resistive state of this selected memory cell in accordance with the read data.
摘要翻译：电阻变化存储器件具有存储单元的单元阵列，每个存储单元存储数据作为可逆设置的电阻值，用于从单元阵列中的选定存储单元读取数据的读出放大器，以及电压发生器电路，在读取所选择的存储单元的数据之后，根据读取的数据，产生用于收敛该选择的存储单元的电阻状态的电压脉冲。

34. 发明授权

US08237143B2 Phase change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US08237143B2
公开(公告)日：2012-08-07
申请号：US13217493
申请日：2011-08-25
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： H01L29/02
CPC分类号： G11C13/0004 , G11C5/02 , G11C7/18 , G11C13/0007 , G11C2211/4013 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233
摘要： A memory device has a semiconductor substrate; a plurality of cell arrays stacked above the substrate, each cell array having memory cells, bit lines each commonly connecting one ends of plural cells arranged along a first direction and word lines each commonly connecting the other ends of plural cells arranged along a second direction; a read/write circuit formed on the substrate as underlying the cell arrays; first and second vertical wiring disposed on both sides of each cell array in the first direction to connect the bit lines to the read/write circuit; and third vertical wirings disposed on both sides of each cell array in the second direction to connect the word lines to the read/write circuit.
摘要翻译：存储器件具有半导体衬底; 多个单元阵列，堆叠在基板上方，每个单元阵列具有存储单元，每个通常连接沿着第一方向布置的多个单元的一端的位线和每个共同连接沿着第二方向布置的多个单元的另一端的字线; 在基板上形成的读/写电路，位于单元阵列下面; 第一和第二垂直布线沿着第一方向布置在每个单元阵列的两侧，以将位线连接到读/写电路; 以及在第二方向上设置在每个单元阵列两侧的第三垂直布线，以将字线连接到读/写电路。

35. 发明授权

US08194434B2 Resistance change memory device 有权
标题翻译：电阻变化记忆装置
公开(公告)号：US08194434B2
公开(公告)日：2012-06-05
申请号：US12605799
申请日：2009-10-26
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C11/00
CPC分类号： G11C5/063 , G11C5/025 , G11C13/0002 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/0083 , G11C2213/72
摘要： A resistance change memory device including: a cell array with memory cells arranged therein, the memory cell storing a resistance state as data in a non-volatile manner; a write buffer configured to supply voltage and current to a selected memory cell in accordance with data to be written in it; and a write control circuit configured to make a part of current supplied to the selected memory cell flow out in accordance with the selected memory cell's state change in a write mode.
摘要翻译：一种电阻变化存储器件，包括：具有排列在其中的存储单元的单元阵列，所述存储单元以非易失性方式存储电阻状态作为数据; 写缓冲器，被配置为根据要写入的数据向选定的存储单元提供电压和电流; 以及写入控制电路，被配置为使得提供给所选择的存储器单元的电流的一部分根据所选存储单元的写入模式的状态变化而流出。

36. 发明授权

US07836377B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07836377B2
公开(公告)日：2010-11-16
申请号：US11625160
申请日：2007-01-19
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C29/00
CPC分类号： H03M13/1545 , H03M13/152 , H03M13/159
摘要： A semiconductor memory device has a built-in error detection and correction system, wherein the error detection and correction system is formed to have a cyclic code, with which multiple error bits are correctable, and wherein the cyclic code is configured in such a manner that a certain number of degrees are selected as information bits from the entire degree of an information polynomial having degree numbers corresponding to an error-correctable maximal bit number, the certain number being a number of data bits which are simultaneously error-correctable in the memory device.
摘要翻译：半导体存储器件具有内置的错误检测和校正系统，其中，错误检测和校正系统形成为具有可纠错多个错误位的循环代码，并且其中循环代码被配置为使得从具有对应于可纠错最大位数的次数的信息多项式的整个程度中选择一定数量的度数，该特定数量是在存储器件中同时进行纠错的数据位数。

37. 发明授权

US07778062B2 Resistance change memory device 有权
标题翻译：电阻变化记忆装置
公开(公告)号：US07778062B2
公开(公告)日：2010-08-17
申请号：US11761400
申请日：2007-06-12
申请人： Haruki Toda , Koichi Kubo
发明人： Haruki Toda , Koichi Kubo
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0016 , G11C13/004 , G11C13/0069 , G11C17/16 , G11C17/165 , G11C2013/0042 , G11C2013/009 , G11C2213/31 , G11C2213/32 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A resistance change memory device including: a semiconductor substrate; at least one cell array formed above the semiconductor substrate, each memory cell having a stack structure of a variable resistance element and an access element, the access element having such an off-state resistance value in a certain voltage range that is ten times or more as high as that in a select state; and a read/write circuit formed on the semiconductor substrate as underlying the cell array for data reading and writing, wherein the variable resistance element comprises a recording layer composed of a composite compound containing at least two types of cation elements, at least one type of the cation element being a transition element having “d” orbit, in which electrons are incompletely filled, the shortest distance between adjacent cation elements being 0.32 nm or less.
摘要翻译：一种电阻变化存储器件，包括：半导体衬底; 形成在所述半导体衬底上的至少一个单元阵列，每个存储单元具有可变电阻元件和存取元件的堆叠结构，所述存取元件具有在十倍或更多的一定电压范围内的截止电阻值与选择状态一样高; 以及形成在半导体基板上的用于数据读写的单元阵列下面的读/写电路，其中可变电阻元件包括由包含至少两种类型的阳离子元素的复合化合物组成的记录层，至少一种阳离子元素是具有“d”轨道的过渡元素，其中电子未完全填充，相邻阳离子元素之间的最短距离为0.32nm以下。

38. 发明授权

US07750334B2 Phase change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US07750334B2
公开(公告)日：2010-07-06
申请号：US11958168
申请日：2007-12-17
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： H01L29/02
CPC分类号： G11C13/0004 , G11C5/02 , G11C7/18 , G11C13/0007 , G11C2211/4013 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233
摘要： A memory device has a semiconductor substrate; a plurality of cell arrays stacked above the substrate, each cell array having memory cells, bit lines each commonly connecting one ends of plural cells arranged along a first direction and word lines each commonly connecting the other ends of plural cells arranged along a second direction; a read/write circuit formed on the substrate as underlying the cell arrays; first and second vertical wirings disposed on both sides of each cell array in the first direction to connect the bit lines to the read/write circuit; and third vertical wirings disposed on both sides of each cell array in the second direction to connect the word lines to the read/write circuit.
摘要翻译：存储器件具有半导体衬底; 多个单元阵列，堆叠在基板上方，每个单元阵列具有存储单元，每个通常连接沿着第一方向布置的多个单元的一端的位线和每个共同连接沿着第二方向布置的多个单元的另一端的字线; 在基板上形成的读/写电路，位于单元阵列下面; 第一和第二垂直布线，沿着第一方向设置在每个单元阵列的两侧，以将位线连接到读/写电路; 以及在第二方向上设置在每个单元阵列两侧的第三垂直布线，以将字线连接到读/写电路。

39. 发明申请

US20100115383A1 MEMORY DEVICE WITH AN ECC SYSTEM 失效
标题翻译：具有ECC系统的存储器件
公开(公告)号：US20100115383A1
公开(公告)日：2010-05-06
申请号：US12555507
申请日：2009-09-08
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/152 , G06F11/1068 , H03M13/1575 , H03M13/3715
摘要： A memory device has an error detection and correction system constructed on a Galois finite field. The error detection and correction system includes calculation circuits for calculating the finite field elements based on syndromes obtained from read data and searching error locations, the calculation circuits having common circuits, which are used in a time-sharing mode under the control of internal clocks.
摘要翻译：存储器件具有在伽罗瓦有限域上构造的误差检测和校正系统。误差检测和校正系统包括用于基于从读取数据和搜索误差位置获得的综合数据计算有限域元素的计算电路，所述计算电路具有在内部时钟控制下的分时模式中使用的公共电路。

40. 发明授权

US07522462B2 Sense amplifier and semiconductor memory device with the same 有权
标题翻译：感应放大器和半导体存储器件相同
公开(公告)号：US07522462B2
公开(公告)日：2009-04-21
申请号：US11563408
申请日：2006-11-27
申请人： Toshiaki Edahiro , Haruki Toda
发明人： Toshiaki Edahiro , Haruki Toda
IPC分类号： G11C7/00
CPC分类号： G11C7/065 , G11C16/28
摘要： A sense amplifier includes: NMOS transistors, drains thereof being coupled to output nodes, gates thereof being coupled to the output nodes, sources thereof being coupled in common to the ground potential node; PMOS transistors, drains thereof being coupled to the drains of the NMOS transistors, sources thereof being coupled to the input nodes; PMOS transistors, drains thereof being coupled to the input nodes, gates thereof being coupled to the output nodes, sources thereof being coupled to the power supply node via a current source device; and NMOS transistors disposed between the output nodes and the ground potential node to be turned on before sensing; and an equalizing transistor disposed between the output nodes.
摘要翻译：读出放大器包括：NMOS晶体管，其漏极耦合到输出节点，其栅极耦合到输出节点，其源极共同耦合到地电位节点; PMOS晶体管，其漏极耦合到NMOS晶体管的漏极，其源极耦合到输入节点; PMOS晶体管，其漏极耦合到输入节点，其栅极耦合到输出节点，其源极经由电流源装置耦合到电源节点; 并且设置在所述输出节点和所述接地电位节点之间的NMOS晶体管将在感测之前导通; 以及设置在输出节点之间的均衡晶体管。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式