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31. 发明申请

US20090323830A1 CURRENT MODE CIRCUITRY TO MODULATE A COMMON MODE VOLTAGE 有权
标题翻译：电流模式电路来调制共模电压
公开(公告)号：US20090323830A1
公开(公告)日：2009-12-31
申请号：US12555300
申请日：2009-09-08
申请人： Daeyun Shim , Min-Kyu Kim , Gyudong Kim , Keewook Jung , Seung Ho Hwang
发明人： Daeyun Shim , Min-Kyu Kim , Gyudong Kim , Keewook Jung , Seung Ho Hwang
IPC分类号： H04B3/00 , H03K19/094 , H03K19/0175
CPC分类号： H04L5/20
摘要： In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and a second chip. The second chip includes receivers to receive the first and second differential signals from the conductors and provide received signals representative thereof, and current mode circuitry to selectively modulate a common mode voltage of either the first or second differential signals to communicate data and wherein the first chip includes common mode detection circuitry to detect changes in the common mode voltage. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，芯片包括在导体上传输差分信号的发射器; 以及电流模式电路，用于选择性地调制差分信号的共模电压以传送数据。在其他实施例中，系统包括用于在导体上传输第一和第二差分信号的第一芯片和第二芯片。第二芯片包括接收器，用于从导体接收第一和第二差分信号并提供表示其的接收信号;以及电流模式电路，用于选择性地调制第一或第二差分信号的共模电压以传送数据，并且其中第一芯片包括用于检测共模电压变化的共模检测电路。描述和要求保护其他实施例。

32. 发明授权

US07627044B2 Clock-edge modulated serial link with DC-balance control 有权
标题翻译：具有直流平衡控制的时钟调制串行链路
公开(公告)号：US07627044B2
公开(公告)日：2009-12-01
申请号：US11264303
申请日：2005-10-31
申请人： Gyudong Kim , Won Jun Choe , Deog-Kyoon Jeong , Jaeha Kim , Bong-Joon Lee , Min-Kyu Kim
发明人： Gyudong Kim , Won Jun Choe , Deog-Kyoon Jeong , Jaeha Kim , Bong-Joon Lee , Min-Kyu Kim
IPC分类号： H04B3/00
CPC分类号： H04L7/0008 , H04L25/0272 , H04L25/0284 , H04L25/4902
摘要： A battery powered computing device has a channel configured as a single direct current balanced differential channel. A signal transmitter is connected to the channel. The signal transmitter is configured to apply clock edge modulated signals to the channel, where the clock edge modulated signals include direct current balancing control signals. A signal receiver is connected to the channel. The signal receiver is configured to recover the direct current balancing control signals.
摘要翻译：电池供电的计算设备具有被配置为单个直流平衡差分通道的通道。信号发射器连接到通道。信号发射器被配置为将时钟边缘调制信号施加到信道，其中时钟边缘调制信号包括直流平衡控制信号。信号接收器连接到通道。信号接收器被配置为恢复直流平衡控制信号。

33. 发明申请

US20090177818A1 DISCOVERY OF ELECTRONIC DEVICES UTILIZING A CONTROL BUS 有权
标题翻译：使用控制总线的电子设备的发现
公开(公告)号：US20090177818A1
公开(公告)日：2009-07-09
申请号：US11969865
申请日：2008-01-04
申请人： Daeyun Shim , Shrikant Ranade , Ravi Sharma , Gyudong Kim
发明人： Daeyun Shim , Shrikant Ranade , Ravi Sharma , Gyudong Kim
IPC分类号： G06F13/00
CPC分类号： G06F3/14 , G09G5/006 , G09G2370/10 , G09G2370/12
摘要： Discovery of electronic devices utilizing a control bus. An embodiment of a method includes connecting a receiving device to a cable, where the cable includes a control bus. If the receiving device is in a disconnect state and a signal from a transmitting device is detected on the control bus, the device is transferred to a state for a first type of transmitting device. If the receiving device is in either the disconnect state or the state for the first type of transmitting device and a predetermined voltage signal is received from the transmitting device, then the receiving device is transferred to a state for a second type of transmitting device.
摘要翻译：发现使用控制总线的电子设备。一种方法的实施例包括将接收设备连接到电缆，其中电缆包括控制总线。如果接收设备处于断开状态并且在控制总线上检测到来自发送设备的信号，则设备被转移到用于第一类型的发送设备的状态。如果接收设备处于断开状态或第一类型的发送设备的状态，并且从发送设备接收到预定的电压信号，则接收设备被转移到第二类型的发送设备的状态。

34. 发明授权

US07558326B1 Method and apparatus for sending auxiliary data on a TMDS-like link 有权
标题翻译：在类似TMDS的链路上发送辅助数据的方法和装置
公开(公告)号：US07558326B1
公开(公告)日：2009-07-07
申请号：US09954663
申请日：2001-09-12
申请人： James D. Lyle , Gyudong Kim , Min-Kyu Kim , Ken-Sue Tan , Paul Daniel Wolf , William C. Altmann , Russel A. Martin
发明人： James D. Lyle , Gyudong Kim , Min-Kyu Kim , Ken-Sue Tan , Paul Daniel Wolf , William C. Altmann , Russel A. Martin
IPC分类号： H04B14/06 , H04N7/04
CPC分类号： H04L1/0057 , G09G5/006 , H04L1/203 , H04L1/206 , H04L25/49 , H04N19/89
摘要： A communication system including a transmitter, a receiver, and a TMDS-like link, in which video data and auxiliary data (typically including timing data associated with other auxiliary data) are transmitted from the transmitter to the receiver, or in which video data are transmitted over the link from the transmitter to the receiver, and auxiliary data (typically including timing data associated with other auxiliary data) are transmitted from the receiver to the transmitter. In typical embodiments the auxiliary data include one or more streams of audio data. Other aspects are transmitters and receivers for use in such a system, methods for sending auxiliary data and video data over a TMDS-like link, methods for transmitting and recovering clocks for auxiliary data transmitted over such a link, methods for synchronizing auxiliary data transmitted over such a link with video data transmitted over such a link, and methods for generating clocks having frequency closely matching the rate at which the auxiliary data are transmitted over such a link.
摘要翻译：包括发射机，接收机和类似TMDS的链路的通信系统，其中视频数据和辅助数据（通常包括与其他辅助数据相关联的定时数据）从发射机发送到接收机，或者哪个视频数据是通过从发射机到接收机的链路传输，并且辅助数据（通常包括与其他辅助数据相关联的定时数据）从接收机发射到发射机。在典型实施例中，辅助数据包括一个或多个音频数据流。其他方面是用于这种系统的发射机和接收机，用于通过类似TMDS的链路发送辅助数据和视频数据的方法，用于发送和恢复通过这种链路传输的辅助数据的时钟的方法，用于同步传输的辅助数据的方法与通过这种链路发送的视频数据的这种链接，以及用于产生具有与辅助数据通过这种链路发送的速率非常匹配的频率的时钟的方法。

35. 发明授权

US07158593B2 Combining a clock signal and a data signal 有权
标题翻译：组合时钟信号和数据信号
公开(公告)号：US07158593B2
公开(公告)日：2007-01-02
申请号：US10099533
申请日：2002-03-15
申请人： Gyudong Kim , Ook Kim , Min-Kyu Kim , Bruce Kim , Seung Ho Hwang
发明人： Gyudong Kim , Ook Kim , Min-Kyu Kim , Bruce Kim , Seung Ho Hwang
IPC分类号： H04L7/00
CPC分类号： H04L25/4902 , G09G5/006 , H04L5/06 , H04L7/0008 , H04L7/0054 , H04L7/027
摘要： A method of transmitting data in a system including at least one data channel and a separate clock channel is disclosed. The method involves combining a clock signal to be transmitted on the clock channel with a data signal to generate a combined clock and data signal. In one embodiment, the data signal has been generated from data words using an encoding scheme that shifts an energy spectrum of the data signal away from an energy spectrum of the clock signal. In another embodiment, the clock signal has a plurality of pulses each having a front edge and a back edge, and the data signal is modulated onto the clock signal by moving at least one edge (i.e. front or back or both) of the plurality of pulses, thereby to create a combined clock and data signal.
摘要翻译：公开了一种在包括至少一个数据信道和单独的时钟信道的系统中发送数据的方法。该方法包括将要在时钟信道上发送的时钟信号与数据信号组合以产生组合的时钟和数据信号。在一个实施例中，数据信号已经使用使数据信号的能谱偏离时钟信号的能谱的编码方案从数据字生成。在另一个实施例中，时钟信号具有多个脉冲，每个脉冲具有前沿和后沿，并且数据信号通过移动多个脉冲的至少一个边缘（即，前面或背面或两者）被调制到时钟信号上脉冲，从而创建一个组合的时钟和数据信号。

36. 发明授权

US07058121B1 Logic gates including diode-connected metal-oxide-semiconductor field-effect transistors (MOSFETS) to control input threshold voltage levels and switching transients of output logic signals 有权
标题翻译：包括二极管连接的金属氧化物半导体场效应晶体管（MOSFET）的逻辑门，用于控制输入阈值电压电平和输出逻辑信号的切换瞬变
公开(公告)号：US07058121B1
公开(公告)日：2006-06-06
申请号：US09989647
申请日：2001-11-20
申请人： Gyudong Kim , Min-Kyu Kim
发明人： Gyudong Kim , Min-Kyu Kim
IPC分类号： H04B1/38
CPC分类号： H04L5/1423
摘要： Logic gates are provided that include a diode-connected metal-oxide-semiconductor field-effect transistor (MOSFET) to produce a gate threshold voltage that differs from a mid-supply voltage level, while providing symmetry in the switching transients of the output logic signals. In one embodiment, the logic gate is a NAND gate. Use of a diode-connected n-type MOSFET in a ground path produces a threshold voltage level higher than the mid-supply voltage level. Use of a diode-connected p-type MOSFET in a supply voltage path produces a threshold voltage level lower than the mid-supply voltage level. In another embodiment, the logic gate is a NOR gate. Use of a diode-connected n-type MOSFET in a ground path produces a threshold voltage level higher than the mid-supply voltage level. Use of a diode-connected p-type MOSFET in a supply voltage path produces a threshold voltage level lower than the mid-supply voltage level.
摘要翻译：提供逻辑门，其包括二极管连接的金属氧化物半导体场效应晶体管（MOSFET），以产生不同于中间电源电压电平的栅极阈值电压，同时在输出逻辑信号的开关瞬变中提供对称性。在一个实施例中，逻辑门是NAND门。在接地路径中使用二极管连接的n型MOSFET产生高于中间电源电压电平的阈值电压电平。在电源电压路径中使用二极管连接的p型MOSFET产生低于中间电源电压电平的阈值电压电平。在另一个实施例中，逻辑门是NOR门。在接地路径中使用二极管连接的n型MOSFET产生高于中间电源电压电平的阈值电压电平。在电源电压路径中使用二极管连接的p型MOSFET产生低于中间电源电压电平的阈值电压电平。

37. 发明授权

US07031858B1 Method and circuit for DC measurement of phase uniformity of multi-phase clocks 有权
标题翻译：多相时钟相位均匀性的直流测量方法和电路
公开(公告)号：US07031858B1
公开(公告)日：2006-04-18
申请号：US10439446
申请日：2003-05-16
申请人： Eric Lee , Gyudong Kim
发明人： Eric Lee , Gyudong Kim
IPC分类号： G01R13/00
CPC分类号： G01R31/31725 , G01R31/3016 , G01R31/31727
摘要： Methods and circuits for measuring clock phase uniformity of multi-phase clock set, including by generating at least one DC phase difference signal such that the DC phase difference signal is, or the DC phase difference signals are, indicative of the phase difference between the clocks of each of multiple pairs of clocks of the clock set, and methods and circuitry for generating such DC phase difference signals. Preferably, multiplexer circuitry asserts to DC signal generation circuitry any selected one of a number of pairs of clocks of the clock set, and the DC signal generation circuitry includes logic (for generating a binary signal in response to each clock pair) and a low pass filter for generating a DC phase difference signal in response to the binary signal. Other aspects are receivers and transmitters that include circuitry for generating at least one DC phase difference signal, and systems including at least one such transmitter (or receiver) and a link (e.g., a multi-channel or single-channel serial link) coupled thereto.
摘要翻译：用于测量多相时钟组的时钟相位均匀性的方法和电路，包括通过产生DC相位差信号至少一个DC相位差信号或DC相位差信号来表示时钟之间的相位差时钟组的多对时钟中的每一对，以及用于产生这种DC相位差信号的方法和电路。优选地，多路复用器电路向DC信号产生电路断言时钟组的多对时钟对中的所选择的一个，并且DC信号产生电路包括逻辑（用于响应于每个时钟对而产生二进制信号）和低通滤波器，用于响应于二进制信号产生DC相位差信号。其他方面是包括用于产生至少一个DC相位差信号的电路的接收机和发射机，以及包括至少一个这样的发射机（或接收机）和耦合到其的链路（例如，多信道或单信道串行链路）的系统。

38. 发明授权

US06985005B1 Differential amplifiers using asymmetric transfer characteristics to suppress input noise in output logic signals 有权
标题翻译：使用非对称传输特性的差分放大器抑制输出逻辑信号中的输入噪声
公开(公告)号：US06985005B1
公开(公告)日：2006-01-10
申请号：US09989487
申请日：2001-11-20
申请人： Gyudong Kim , Min-Kyu Kim
发明人： Gyudong Kim , Min-Kyu Kim
IPC分类号： H03K17/16
CPC分类号： H04L25/0292 , H03F3/45179 , H03F3/45632 , H03K5/2481 , H04L5/18 , H04L25/0272
摘要： An output amplifier is provided for use in a bidirectional communications interface, for example, connecting a transmitter and a receiver to a transmission line. The output amplifier includes a differential amplifier pair connected to output circuitry. The differential amplifier pair receives differential data signal pairs from each of a transmission line and a transmitter. The output circuitry receives signals from the differential amplifier pair and, in response, forms single-ended output logic signals. The output amplifier suppresses electronic input noise throughput using an asymmetric transfer characteristic that offsets output signal logic levels with respect to input noise signal levels. The asymmetric transfer characteristic is produced by skewing a transfer characteristic of the differential amplifier pair using an asymmetrical transistor configuration at an output side of the differential amplifier pair. The output logic signals represent data received on the transmission line, and are provided to the receiver.
摘要翻译：输出放大器被提供用于双向通信接口，例如将发射器和接收器连接到传输线。输出放大器包括连接到输出电路的差分放大器对。差分放大器对从传输线和发送器中的每一个接收差分数据信号对。输出电路从差分放大器对接收信号，作为响应，形成单端输出逻辑信号。输出放大器使用偏移相对于输入噪声信号电平的输出信号逻辑电平的非对称传输特性来抑制电子输入噪声吞吐量。非对称传输特性是通过在差分放大器对的输出侧使用不对称晶体管配置来歪斜差分放大器对的传输特性而产生的。输出逻辑信号表示在传输线上接收的数据，并提供给接收机。

39. 发明授权

US6144242A Controllable delays in multiple synchronized signals for reduced electromagnetic interference at peak frequencies 有权
标题翻译：多个同步信号中的可控延迟，用于降低峰值频率时的电磁干扰
公开(公告)号：US6144242A
公开(公告)日：2000-11-07
申请号：US148815
申请日：1998-09-04
申请人： Deog-Kyoon Jeong , Gyudong Kim , David D. Lee
发明人： Deog-Kyoon Jeong , Gyudong Kim , David D. Lee
IPC分类号： H04B3/04 , H04L25/08 , H03H11/26
CPC分类号： H04L25/085
摘要： Multiple controllable delays reduce EMI radiated during the transmission of multiple synchronized signals. Each controllable delay introduces a controlled delay into a corresponding signal being transmitted. The controlled delay is such that the combined strength of the multiple signals at peak frequencies is substantially reduced. This results in reduced EMI radiation at those peak frequencies.
摘要翻译：多个可控延迟降低了传输多个同步信号期间的EMI辐射。每个可控延迟将受控的延迟引入正在传输的相应信号。受控的延迟使得峰值频率处的多个信号的组合强度显着降低。这导致在那些峰值频率下降低了EMI辐射。

40. 发明申请

US20110193579A1 DETERMINATION OF PHYSICAL CONNECTIVITY STATUS OF DEVICES BASED ON ELECTRICAL MEASUREMENT 有权
标题翻译：基于电气测量的装置的物理连接状态的确定
公开(公告)号：US20110193579A1
公开(公告)日：2011-08-11
申请号：US13021958
申请日：2011-02-07
申请人： Jason Wong , Gyudong Kim
发明人： Jason Wong , Gyudong Kim
IPC分类号： G01R27/08
CPC分类号： G01R31/021 , G06F11/3055 , G06F11/3485 , G06F11/349
摘要： Embodiments of the invention are generally directed to determination of physical connectivity status of devices based on electrical measurement. An embodiment of a method includes discovering a connection of a first device with a second device, and performing an electrical measurement of the second device by the first device via the connection between the first device and the second device, where performing the electrical measurement includes sensing by the first device of an element of the second device. The method further includes, if the sensing by the first device fails to detect the element of the second device and a predetermined condition for the electrical measurement is enabled, then determining by the first device that the connection with the second device has been lost.
摘要翻译：本发明的实施例通常涉及基于电测量来确定设备的物理连接状态。一种方法的实施例包括发现第一设备与第二设备的连接，以及由第一设备经由第一设备和第二设备之间的连接执行第二设备的电测量，其中执行电测量包括感测通过第二装置的元件的第一装置。该方法还包括：如果第一设备的感测不能检测到第二设备的元件，并且启用用于电测量的预定条件，则由第一设备确定与第二设备的连接已经丢失。

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