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31. 发明申请

US20120045147A1 IMAGE CONVERSION METHOD, CONVERSION DEVICE, AND DISPLAY SYSTEM 有权
标题翻译：图像转换方法，转换装置和显示系统
公开(公告)号：US20120045147A1
公开(公告)日：2012-02-23
申请号：US13284227
申请日：2011-10-28
申请人： Yuan Liu , Song Zhao , Jing Wang
发明人： Yuan Liu , Song Zhao , Jing Wang
IPC分类号： G06K9/36
CPC分类号： G06T3/40 , G06K9/325
摘要： An image conversion method, a conversion device, and a display system are provided in the embodiments of the present invention. The image conversion method includes: performing word area detection on an image to acquire a detected word area; and performing conversion processing on the image according to the word area to acquire a converted image that has an aspect ratio different from that of an unconverted image. The conversion device includes: a detection unit, configured to perform word area detection on an image to acquire a detected word area; and a conversion unit, configured to perform conversion processing on the image according to the word area to acquire a converted image that has an aspect ratio different from that of an unconverted image. In this way, an important content area of the image may be retained and clearly displayed.
摘要翻译：在本发明的实施例中提供了图像转换方法，转换装置和显示系统。图像转换方法包括：对图像执行字区域检测以获取检测到的字区域; 以及根据所述单词区域对所述图像执行转换处理，以获取具有与未转换图像的宽高比不同的宽高比的转换图像。转换装置包括：检测单元，被配置为对图像执行字区域检测以获取检测到的字区域; 以及转换单元，被配置为根据所述单词区域对所述图像执行转换处理，以获取具有与未转换图像的宽高比不同的纵横比的转换图像。以这种方式，图像的重要内容区域可以被保留和清楚地显示。

32. 发明授权

US08101476B2 Stress memorization dielectric optimized for NMOS and PMOS 有权
标题翻译：针对NMOS和PMOS优化的应力记忆电介质
公开(公告)号：US08101476B2
公开(公告)日：2012-01-24
申请号：US12541335
申请日：2009-08-14
申请人： Kanan Garg , Haowen Bu , Mahalingam Nandakumar , Song Zhao
发明人： Kanan Garg , Haowen Bu , Mahalingam Nandakumar , Song Zhao
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/3185 , H01L21/823807 , H01L29/7843 , H01L29/7845
摘要： A method for forming a tensile SiN stress layer for stress memorization enhancement of NMOS transistors with a high Si—H/N—H bond ratio that does not degrade PMOS transistors. A CMOS integrated circuit is processed through a NMOS source and drain implant but not through NMOS source and drain anneal. A SiN dielectric layer is deposited such that an area ratio of a Si—H peak to a N—H peak in a FTIR spectrum is greater than 7 and a tensile stress of the SiN dielectric is greater than 150 MPa. The CMOS integrated circuit is annealed after deposition of the SiN dielectric layer and the SiN dielectric layer is removed from at least a part of the integrated circuit.
摘要翻译：一种用于形成具有不降低PMOS晶体管的高Si-H / N-H键比的NMOS晶体管的应力记忆增强的拉伸SiN应力层的方法。 CMOS集成电路通过NMOS源极和漏极注入而不是通过NMOS源极和漏极退火进行处理。沉积SiN电介质层，使得FTIR光谱中Si-H峰与N-H峰的面积比大于7，并且SiN电介质的拉伸应力大于150MPa。在沉积SiN电介质层之后对CMOS集成电路进行退火，并且从集成电路的至少一部分去除SiN介电层。

33. 发明申请

US20090079008A1 CMOS Fabrication Process 有权
标题翻译： CMOS制作工艺
公开(公告)号：US20090079008A1
公开(公告)日：2009-03-26
申请号：US12209270
申请日：2008-09-12
申请人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
发明人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/823814 , H01L29/1087 , H01L29/7847
摘要： Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.
摘要翻译：对于PMOS晶体管，超高温（UHT）超过1200℃退火少于100毫秒会减少范围位错的终止，但与用于增强NMOS导通电流的应力记忆技术（SMT）层不兼容。本发明首先通过使用碳共注入形成PSD并且在植入NSD并沉积SMT层之前对其进行UHT退火来逆转形成NMOS的常规顺序。实现了低于100cm-2的PSD空间电荷区域的范围位错密度的结束。来自SMT层的PMOS中的拉伸应力显着降低。 PLDD还可以进行UHT退火以减少靠近PMOS沟道的范围位错的结束。

34. 发明授权

US07216310B2 Design method and system for optimum performance in integrated circuits that use power management 有权
标题翻译：使用电源管理的集成电路中的最佳性能设计方法和系统
公开(公告)号：US07216310B2
公开(公告)日：2007-05-08
申请号：US10993815
申请日：2004-11-19
申请人： Amitava Chatterjee , David Barry Scott , Theodore W. Houston , Song Zhao , Shaoping Tang , Zhiqiang Wu
发明人： Amitava Chatterjee , David Barry Scott , Theodore W. Houston , Song Zhao , Shaoping Tang , Zhiqiang Wu
IPC分类号： G06F17/50 , G11C5/14 , H03K3/01 , G05F1/10
CPC分类号： G06F17/505
摘要： The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory transistors. The method further comprises determining (115) a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining (120) a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used (125) to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting (130) the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.
摘要翻译：本发明提供一种设计电路的方法（100）。该方法包括指定（105）存储晶体管和逻辑晶体管的设计参数，并选择（110）存储晶体管的测试保持模式偏置电压。所述方法还包括在所述测试保持模式偏置电压下确定（115）保持模式漏电流和所述设计参数的第一关系，并获得（120）所述有源模式驱动电流与所述设计参数的第二关系。使用第一和第二关系（125）来评估是否存在保持模式漏电流和有源模式驱动电流在预定电路规范内的设计参数值的范围。该方法还包括调整（130）测试保持模式偏置电压，并重复确定和使用如果保持模式总泄漏电流或有源模式驱动电流超出预定电路规范。

35. 发明申请

US20060189048A1 Method to strain NMOS devices while mitigating dopant diffusion for PMOS using a capped poly layer 有权
标题翻译：使用封端的多晶硅层减少PMOS器件的掺杂剂扩散的方法来应变NMOS器件
公开(公告)号：US20060189048A1
公开(公告)日：2006-08-24
申请号：US11060841
申请日：2005-02-18
申请人： Manoj Mehrotra , Lahir Adam , Song Zhao , Mahalingam Nandakumar
发明人： Manoj Mehrotra , Lahir Adam , Song Zhao , Mahalingam Nandakumar
IPC分类号： H01L21/84
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/6656 , H01L29/6659 , H01L29/7843 , Y10S438/902
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in active regions of a PMOS region (102). A first thermal process is performed that activates the formed source/drain regions and drives in implanted dopants (104). Subsequently, source/drain regions are formed in active regions of an NMOS region (106). Then, a capped poly layer is formed over the device (108). A second thermal process is performed (110) that causes the capped poly layer to induce strain into the channel regions of devices. Because of the first thermal process, unwanted dopant diffusion, particularly unwanted p-type dopant diffusion, during the second thermal process is mitigated.
摘要翻译：本发明通过提供制造方法来促进半导体制造，所述方法对设备的沟道区域施加拉伸应变，同时减轻不期望的掺杂剂扩散，这降低了器件性能。源极/漏极区形成在PMOS区（102）的有源区中。执行第一热处理，其激活所形成的源极/漏极区域和在注入的掺杂剂（104）中的驱动。随后，在NMOS区域（106）的有源区域中形成源极/漏极区域。然后，在器件（108）上形成封端的多晶硅层。执行第二热处理（110），其使得封端的多晶硅层引入器件的沟道区域的应变。由于第一热处理，减少了在第二热处理期间不期望的掺杂剂扩散，特别是不期望的p型掺杂剂扩散。

36. 发明授权

US07029967B2 Silicide method for CMOS integrated circuits 有权
标题翻译： CMOS集成电路的硅化法
公开(公告)号：US07029967B2
公开(公告)日：2006-04-18
申请号：US10896599
申请日：2004-07-21
申请人： Song Zhao , Sue E. Crank , Amitava Chatterjee , Kaiping Liu , Jiong-Ping Lu , Donald S. Miles , Duofeng Yue , Lance S. Robertson
发明人： Song Zhao , Sue E. Crank , Amitava Chatterjee , Kaiping Liu , Jiong-Ping Lu , Donald S. Miles , Duofeng Yue , Lance S. Robertson
IPC分类号： H01L21/8238 , H01L21/331
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/28518 , H01L21/823835 , H01L29/665
摘要： A method for forming metal silicide regions in source and drain regions (160, 170) is described. Prior to the thermal annealing of the source and drain regions (160, 170), germanium is implanted into a semiconductor substrate adjacent to sidewall structures (90, 95) formed adjacent gate structures (60, 70). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (160, 170). Following thermal annealing of the source and drain regions (160, 170), the implanted germanium prevents the formation of metal silicide spikes.
摘要翻译：描述了在源区和漏区（160,170）中形成金属硅化物区域的方法。在源极和漏极区域（160,170）的热退火之前，将锗注入到与栅极结构（60,70）相邻形成的侧壁结构（90,95）附近的半导体衬底中。植入的锗物质在半导体衬底中的位置将与源区和漏区（160,170）重叠。在源极和漏极区域（160,170）的热退火之后，注入的锗防止形成金属硅化物尖峰。

37. 发明申请

US20060019478A1 Silicide method for CMOS integrated circuits 有权
公开(公告)号：US20060019478A1
公开(公告)日：2006-01-26
申请号：US10896599
申请日：2004-07-21
申请人： Song Zhao , Sue Crank , Amitava Chatterjee , Kaiping Liu , Jiong-Ping Lu , Donald Miles , Duofeng Yue , Lance Robertson
发明人： Song Zhao , Sue Crank , Amitava Chatterjee , Kaiping Liu , Jiong-Ping Lu , Donald Miles , Duofeng Yue , Lance Robertson
IPC分类号： H01L21/28
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/28518 , H01L21/823835 , H01L29/665
摘要： A method for forming metal silicide regions in source and drain regions (160, 170) is described. Prior to the thermal annealing of the source and drain regions (160, 170), germanium is implanted into a semiconductor substrate adjacent to sidewall structures (90, 95) formed adjacent gate structures (60, 70). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (160, 170). Following thermal annealing of the source and drain regions (160, 170), the implanted germanium prevents the formation of metal silicide spikes.

38. 发明申请

US20050149887A1 Design method and system for optimum performance in integrated circuits that use power management 有权
标题翻译：使用电源管理的集成电路中的最佳性能设计方法和系统
公开(公告)号：US20050149887A1
公开(公告)日：2005-07-07
申请号：US10993815
申请日：2004-11-19
申请人： Amitava Chatterjee , David Scott , Theodore Houston , Song Zhao , Shaoping Tang , Zhiqiang Wu
发明人： Amitava Chatterjee , David Scott , Theodore Houston , Song Zhao , Shaoping Tang , Zhiqiang Wu
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory transistors. The method further comprises determining (115) a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining (120) a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used (125) to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting (130) the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.
摘要翻译：本发明提供一种设计电路的方法（100）。该方法包括指定（105）存储晶体管和逻辑晶体管的设计参数，并选择（110）存储晶体管的测试保持模式偏置电压。所述方法还包括在所述测试保持模式偏置电压下确定（115）保持模式漏电流和所述设计参数的第一关系，并获得（120）所述有源模式驱动电流与所述设计参数的第二关系。使用第一和第二关系（125）来评估是否存在保持模式漏电流和有源模式驱动电流在预定电路规范内的设计参数值的范围。该方法还包括调整（130）测试保持模式偏置电压，并重复确定和使用如果保持模式总泄漏电流或有源模式驱动电流超出预定电路规范。

39. 发明授权

US06822297B2 Additional n-type LDD/pocket implant for improving short-channel NMOS ESD robustness 有权
标题翻译：额外的n型LDD /袋式注入，用于改善短沟道NMOS ESD稳健性
公开(公告)号：US06822297B2
公开(公告)日：2004-11-23
申请号：US09876292
申请日：2001-06-07
申请人： Mahalingam Nandakumar , Song Zhao , Youngmin Kim
发明人： Mahalingam Nandakumar , Song Zhao , Youngmin Kim
IPC分类号： H01L2362
CPC分类号： H01L29/6659 , H01L27/0266 , H01L29/1083 , H01L29/7833
摘要： A short-channel NMOS transistor in a p-well, bordered laterally on each side by an isolation region and vertically by a channel stop region, has a n-source and a n-drain, each comprising a shallow region extending to the transistor gate and a deeper region recessed from the gate, and both having a depletion region when reverse biased. The shallow regions are surrounded in part by an enhanced p-doping implant pocket. The transistor further has in these regions of enhanced p-doping another region of a p-resistivity higher than the remainder of the semiconductor. These regions extend laterally approximately from the inner border of the respective shallow region to the inner border of the respective recessed region, and vertically from a depth just below the depletion regions of source and drain to approximately the top of the channel stop regions. According to the invention, these regions of higher p-type resistivity are created after gate definition by an ion implant of compensating n-doping, such as arsenic or phosphorus, using the same photomask already used for implants creating the extended source and drain and the pockets of enhanced p-doping. In an ESD event, these regions of higher resistivity increase the current gain of the parasitic lateral npn bipolar transistor and thus raise the current It2, which initiates the thermal breakdown with its destructive localized heating, thereby improving ESD robustness.
摘要翻译： p阱中的短沟道NMOS晶体管具有n源极和n沟道，每个包含延伸到晶体管栅极的浅区域，每个侧面由隔离区域横向限定并由沟道停止区域垂直地限定以及从栅极凹陷的较深区域，并且当反向偏置时都具有耗尽区域。浅区域部分地被增强的p掺杂注入口袋包围。晶体管还在这些增强的p掺杂区域中具有比半导体其余部分高的p电阻率的另一区域。这些区域大致从相应的浅区域的内部边界横向延伸到相应的凹陷区域的内部边界，并且从刚好在源极和漏极的耗尽区域的深度的深度垂直地延伸到接近通道停止区域的顶部。根据本发明通过使用已经用于形成扩展的源极和漏极的植入物的相同的光掩模，通过补偿n掺杂的离子注入（例如砷或磷）在栅极定义之后产生这些较高p型电阻率的区域，在ESD事件中，这些具有较高电阻率的区域增加了寄生横向npn双极晶体管的电流增益，从而提高了电流It2，从而使其具有破坏性的局部加热引起热击穿，从而提高了ESD鲁棒性。

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